JPS6155938A - Method for isoration of electronic element - Google Patents

Method for isoration of electronic element

Info

Publication number
JPS6155938A
JPS6155938A JP59177803A JP17780384A JPS6155938A JP S6155938 A JPS6155938 A JP S6155938A JP 59177803 A JP59177803 A JP 59177803A JP 17780384 A JP17780384 A JP 17780384A JP S6155938 A JPS6155938 A JP S6155938A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
deep trap
electronic elements
electrodes
layer including
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59177803A
Other languages
Japanese (ja)
Other versions
JPH0428144B2 (en
Inventor
Haruo Horimatsu
細松 春夫
Morio Wada
守夫 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP59177803A priority Critical patent/JPS6155938A/en
Publication of JPS6155938A publication Critical patent/JPS6155938A/en
Publication of JPH0428144B2 publication Critical patent/JPH0428144B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Abstract

PURPOSE:To isolate electronic elements easily without extending the intervals by forming the isolation zones of electronic elements out of the layer including a deep trap level produced by impurities or defects existing in the semiconductor substrate. CONSTITUTION:By chemical etching of a highly-resistant semiconductor substrate 30, a layer including a deep trap layer is formed in the vicinity of the surface of substrate 30. Nextly, by etching only the surface where barrier junction electrodes 1 are formed by Ar<+> ions, the layer including a deep trap level is removed and the layer including a deep trap level is left in the part except the plane on which the electrodes 1 are formed thereby forming isolation zones 10. After forming the isolation zones 10, the electrodes 1 are formed by Schottky barrier junction in the part where the deep trap level is removed and the electrodes composed electronic elements together with an ohmic electrode 2 formed in another plane.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体基板上にpn接合またはショットキ・バ
リア接合などにより形成する複数の電子素子間の分離特
性の改善に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to improvement of isolation characteristics between a plurality of electronic elements formed on a semiconductor substrate by a pn junction, a Schottky barrier junction, or the like.

〈従来技術〉 半導体L4板上に薄膜を形成し、ダイオードやトランジ
スタなどの電子素子を形成する場合、小さな面積に可能
な限り多くの電子素子を形成した方が経済的に有利であ
る。
<Prior Art> When forming a thin film on the semiconductor L4 board to form electronic elements such as diodes and transistors, it is economically advantageous to form as many electronic elements as possible in a small area.

従来半導体基板上に電子素子を形成1゛る方法として、
第2図〜第4図に断面図にて示すものが知られている。
Conventionally, as a method for forming electronic elements on a semiconductor substrate,
What is shown in cross-sectional views in FIGS. 2 to 4 is known.

第2図において、3は半導体基板でその一方の面にショ
ットキ・バリア接合rPi(ilが一定の間隔dを隔て
て形成され、他方の面にオーミック接合Fi極2が全面
に形成され、Iyl配電(蛎1゜2間に電子素子を構成
している。上記従来例においては、各電子素子間の分離
は半導体基板3を高抵抗半導体とし、電子素子間の距離
を大きくとって各電子素子間の抵抗が大きくなるように
して行なっていた。このような構造の場合、第5図の断
面図にて示ず如く、半導体基板の抵抗を大きくしてa密
度に電子素子を形成しようとしても高抵抗半導体のキャ
リアm度が低くなるに従い空乏FI8が拡大し、この空
乏1!!78が隣接の電子素子と接触するので、各電子
素子間の間隔を小さくすることが難しく、経済的に不利
であるとともに各電子素子の配置やに9計上も問題があ
る。
In Fig. 2, reference numeral 3 denotes a semiconductor substrate, on one side of which Schottky barrier junctions rPi(il) are formed at a constant interval d, and on the other side, an ohmic junction Fi pole 2 is formed over the entire surface, and Iyl power distribution. (Electronic elements are configured between 1° and 2 mm.) In the conventional example described above, the separation between each electronic element is achieved by using the semiconductor substrate 3 as a high-resistance semiconductor and keeping a large distance between each electronic element. In such a structure, as shown in the cross-sectional view of Fig. 5, even if an attempt is made to increase the resistance of the semiconductor substrate to form an electronic element with a high a-density, As the carrier m degree of the resistive semiconductor decreases, the depletion FI8 expands, and this depletion 1!!78 comes into contact with adjacent electronic elements, making it difficult to reduce the distance between each electronic element, which is economically disadvantageous. There is also a problem with the arrangement of each electronic element.

第3図に示す従来例は半導体基板3の一方の面にエピタ
キシャル層4を形成し、この上にシミットキ・バリア接
合後エピタキシャルF′J4をメI)′エツチングして
各電子素子間の分離を行なって他方の面に形成したオー
ミック電極2との間で電子素子をjf4成する方法であ
るが、半導体基板上にエピタキシャル層を形成しその表
面にメサエッチングを行なう技術が各硬化合物半導体で
tよ確立されておらずInな場合が多い。
In the conventional example shown in FIG. 3, an epitaxial layer 4 is formed on one surface of a semiconductor substrate 3, and an epitaxial layer F'J4 is etched on this layer after Schmittsky barrier bonding to separate each electronic element. This is a method of forming an electronic element between the ohmic electrode 2 formed on the other surface of the semiconductor substrate, but the technique of forming an epitaxial layer on a semiconductor substrate and performing mesa etching on its surface is the most common method for each cured compound semiconductor. It is not well established and is often introductory.

第4図に示す従来例は半導体基板3の一方の面にエピタ
キシャルVI4を形成し、このエピタキシャルll!1
4を拡散Fi15により分離し他方の面に形成したオー
ミック電極2との間で電子素子を構成する方法で、例え
ばエピタキシャル層が0形工ピタキシヤル層であれば拡
散層はp十拡散層として形成する。この場合、ショット
キ・バリア接合電極1の形成は拡散層5を形成する前で
も後でもよい。
In the conventional example shown in FIG. 4, an epitaxial layer VI4 is formed on one surface of a semiconductor substrate 3, and this epitaxial layer ll! 1
4 is separated by a diffusion film 15 and an ohmic electrode 2 formed on the other surface forms an electronic device. For example, if the epitaxial layer is a 0-type epitaxial layer, the diffusion layer is formed as a p+ diffusion layer. . In this case, the Schottky barrier junction electrode 1 may be formed before or after the diffusion layer 5 is formed.

しかしながら、各種化合物半導体に拡散1!15を形成
するための熱処理工程やドーパントの還択は技術的に確
立されておらず困難な場合が多い。
However, the heat treatment process and dopant selection for forming diffusion 1!15 in various compound semiconductors are not technically established and are often difficult.

〈発明の目的〉 本発明は上記従来例の問題点に鑑みてなされたもので、
各電子素子間の間隅を大きくすることなく簡単に分離す
ることが可能な分離法を提供することを目的とする。
<Object of the invention> The present invention has been made in view of the problems of the above-mentioned conventional example.
It is an object of the present invention to provide a separation method that allows easy separation without increasing the space between electronic elements.

〈発明のM4成〉 この目的を達成する本発明の構成は、半導体基板上にp
n接合またはショットキ・バリア接合等により複数の電
子素子を形成する際の電子素子の分離法において、前記
電子素子の分離帯を半導体基板中に存tfする欠陥、不
純物によって生じる深いトラップ単位を含む層により形
成したことを構成上の特徴とするものである。
<M4 configuration of the invention> The configuration of the present invention that achieves this objective is to
In a method for separating electronic devices when a plurality of electronic devices are formed using n-junctions or Schottky barrier junctions, etc., the separation band of the electronic device is formed into a layer containing deep trap units caused by defects and impurities existing in the semiconductor substrate. Its structural feature is that it is formed by.

〈実施例〉 第1図は本発明の一実施例を示すもので、30は例えば
p形Cd Te結品からなる高抵抗半導体である。10
は分離帯で、高抵抗半導体30の表面に形成された欠陥
、不純物によって生じる深いトラップ単位を含む層によ
り形成されている。この欠陥、不純物によって生じる深
いトラップ単位を含むli!110は通常は半導体基板
の欠陥として極力除かれるべきものであるが、本発明に
おいてはこの欠陥を積極的に利用して分離帯10を形成
するものである。まず、高抵抗半導体基板30を化学エ
ツチングして、基板30の表面近くに深いトラップ単位
を含む層を形成し、次にショットキ・バリア接合W1極
1が形成される而のみをAr+イオンによってエツチン
グして深いトラップ順位を含む瘤を取り除き、ショット
キ・バリア接合電極1が形成される面以外に深い1−ラ
ップ順位を含む層を残して分m (l) 10を形成す
る。上記のように分離帯10を形成した侵、A1.Pt
簀を深いトラップ準位を取り除いた部分にショットキ・
バリア接合して電極1を形成し、他方の面に形成したオ
ーミック電極2との闇で電子素子を構成する。
<Embodiment> FIG. 1 shows an embodiment of the present invention, in which 30 is a high-resistance semiconductor made of, for example, a p-type CdTe crystal. 10
is a separation band, which is formed by a layer containing deep trap units caused by defects and impurities formed on the surface of the high-resistance semiconductor 30. This defect, li!, contains deep trap units caused by impurities! Normally, the defects 110 should be removed as much as possible as defects in the semiconductor substrate, but in the present invention, this defect is actively utilized to form the separation zone 10. First, the high-resistance semiconductor substrate 30 is chemically etched to form a layer containing deep trap units near the surface of the substrate 30, and then only the portion where the Schottky barrier junction W1 pole 1 is formed is etched with Ar+ ions. Then, the layer containing the deep trap order is removed, and the layer containing the deep 1-lap order is left on the surface other than the surface where the Schottky barrier junction electrode 1 is formed, and a layer m (l) 10 is formed. A1. Pt
A Schottky filter is applied to the part where the deep trap level is removed.
An electrode 1 is formed by barrier bonding, and together with an ohmic electrode 2 formed on the other surface, an electronic element is constructed.

この方法によれば、ショットキ・バリア接合によって半
導体基板30に形成される空乏層の拡大が分離帯10に
よって阻止され隣接する電子素子が接触71ることがな
い。
According to this method, the expansion of the depletion layer formed in the semiconductor substrate 30 by the Schottky barrier junction is prevented by the separation band 10, and the adjacent electronic elements do not come into contact 71.

なilj半々半々板基板に形成Jる電子素子としCは、
光検出素子、β線検出素子、χFA検出検出索子チヤン
ネル形とし−C形成する等、各種利用が可能である。ま
た、本実施例においては、電子素子を構成する一方の電
極をショットキ・バリア接合電極として説明したがこの
電(折はpH接合電極として構成してもよい。
Assuming that an electronic device is formed on a half-half board, C is
Various uses are possible, such as a photodetection element, a β-ray detection element, a χFA detection channel type, and a -C formation. Further, in this embodiment, one electrode constituting the electronic element is described as a Schottky barrier junction electrode, but this electrode may also be constructed as a pH junction electrode.

〈発明の効果ン 以上、実施例とともに具、体内に説明したように、本発
明によれば、筒中な方法で分離帯を形成Jることができ
、半導体上に高密度に電子素子を形成することができ経
済上の効果は大である。
<Effects of the Invention> As explained above in conjunction with the embodiments, according to the present invention, a separation zone can be formed by an in-house method, and electronic elements can be formed in a high density on a semiconductor. The economic effect is great.

【図面の簡単な説明】 第1図は本発明の一実施例を示す半導体基板の断面図、
第2図〜第4図は従来例を示す半導体基板の断面図、第
5図は第2図の従来例において空乏層が接触した状態を
示す断面図である。 1・・・ショットキ・バリア電極、2・・・オーミック
接合電極、10・・・分離帯、30・・・高(■抗生導
体。
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view of a semiconductor substrate showing an embodiment of the present invention;
2 to 4 are cross-sectional views of a semiconductor substrate showing a conventional example, and FIG. 5 is a cross-sectional view showing a state in which the depletion layers are in contact with each other in the conventional example of FIG. 1... Schottky barrier electrode, 2... Ohmic junction electrode, 10... Separation band, 30... High (■Antibiotic conductor.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上にpn接合またはショットキ・バリア接合
などにより複数の電子素子を形成する際の電子素子の分
離法において、前記電子素子の分離帯を半導体基板中に
存在する欠陥、不純物によって生じる深いトラップ準位
を含む層により形成したことを特徴とする電子素子の分
離法。
In a method for separating electronic devices when a plurality of electronic devices are formed on a semiconductor substrate using pn junctions or Schottky barrier junctions, separation bands of the electronic devices are separated into deep trap states caused by defects and impurities existing in the semiconductor substrate. 1. A method for separating an electronic device, characterized in that the electronic device is formed by a layer containing an active layer.
JP59177803A 1984-08-27 1984-08-27 Method for isoration of electronic element Granted JPS6155938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59177803A JPS6155938A (en) 1984-08-27 1984-08-27 Method for isoration of electronic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59177803A JPS6155938A (en) 1984-08-27 1984-08-27 Method for isoration of electronic element

Publications (2)

Publication Number Publication Date
JPS6155938A true JPS6155938A (en) 1986-03-20
JPH0428144B2 JPH0428144B2 (en) 1992-05-13

Family

ID=16037358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59177803A Granted JPS6155938A (en) 1984-08-27 1984-08-27 Method for isoration of electronic element

Country Status (1)

Country Link
JP (1) JPS6155938A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5026573A (en) * 1988-03-02 1991-06-25 Tokai Regional Fishery Research Laboratory Method for the preparation of leached fish flesh and product thereof
US5196221A (en) * 1990-02-08 1993-03-23 Rutgers University Process for inhibiting the growth of bacteria on seafood

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837232A (en) * 1971-09-15 1973-06-01
JPS5658226A (en) * 1979-10-17 1981-05-21 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS5662882A (en) * 1979-10-30 1981-05-29 Agency Of Ind Science & Technol Feeding of raw material to pyrolysis plant and its device
JPS57177537A (en) * 1981-04-24 1982-11-01 Matsushita Electric Ind Co Ltd Isolation of semiconductor element
JPS5860557A (en) * 1981-10-06 1983-04-11 Nec Corp Forming method for high-resistance layer of gallium arsenide

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837232A (en) * 1971-09-15 1973-06-01
JPS5658226A (en) * 1979-10-17 1981-05-21 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS5662882A (en) * 1979-10-30 1981-05-29 Agency Of Ind Science & Technol Feeding of raw material to pyrolysis plant and its device
JPS57177537A (en) * 1981-04-24 1982-11-01 Matsushita Electric Ind Co Ltd Isolation of semiconductor element
JPS5860557A (en) * 1981-10-06 1983-04-11 Nec Corp Forming method for high-resistance layer of gallium arsenide

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5026573A (en) * 1988-03-02 1991-06-25 Tokai Regional Fishery Research Laboratory Method for the preparation of leached fish flesh and product thereof
US5196221A (en) * 1990-02-08 1993-03-23 Rutgers University Process for inhibiting the growth of bacteria on seafood

Also Published As

Publication number Publication date
JPH0428144B2 (en) 1992-05-13

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