JPS5848468A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5848468A
JPS5848468A JP14594681A JP14594681A JPS5848468A JP S5848468 A JPS5848468 A JP S5848468A JP 14594681 A JP14594681 A JP 14594681A JP 14594681 A JP14594681 A JP 14594681A JP S5848468 A JPS5848468 A JP S5848468A
Authority
JP
Japan
Prior art keywords
semiconductor
field effect
active layer
gate electrode
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14594681A
Other languages
Japanese (ja)
Inventor
Yasunobu Ishii
康信 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14594681A priority Critical patent/JPS5848468A/en
Publication of JPS5848468A publication Critical patent/JPS5848468A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV

Abstract

PURPOSE:To obtain uniform active semiconductor layers by forming the active semiconductor layers constituting two field effect transistors by the same semiconductors with the same thickness and the same impurity concentration. CONSTITUTION:The active semiconductor layer 1A which constitutes the field effect transistor 8A and the active semiconductor layer 1B which constitutes the field effect transistor 11B are formed by the same semiconductors under the conditions with the same thickness, the same impurity concentration, and the like. However, the gate electrode 6A of the field effect transistor 8A and the gate electrode 6B of the field effect transistor 11B are made of different gate electrode materials. A Schottky junciton 7A is formed between the gate electrode 6A and the active semiconductor layer 1A, and a homogenious P-N junction 10B is formed between the gate electrode 9B and the active semiconductor layer 1B. Therefore, the Schottky junction 7A and the homogeneous P-N junction 10B have the different heights of barriers. Thus the field effect transistors 8A and 11B have different pinchoff voltages.

Description

【発明の詳細な説明】 本発明は、少くとも第1及び第2の半導体能動層がそれ
等に共通の牛絶縁性−半導体基板上に形成され、その第
1の半導体能動層と、その第1の半導体能動層に、上記
半絶縁性半導体基板側とは反対側に於てオーiックに連
結せるW41のソース電極及びIRlのドレイン電極と
、上記lR1の半導体゛能動層に、上記半絶縁性半導体
基板側とは反対側に於ける上記第1のソース電極及び上
記第1のドレイン電極間に於て、上記第1の半導体能動
層との間でショットキ接合又はPN接合を形成すべく連
結せるW41のゲート−極を含んで第1の電界効果トラ
ンジスタが形成され、上記第2の半導体能動層と、その
M2の半導体能動層に、上記半絶縁性半導体基&貴とは
反対側に於てオーイックに連結せる第2のソース電極及
び第2のドレイン電極と、上記第2の半導体能vIp1
1に、上記半絶縁性半導体基板側とは反対側に於ける上
記第2のソース電極及び上記纂2のドレイン電極間に於
て、上記第2の半導体能動層との間でショットキ接合又
はPN接合を形成すべく連結せる第2のゲート電極とを
含んで第1の電界効果トランジスタとは異なるピンチオ
フ電圧を有する第2の電界効果トランジスタが構成され
てなる構成を有する半導体装置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides that at least a first and a second semiconductor active layer are formed on a common insulating-semiconductor substrate; A source electrode of W41 and a drain electrode of IRl are electrically connected to the semiconductor active layer of IR1 on the side opposite to the semi-insulating semiconductor substrate side, and To form a Schottky junction or a PN junction with the first semiconductor active layer between the first source electrode and the first drain electrode on the side opposite to the insulating semiconductor substrate side. A first field effect transistor is formed including the gate-pole of W41 connected to the second semiconductor active layer and the semiconductor active layer of M2, on the opposite side from the semi-insulating semiconductor base & a second source electrode and a second drain electrode that are ohically connected to each other; and the second semiconductor capacitor vIp1.
1. A Schottky junction or a PN junction is formed between the second source electrode and the drain electrode of the wire 2 on the side opposite to the semi-insulating semiconductor substrate and the second semiconductor active layer. The present invention relates to an improvement in a semiconductor device having a configuration in which a second field effect transistor includes a second gate electrode connected to form a junction and has a pinch-off voltage different from that of the first field effect transistor.

従来の斯檀半導体装筺に於ては、第1の電界効果トラン
ジスタの第1のゲート電極と、tJ42の電界効果トラ
ンジスタの第2のゲート電極とが同じゲート電極用材料
で形成され、従って第1及び#!2の電昇効果トランジ
スタのショットキ接合又はPN接合 が同じ障壁の高さ
を有し、然し乍ら第1の電界効果トランジスタの第10
)半導体能動層と第2の電界効果トランジスタの第2の
半導体能動層とが同じ半導体で形成されているとしても
、異なる厚さ又は異なる不純物濃度を有していることに
よって、第1及び*2の電界効果トランジスタが異なる
ピンチオフ電圧を有しているを普通としてい□た、 即ち、令弟1の電界効果トランジスタの第1のゲート電
極と、第2の電界効果トランジスタの第2のケート電極
とが同じケート11L極用材料で形成され、然し乍らt
J741の電昇効果トランジスタの第1の半導体能動層
と第2の電昇効果トランジスタの第2の半導体能動層と
が同じ半導体で構成されているも、真なる*g+有して
いることによって、第1及び第2の電界効果トランジス
タが異なるピンチオフ−圧を有している場合で、図示説
明すれば、第1図又は#42図を併なって以下述べる構
成を有するを普通としていた。
In the conventional sandalwood semiconductor device, the first gate electrode of the first field effect transistor and the second gate electrode of the tJ42 field effect transistor are formed of the same gate electrode material, so that 1 and #! The Schottky junctions or PN junctions of the two field effect transistors have the same barrier height, but the tenth field effect transistor of the first field effect transistor has the same barrier height.
) Even if the semiconductor active layer and the second semiconductor active layer of the second field effect transistor are formed of the same semiconductor, the first and *2 semiconductor active layers may have different thicknesses or different impurity concentrations. It is common that the field effect transistors have different pinch-off voltages, i.e., the first gate electrode of the second field effect transistor and the second gate electrode of the second field effect transistor. are made of the same material for the gate 11L pole, but
Even though the first semiconductor active layer of the charge effect transistor of J741 and the second semiconductor active layer of the second charge effect transistor are made of the same semiconductor, by having the true *g+, In the case where the first and second field effect transistors have different pinch-off voltages, it is common to have the configuration described below with reference to FIG. 1 or #42.

先ず第1図の構成にっき述哀るに、例えばN型の半導体
能動層1人及び1Bが、それ等に共通の例えばGaAs
  でなる半絶縁性半導体基板2上に、所鯖メサエッチ
ングによって形成された所順メサエッチング部5によっ
て互に分離されて並置形成されている。この場合半導体
能動層1人及び1Bは、同、じ半導体例えばGaAs 
で形成され且同じ不純物#1度を有しているも、異なる
犀さDa及びDbを有する。実際上半導体能動層1人は
、半絶縁性半導体基板、2内にその主、向側よりN!I
I不純物イオンを打込むという#!1の不純物イオン打
込地理によって形成され、又半導体能動層1Bは、半絶
縁性半導体基板2内にその主面側よりNWi不純物イオ
ンを第1の不純物、イオン打込処理時とは異なる不純物
イオンの加速電圧で打込むという第2の不純物イオン打
込処造によって形成されている。
First of all, referring to the structure shown in FIG.
They are formed on a semi-insulating semiconductor substrate 2, separated from each other by sequential mesa etching portions 5 formed by mesa etching. In this case, the semiconductor active layers 1 and 1B are made of the same semiconductor, for example GaAs.
Although they are formed of and have the same impurity #1 degree, they have different densities Da and Db. In fact, the semiconductor active layer 1 is located in a semi-insulating semiconductor substrate, 2 whose main layer is N! from the opposite side! I
I implanting impurity ions #! The semiconductor active layer 1B is formed by implanting NWi impurity ions into the semi-insulating semiconductor substrate 2 from the main surface side as the first impurity, and impurity ions different from those during the ion implantation process. The impurity ions are formed by a second impurity ion implantation process in which the impurity ions are implanted at an acceleration voltage of .

又半導体能動層1人に、半絶縁性半導体基板21mとは
反対側に於て、例えば金属でなるソース電極4A及、び
ドレイン電極5Aがオーiックに連結されている。爽に
半導体能動層1人に、半絶縁性半導体基板2IIとは反
対側に於けるソース電極4A及びドレイン電[1i5A
間に於て、例えばMでなるゲートIIL極6今が半導体
能動ト命接合7Aを型成すべ く連結されている。而して半導体能動層1ム、ソース電
極4A、 ドレイン電極5 A及ヒゲート電極6Aを含
んでショットキ接合型電界効果トランジスタ8Aが構成
されている。
Further, a source electrode 4A and a drain electrode 5A made of metal, for example, are electrically connected to one semiconductor active layer on the opposite side from the semi-insulating semiconductor substrate 21m. In one semiconductor active layer, a source electrode 4A and a drain electrode [1i5A on the side opposite to the semi-insulating semiconductor substrate 2II]
In between, a gate IIL pole 6, for example M, is connected to form a semiconductor active junction 7A. A Schottky junction field effect transistor 8A is constituted by the semiconductor active layer 1, the source electrode 4A, the drain electrode 5A, and the gate electrode 6A.

更に半導体能動層1Bに、半絶縁性半導体基板211と
は反対側に於て、電界効果トランジスタ8Aのソース電
極4人及びドレイン電極5Aと同じ金属でなるソース電
極4B及びドレイン電極5Bがオーミックに連結されて
いる。又半導体能動層IBJζ半絶縁半絶縁体半導体基
板は反対側に於けるソース電1i4B及びドレイン電極
5B間に於て、電界効果トランジスタ8Aのゲート電極
6人と同じ金属でなるゲート電極6Bが、半導体能動層
1Bとの間で、電界効果トランジスタ、&Aのショット
キ接合7Aと同じ障壁高さを有するショットキ接合7B
を形成すべく連結されている。而して半導体能動層1B
Furthermore, a source electrode 4B and a drain electrode 5B made of the same metal as the four source electrodes and the drain electrode 5A of the field effect transistor 8A are ohmically connected to the semiconductor active layer 1B on the opposite side from the semi-insulating semiconductor substrate 211. has been done. In addition, between the source electrode 1i4B and the drain electrode 5B on the opposite side of the semiconductor active layer IBJζ semi-insulating semi-insulating semiconductor substrate, a gate electrode 6B made of the same metal as the six gate electrodes of the field effect transistor 8A is a semiconductor substrate. A Schottky junction 7B having the same barrier height as the Schottky junction 7A of the field effect transistor &A is connected to the active layer 1B.
are connected to form a Therefore, the semiconductor active layer 1B
.

ソース1lll:1k4B、)し4ンi[5BAc)グ
ー)電極6Bを含んでショットキ接合型電界効果トラン
ジスタ8Bが構成されている。
A Schottky junction field effect transistor 8B is constituted by the source 1lll:1k4B,) and 4in[5BAc)g) electrode 6B.

次に第2図の構成につき述べるに、第1図の場合と同様
の半導体能動層1人及び1Bが、第1図の場合と同様の
半絶縁性半導体基板2上に、第1図の場合と同様にメサ
エッチングs3によって分離されて並置形成されている
Next, to describe the configuration of FIG. 2, the same semiconductor active layer 1 and 1B as in the case of FIG. 1 are placed on the same semi-insulating semiconductor substrate 2 as in the case of FIG. Similarly, they are separated and juxtaposed by mesa etching s3.

又半導体能動層1人に111図の場合と同様のソース電
極4人及びドレイン電極5Aがオーはツクに連結されて
いる。然し乍ら半導体能動層1人に、半絶縁性半導体基
板211とは反対側に於けるソース電極4人及びドレイ
ン電極5A間に於て、例えば(hAs でなるゲート電
極9Aが、半導体能動層1人との間でPNlii’合1
0Aを合成0Aく連結されている。而して半導体能動層
IA、ソース電極4A、 ドレイン電極5A及びゲート
電極9Aを含んでPN接合型電界効果トランジスタ11
Aが構成されている。
Furthermore, four source electrodes and a drain electrode 5A similar to the case shown in FIG. 111 are connected to one semiconductor active layer. However, between one semiconductor active layer and four source electrodes and four drain electrodes 5A on the opposite side from the semi-insulating semiconductor substrate 211, for example, a gate electrode 9A made of (hAs) is connected to one semiconductor active layer. Between PNlii' and 1
0A is connected to synthesize 0A. The PN junction field effect transistor 11 includes the semiconductor active layer IA, the source electrode 4A, the drain electrode 5A, and the gate electrode 9A.
A is configured.

更に半導体能動層1Bに#11図の場合と同様のソース
電極4B及びドレイン電極5Bがオーミンクに連結され
ている。然し乍ら半導体能動層1Bに、半絶縁性半導体
基&211とは反対側に於けるソース電極4p及びドレ
イン11IL極5B間に於て、電界効果トランジスタ1
1Aのゲート電極9Aと同じ半導体でなるゲート電極9
Bが、半導体能動層1Bとの間で、電界効果トランジス
タ11AのPN接合10Aと同じ陣壁尚さを有するPN
接合10Bを形成すべく連結されている。而して半導体
能動層IB、ソース電極4 B、  ドレイン電極5B
及びゲート′vL極9Bを含んでPN接合型電界効果ト
ランジスタ11.+Bが構成されている。
Further, a source electrode 4B and a drain electrode 5B, similar to those in Figure #11, are connected to the semiconductor active layer 1B in an ohmic manner. However, in the semiconductor active layer 1B, there is a field effect transistor 1 between the source electrode 4p and the drain 11IL pole 5B on the opposite side from the semi-insulating semiconductor substrate &211.
Gate electrode 9 made of the same semiconductor as gate electrode 9A of 1A
B has the same wall thickness as the PN junction 10A of the field effect transistor 11A between it and the semiconductor active layer 1B.
They are connected to form a junction 10B. Thus, the semiconductor active layer IB, the source electrode 4B, and the drain electrode 5B
and a PN junction field effect transistor 11. including the gate 'vL pole 9B. +B is configured.

以上11図及びt42図にて、第1の電界効果トランジ
スタ(第1図の場合8A、92図の場合11人)の第1
のゲート電極(#!1−の場合6A、第2図の場合9人
)と、t142の電界効果トランジスタ(第1図の場合
8B、第2図の場合11 B )ノaR2(7)ゲート
電極(#!1図の場合6B%第2図の場合9B)とが−
1じケート電極用材料で形成され、然し乍ら#!1の電
界効果トランジスタの謝1の半導体能、動層(第1図及
び第2図の場合共1A゛)と謝2の電界効果トランジス
タの第2の半導体能動層(第1図及び絹2図の場合共I
B)とが同じ半導体で構成されているも、異なる厚さく
前者がDa 、後者がDb )を有していることによっ
て、wil及びW42の電界効果トランジスタが異なる
ピンチオフ電圧を有している場合の従来の半導体装置が
明らかとなった。同第1及び第2の電界効果トランジス
タが異なるピンチオフ電圧を有するということは、第1
図の場合第1の電界効果トランジスタ8Aのソース電極
4人及びゲートIIE極6A間に徐々に値の大になる電
圧を与える場合に於て、ショットキ接合7Aより半絶縁
性半導体基&2儒に拡がる空乏層12Aが半絶縁半導体
基板2に達し、これによりソース電極4人及びドレイン
電極5A間が非導通状態になるときの、ソース電極4A
及びゲート電極6人間の電圧と、第2の電界効果トラン
ジスタ8Bのソース電極4B及びケート電極6B間に同
様に徐々に値の大になる電圧を与える場合に於て、ショ
ットキ接合7F!hより半絶縁性半導体基板2側に拡が
る空乏層12Bが半絶縁性半導体基板2に達し、これに
よりソース電極4 B、及びドレイン電極、5B間が非
導通状態になるときのソースWa4B及びゲート電極6
B間の電圧とが異なることを意味する。又第、2図の場
合、第1の電界効果トランジスタ11Aのソース電極4
A及びゲート電極9A間に徐iに値の大になる電圧を与
える場合に於て、PN接合10Aより半絶縁性半導体基
板211ilに拡がる空乏層15Aが半絶縁性半導体基
板2に達し、これにより、ソース電極4A及びドレイン
電極5A間が非導通状態になるときのソース電極4A及
びゲート電極9A間の電圧と、第2の電界効果トランジ
スタ11Bのソースを極4B及びゲート電極9B間に徐
々に値の大になる電圧を与える場合に於て、PN−接合
10Bより牛絶縁性半導体基&211に拡がる空乏層1
3Bが半絶縁性半導体基板2に達し、これによりソース
電極4B及びドレイン電極5、 B間が非導通状態にな
るときのソース電極4B及びゲート1498間の電圧と
が異なることを意味する。
In Figure 11 and Figure t42 above, the first field effect transistor (8A in Figure 1, 11 in Figure 92)
(6A in case of #!1-, 9 in case of Fig. 2) and a field effect transistor of t142 (8B in case of Fig. 1, 11 B in case of Fig. 2) noaR2 (7) gate electrode (#! 6B for Figure 1 9B for Figure 2) and -
It is made of the same electrode material, but #! The semiconductor active layer of the field effect transistor 1 (1A in both FIGS. 1 and 2) and the second semiconductor active layer of the field effect transistor 2 (1A in both FIGS. 1 and 2) In the case of I
B) and W42 are made of the same semiconductor but have different thicknesses, Da and Db), so that the field effect transistors wil and W42 have different pinch-off voltages. A conventional semiconductor device has been revealed. The fact that the first and second field effect transistors have different pinch-off voltages means that the first and second field effect transistors have different pinch-off voltages.
In the case shown in the figure, when applying a voltage that gradually increases in value between the four source electrodes and the gate IIE electrode 6A of the first field effect transistor 8A, the voltage spreads from the Schottky junction 7A to the semi-insulating semiconductor base &2 The source electrode 4A when the depletion layer 12A reaches the semi-insulating semiconductor substrate 2 and the four source electrodes and the drain electrode 5A become non-conductive.
When applying a voltage that gradually increases in value between the voltage between the gate electrode 6 and the source electrode 4B and the gate electrode 6B of the second field effect transistor 8B, the Schottky junction 7F! The depletion layer 12B extending from h to the semi-insulating semiconductor substrate 2 side reaches the semi-insulating semiconductor substrate 2, thereby causing a non-conducting state between the source electrode 4B, the drain electrode, and the source electrode Wa4B and the gate electrode 5B. 6
This means that the voltage between B and B is different. In the case of FIG. 2, the source electrode 4 of the first field effect transistor 11A
When applying a voltage that gradually increases in value i between A and the gate electrode 9A, the depletion layer 15A that spreads from the PN junction 10A to the semi-insulating semiconductor substrate 211il reaches the semi-insulating semiconductor substrate 2, thereby , the voltage between the source electrode 4A and the gate electrode 9A when the source electrode 4A and the drain electrode 5A become non-conductive, and the voltage between the source electrode 4B and the gate electrode 9B of the second field effect transistor 11B gradually change. When applying a voltage that increases, the depletion layer 1 spreads from the PN-junction 10B to the insulating semiconductor substrate &211.
3B reaches the semi-insulating semiconductor substrate 2, which means that the voltage between the source electrode 4B and the gate 1498 is different when the source electrode 4B and the drain electrode 5, B become non-conductive.

然し乍ら、第1図及びtR2図にて上述せる従来の半導
体装置の場合、第1の電界効果トランジスタを構成せる
第1の半導体能動層1人と第2の電界効果トランジスタ
を構成せる第2の半導体能動層1Bとを異なる厚さDa
及びDbを有するものとして各別に形成するを要し、(
上側費し)、この為s1及び第2の半導体能動層を得る
に多くの工程を一〇”そいた。又第1及び第2の半導体
能動層1人及び1Bの互に異なる厚さDa及びDbを、
所期あ値で均=に得るに一薙を伴い、この為第1及び第
2の電界効果トランジスタを所期の特性を有するものと
して得るのが困難であうた。更に上側の如く第1及び第
2の半導体能動層1人及び1Bを不純物イオン打込処理
により形成するi合、高温アニニル処理を必要とし、こ
の為□′i1及び第2の半導体能動層1人及び1Bを得
るに更に多くの工程を擬していた等の欠点を有していた
However, in the case of the conventional semiconductor device described above in FIGS. 1 and tR2, one first semiconductor active layer forming the first field effect transistor and one second semiconductor forming the second field effect transistor The active layer 1B has a different thickness Da.
and Db, it is necessary to form each separately, (
For this reason, many steps were performed to obtain s1 and the second semiconductor active layer.Also, the first and second semiconductor active layers 1 and 1B had mutually different thicknesses Da and 10". Db,
It took some time to obtain the desired values evenly, and therefore it was difficult to obtain the first and second field effect transistors having the desired characteristics. Furthermore, in the case where the first and second semiconductor active layers and 1B are formed by impurity ion implantation treatment as shown above, high-temperature aninyl treatment is required. This method had disadvantages such as simulating many more steps to obtain 1B and 1B.

尚、上述に於ては、第1図及びwJ2図を伴なって、第
1の電界効果トランジスタの#!1のゲート電極と、第
2の電界効果トランジスタの第22のゲート電極とが同
じゲート電極用材料で形成され、然し乍ら第1の電界効
果トランジスタの第1の半導体能動層と、1@2の電界
効果トランジスタの182の半導体能動層とが同じ半導
体で構成されているも、異なる厚さを有することによっ
て、#!1及び第2の電界効果トランジスタが異なるピ
ンチオフ電圧を肴している場合の従来の半導体装置の欠
点を述べたが、第1の電界効果トランジスタの#!1の
ゲート電極と、第2の電界効果トランジスタの#!2の
ゲート電極とが同じゲート電極用材料で構成され、然し
乍ら謝1の電界効果トランジスタの第1の半導体・1−
助層と、第2の電界効果トランジスタの第2の半導体能
動層とが同じ半導体で構成されているも、異なる不純物
濃度を有することによって、第1及び第2の電界効果ト
ランジスタが異なるピンチオフ電圧を有している場合の
従来の半導体装置の場合、詳細説明はこれを省略するも
、第1の電界効果トランジスタを構成せる第1の半導体
能動層と第2の電界効果トランジスタを構成せる第2の
半導体能動層とを異なる不純物濃度を有するものとして
各別に形成するを要し、又異なる不純物濃度を所期の値
で得るに困難を伴う等の欠点を有していた。
Incidentally, in the above description, #! of the first field effect transistor is described with reference to FIGS. The first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are formed of the same gate electrode material, but the first semiconductor active layer of the first field effect transistor and the second gate electrode of the second field effect transistor are Even though the 182 semiconductor active layers of the effect transistor are made of the same semiconductor, they have different thicknesses, so that #! The disadvantages of the conventional semiconductor device when the first and second field effect transistors are provided with different pinch-off voltages have been described. 1 gate electrode and #! of the second field effect transistor. The gate electrodes of the field effect transistors 1 and 2 are made of the same gate electrode material;
Although the auxiliary layer and the second semiconductor active layer of the second field effect transistor are made of the same semiconductor, they have different impurity concentrations, so that the first and second field effect transistors have different pinch-off voltages. In the case of a conventional semiconductor device having a first semiconductor active layer constituting a first field effect transistor and a second semiconductor active layer constituting a second field effect transistor, although a detailed description thereof will be omitted, It is necessary to separately form semiconductor active layers having different impurity concentrations, and there are also drawbacks such as difficulty in obtaining different impurity concentrations at desired values.

依って本発明は上述せる欠点のない、新規なwI1g1
半導体装置を提案せんとするもので、以下詳述する所よ
り明らかとなるであろう。
Therefore, the present invention provides a novel wI1g1 without the above-mentioned drawbacks.
This will become clear from the detailed description below.

W43図は本発明による半導体装置の第1の実施例を示
し、第1図及び#!2図との両名部分には同一符号を符
して詳細説明はこれを省略するも、第1及び第2図の場
合と同様の半導体能動層1人及び1Bが、第1及び第2
図の場合と同様の半絶縁性半導体基板2上に、第1図の
場合と同様に、メサエッチンク部3によって互に分離さ
れて並置されて形成されている。但しこの場合、半導体
能動層1人及び1Bは、同じ半導体例えばGaAs  
で且同じ厚さ、不純物#度尋の条件で形成されている。
Figure W43 shows a first embodiment of the semiconductor device according to the present invention, and Figures 1 and #! The same reference numerals are given to the parts in both FIGS. 2 and 2, and a detailed explanation thereof will be omitted.
As in the case of FIG. 1, they are formed on a semi-insulating semiconductor substrate 2 similar to that shown in the figure, separated from each other by mesa etching portions 3 and juxtaposed. However, in this case, the semiconductor active layers 1 and 1B are made of the same semiconductor, for example, GaAs.
and are formed under the same conditions of the same thickness and impurity count.

実際上、半導体能動層1人及び1Bは、半絶縁性半導体
基板2の主向上に一様性のある1つの半導体層を一義的
にエピタキシャル成長法によって形成し、然る后その半
導体層に対しメサエッチングs3を形成すべくエツチン
グ処理をなして形成される。
In practice, the semiconductor active layers 1 and 1B are formed primarily by forming one uniform semiconductor layer on the semi-insulating semiconductor substrate 2 by an epitaxial growth method, and then forming a mesa layer on the semiconductor layer. It is formed by performing an etching process to form etching s3.

又半導体能動層1Aに、半絶縁性半導体基板211とは
反対側に於て、第1及び!!42図の場合と同様のソー
ス電極4人及びドレイン電極5Aがオーミックに連結さ
れている′。更に半導体能動層1人に、半絶縁性半導体
基板2@とは反対側に於けるソース電極4人及びドレイ
ン電極5A間に於て、#11図の場合と同様の金属でな
るゲート電極6人が、半導体能動層1人との間で!@1
図の場合と同様のシ1ットキ接合7Aを形成すべく連結
されている。而して牛尋体能助層IA、ソース電極4A
1 ドレイン電極5A及びゲート電極6Aを含んで第1
図の場合と同様ノショットキ接合型電界効果トランジス
タ8Aが構成されている・。
Further, in the semiconductor active layer 1A, on the side opposite to the semi-insulating semiconductor substrate 211, the first and! ! Four source electrodes and a drain electrode 5A similar to the case shown in FIG. 42 are ohmically connected. Furthermore, for each semiconductor active layer, between the four source electrodes on the opposite side of the semi-insulating semiconductor substrate 2@ and the drain electrode 5A, there are six gate electrodes made of the same metal as in the case of Figure #11. However, between one semiconductor active layer! @1
They are connected to form a seat joint 7A similar to that shown. Therefore, Ushihiro body support layer IA, source electrode 4A
1 The first electrode including the drain electrode 5A and the gate electrode 6A
A Noschottky junction field effect transistor 8A is constructed as in the case shown in the figure.

更に半導体能動層1Bに、半絶縁性半導体基板211と
は反対側に於て、第1及び第2図の場合と同様のソーλ
電極4B及びドレイン電極5Bがオーミックに連結され
ている。又半導体能動層1Bに、半絶縁性半導体基板2
−とは反対側に於けるソーλ電極4B及びドレイン電極
5B閣に於て、第2図の場合と同様の、半導体能動層1
Bと同じ半導体でなるゲート電極9Bが、半導体能動層
1Bとの間で、第2図の場合と1シ様のPN@合10B
を形成すべく連結されている。而して半導体能動層IB
1ソース電極4B、  ドレイン電極5B及びゲート電
極9Bを含んで第2図の場合と同様のPN接合屋電界効
果トランジスタ11Bが構成されている。尚この場合P
N接合型電界効果トランジスタ11Bの半導体能動層1
Bのゲート電極9B下の領域が、ショットキ接合型電界
効果トランジスタ8Aの半導体能動層IAのゲート電極
6A下の領域と同じ厚さ、不純物濃度等の条件を有する
ものである。
Furthermore, on the side opposite to the semi-insulating semiconductor substrate 211, a saw λ similar to that in FIGS. 1 and 2 is placed on the semiconductor active layer 1B.
The electrode 4B and the drain electrode 5B are ohmically connected. Further, a semi-insulating semiconductor substrate 2 is provided on the semiconductor active layer 1B.
- On the side opposite to the source λ electrode 4B and the drain electrode 5B, a semiconductor active layer 1 similar to that in FIG.
Between the gate electrode 9B made of the same semiconductor as B and the semiconductor active layer 1B, there is a PN@coupling 10B in the same manner as in the case of FIG.
are connected to form a Therefore, the semiconductor active layer IB
A PN junction field effect transistor 11B similar to that shown in FIG. 2 is constructed including a source electrode 4B, a drain electrode 5B, and a gate electrode 9B. In this case, P
Semiconductor active layer 1 of N-junction field effect transistor 11B
The region under the gate electrode 9B of B has the same conditions such as thickness and impurity concentration as the region under the gate electrode 6A of the semiconductor active layer IA of the Schottky junction field effect transistor 8A.

以上が本発明による半導体装置の第1の実施例の構成で
あるが、斯る構成によれば、電界効果トランジスタ8人
を構成せる半導体能動層1人と電界効果トランジスタ1
1Bを構成せる半導体能動層1Bとが、同じ半導体で且
同じ厚さ、不純物濃度等の条件で形成され、然し乍ら電
界効果トランジスタ8人のゲート電極6Aと電界効果ト
ランジスタ11Bのゲート電極9Bとが異なるゲート電
極用材料で形成され、そし1て電界効果トランジスタ8
ムのゲート電極6ムが半導体能動層1人との間でショッ
トキ接合7人を形成し、又電界効果トランジスタ11B
のダート電極9Bが半導体能動層1Bとの間でホモPN
接合10Bを形成していることによりショットキ接合7
人とホモPN接合10Bとが異なる障壁の高さを有して
いる。仁の為電界効果トランジスタ8人及び11Bが異
なるピンチオフ電圧を′有する。例えば半導体能動層1
人及び1Bが共にGaAg でなり、そして厚さが共に
120OL不純物#Ifが共に1X 1Q ” al−
’でなり、ゲート電極6人がAI!でなり、ゲート電極
9BがGa入3 でなる場合、ショットキ接合7人がα
8■、PN’接合10Bが1.4■の障壁の高さを有し
、電界効果トランジスタ8人が−0,2V、 ”tl’
ll効果) ラン’)x911 Bカ+2.OVのピン
チオフ電圧を有する。
The above is the configuration of the first embodiment of the semiconductor device according to the present invention. According to this configuration, one semiconductor active layer and one field effect transistor constitute eight field effect transistors.
The semiconductor active layer 1B constituting the semiconductor active layer 1B is made of the same semiconductor and is formed under the same conditions such as the same thickness and impurity concentration, but the gate electrode 6A of the eight field effect transistors and the gate electrode 9B of the field effect transistor 11B are different. A field effect transistor 8 is formed of a gate electrode material, and 1 is formed of a gate electrode material.
The gate electrode 6 of the semiconductor active layer forms a Schottky junction with the semiconductor active layer, and the field effect transistor 11B
The dirt electrode 9B is homo-PN between the semiconductor active layer 1B
Schottky junction 7 is formed by forming junction 10B.
Humans and homo-PN junction 10B have different barrier heights. The 8 field effect transistors and 11B have different pinch-off voltages. For example, semiconductor active layer 1
1B and 1B are both made of GaAg, and both have a thickness of 120 OL impurity #If is 1X 1Q ” al-
'Then, the 6 gate electrodes are AI! When the gate electrode 9B is made of Ga-containing 3, the Schottky junction 7 is α
8■, the PN' junction 10B has a barrier height of 1.4■, and the 8 field effect transistors have -0.2V, "tl"
ll effect) Run') x911 B +2. It has a pinch-off voltage of OV.

従って1m3図にて上述せる本発明による半導体装置に
よれ□ば、w41及び42図の場合と同様に、互に異な
るピンチオフ電圧を有する2つの電界効果トランジスタ
を構成している構成を有する。然し乍らその2つの電界
効果トランジスタを構成せる半導体能動層1人及び1B
が同じ半導体で且−じ厚さ、不純物濃度等の条件で形成
されているので、それ等″¥−尋体舵体能動層1人1B
を#!1図及び第21の従来の場合の如くに各別に形成
するを要さず、従って半導体能動層1人及び1Bfi−
第1図及び第2図の場合に比し容易に均一に得ることが
出来る等、第1図及び第2−にて上述せる欠点を伴うこ
とがないという大なる特徴を有する。
Accordingly, the semiconductor device according to the present invention shown in FIG. 1m3 has a configuration in which two field effect transistors having different pinch-off voltages are formed, as in the case of FIGS. w41 and 42. However, the semiconductor active layers 1 and 1B that constitute the two field effect transistors
Since they are formed of the same semiconductor and under the same conditions such as thickness and impurity concentration, they are
of#! Unlike the conventional cases shown in FIGS. 1 and 21, it is not necessary to form each semiconductor active layer separately.
It has great features such as being able to be obtained more easily and uniformly than in the case of FIGS. 1 and 2, and without the drawbacks mentioned above in FIGS. 1 and 2-.

次に第4図を伴なって本発明による半導体装置の第2の
実施例を述べるに、第3図との対応部分には同一符号を
附して詳細説明はこれを省略するも、aR5図にて上述
せる構成に於て、半導体能動層1Bに、それと同じ半導
体でなるゲート電極9Bが、半導体能動層1Bとの間で
ホモPN@合10Bを形成すべく連結されてなる構成の
へテロPN接合W亀界効果トランジスタ11Bが、例え
ばGaAs でなる半導体りじ助層1Bにそれとは異な
る例えばCmrkl、−、ks  (但し0<x<1 
)で表わされる半導体でなるケート電fI9B’が半導
体能動層1Bとの間でヘテロ接合IQB’を形成すべく
連結されてなる構成のへテロPN接合型電界効果トラン
ジスタ11B′に置換されてなることを除いては、第3
図の場合と同様の構成を有する。
Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIG. 4. Parts corresponding to those in FIG. In the above-mentioned structure, the semiconductor active layer 1B is connected to the gate electrode 9B made of the same semiconductor so as to form a homogeneous PN@contact 10B with the semiconductor active layer 1B. The PN junction W tortoise field effect transistor 11B has a semiconductor substrate auxiliary layer 1B made of GaAs, for example.
) is replaced with a hetero PN junction field effect transistor 11B' having a structure in which the gate electrode fI9B' made of a semiconductor represented by 1B is connected to form a heterojunction IQB' with the semiconductor active layer 1B. Except for the third
It has the same configuration as the case shown in the figure.

以上が本発明による半導体装置の第2の実施例の構成で
あるが、斯る構成によれは、それが上述せる事項を除い
ては第3図の場合と同様であり、そしてショットキ接合
7Aとへテロ接合10B′とが異なる障壁の高さを有し
ていること明らかである。この為電界効果トランジスタ
8人及び11B′とが異なるピンチオフ電圧を有する。
The above is the configuration of the second embodiment of the semiconductor device according to the present invention, and this configuration is the same as that shown in FIG. 3 except for the matters mentioned above, and the Schottky junction 7A and It is clear that the heterojunction 10B' has a different barrier height. For this reason, the field effect transistors 8 and 11B' have different pinch-off voltages.

従って第4図にて上述せる本発明による半導体装置によ
れば、第3図の場合と同様に互に異なるピンチオフ電圧
を有する2つの電界効果トランジスタを構成している構
成を有する。然し乍らその2つの電界効果トランジスタ
を構成せる半導体能動層1人及び1Bが第6恥の場合と
同様に同じ半導体で且同じ岸さ、不純物濃度等の条件で
形成されているので、fig3図の場合と同様の優れた
特徴を有する。
Accordingly, the semiconductor device according to the present invention described above with reference to FIG. 4 has a configuration in which two field effect transistors having mutually different pinch-off voltages are formed, as in the case of FIG. 3. However, since the semiconductor active layers 1 and 1B constituting the two field effect transistors are made of the same semiconductor and are formed under the same conditions such as the same thickness and impurity concentration as in the case of the 6th case, in the case of fig. It has the same excellent characteristics.

次に第5図を伴なって本発明による半導体装置のIJ!
3の実施例を述べるに、第6図及び第4図との対応部分
には同一符号を附して詳細説明はこれを省略するも、第
6図にて上述せる構成に於て、半導体能動層1人に金楓
でなるゲート電極6人が、半導体能動層1人との間でシ
ョットキ接合7人を形成すべく連結されてなる構成のシ
ョットキ接合型電界効果トランジスタ8Aが、例えば(
)aAs  でなる半導体能動層1人に、それとは異な
る例えば龜−!t−,Aa  (但し0〈x〈1)で表
わされる半導体でなるゲート電極9 B’が、半導体能
動層1Bとの間でヘテ0接合10B′を形成すべく連結
されてなる構成のへテロPN接合m電界効果トランジス
タ11B′に置換されてなることを除いては第3図の場
合と同様の構成を有する。
Next, with reference to FIG. 5, IJ! of the semiconductor device according to the present invention!
Embodiment 3 will be described. Parts corresponding to those in FIG. 6 and FIG. For example, a Schottky junction field effect transistor 8A has a configuration in which six gate electrodes made of gold maple per layer are connected to one semiconductor active layer to form seven Schottky junctions.
) aAs semiconductor active layer, for example, a different semiconductor active layer -! A heterostructure in which a gate electrode 9B' made of a semiconductor represented by t-, Aa (0<x<1) is connected to form a heterojunction 10B' with a semiconductor active layer 1B. It has the same structure as the case of FIG. 3 except that it is replaced with a PN junction m field effect transistor 11B'.

以上が本発明による半導体装置の第3の実施例の構成で
あるが、斯る構成によれば、それが上述せる事項を除い
て第3図の場合と同様であり、モしてヘテロPN接合1
0B′とホモPN@酋10Bとが異なる障壁の高さを有
していること明らかであるので、電界効果トランジスタ
11B′及び11Bが異なるピンチオフ電圧を有し、そ
してこの場合も半導体能動層1人及び1Bが同じ半導体
で且同じ厚さ、不純物#I&嵐勢の条件で形成されてい
るので、#!3図の場合と同様の優れた特徴を有する。
The above is the configuration of the third embodiment of the semiconductor device according to the present invention. According to this configuration, it is the same as the case of FIG. 1
Since it is clear that 0B' and homo PN@10B have different barrier heights, field effect transistors 11B' and 11B have different pinch-off voltages, and in this case also one semiconductor active layer. and 1B are made of the same semiconductor, have the same thickness, and are formed under the conditions of impurity #I & storm force, so #! It has the same excellent features as the case in Figure 3.

次に第6図を伴なって本発明による半導体装置の#I4
の実施例を述べるに、第5図との対応部分に同一符号を
附して詳細説明はこれを省略するも、第5図にて上述せ
る構成に於て、半導体能動層1Bにそれと同じ半導体で
なるゲート電極9Bが、半導体能動層1Bとの間でホモ
PNg合10Bを形成すべ(連結されてなる構成のホモ
PN接合型電界効果トランジスタ11Bが、例えばGa
As でなる半導体能動層1Bに、その半導体能動層1
Bの半導体及びゲート電極9 B’の半導体とは異なる
例えばGhN 、−yAa (但し0<y<1 、x”
qy )で表わされる半導体でなるゲート電極? Bl
が、半導体能動層1Bとの間でヘテロ接合10B′とは
異なる障壁の^さを有するヘテロ接合10B’を形成す
べく連結されてなる構成のへテロ接合型電界効果トラン
ジスタ11 Blに置換されてなることを除いては第5
図の場合と同様の構成を有する。
Next, with reference to FIG. 6, #I4 of the semiconductor device according to the present invention
To describe the embodiment, the same reference numerals are given to the parts corresponding to those in FIG. 5, and detailed explanation thereof is omitted. However, in the configuration described above in FIG. The gate electrode 9B should form a homo-PNg junction field effect transistor 10B with the semiconductor active layer 1B.
The semiconductor active layer 1B is made of As.
For example, GhN, -yAa (where 0<y<1, x''
A gate electrode made of a semiconductor represented by qy )? Bl
is replaced with a heterojunction field effect transistor 11Bl configured to be connected to the semiconductor active layer 1B to form a heterojunction 10B' having a barrier height different from that of the heterojunction 10B'. 5th except becoming
It has the same configuration as the case shown in the figure.

以上が本発明による半導体装置のwA4の実施例の構成
であるが、斯る構成によれば、それが上述せる拳項を除
いては第5図の場合と同様であるので、電界効果トラン
ジスタ11B′及び11B#が異なるピンチオフ電圧を
有し、そしてこの場合も半導体能動層1人及び1Bが同
じ半導体で且同じ厚さ、不純物濃度勢の条件で形成され
ているので、tssFiaの場合と同様の優れた特徴を
有する。
The above is the configuration of the embodiment of the semiconductor device wA4 according to the present invention. According to this configuration, it is the same as the case of FIG. ' and 11B# have different pinch-off voltages, and in this case as well, the semiconductor active layers 1 and 1B are made of the same semiconductor and are formed under the same thickness and impurity concentration conditions. It has excellent characteristics.

尚上述に於ては本発明の僅かな実施例を示したに貿まり
、本発明の精神を脱することなしに種々の変N変更をな
し得るであろう。
It should be noted that the foregoing has described only a few embodiments of the invention, and various modifications may be made without departing from the spirit of the invention.

【図面の簡単な説明】[Brief explanation of the drawing]

#11図及び@2図は従来の半導体装置を示す路線的断
面図、w45図、I!4図、第5図及び第6図は夫々本
発明による第1、第2、尾3及び第4の実施例を示す路
線的断面図である。 層中、IA及び1Bは半導体能動層、2は半絶縁性半導
体基板、4A及び4Bはソース電極、5A及び5Bはド
レイン電極、6A16B。 9A、9B、9B’及び9BIはゲート電極、7ム及び
7Bはショットキ接合、10A、10B。 10B′及び10B’はへテロ接合、8A、8B111
B111B’及び11B#は電界効果トランジスタを夫
々示す。 出願人 日本電信・wt帖公社
#11 figure and @2 figure are line cross-sectional views showing conventional semiconductor devices, w45 figure, I! 4, 5, and 6 are cross-sectional views showing the first, second, tail 3, and fourth embodiments of the present invention, respectively. Among the layers, IA and 1B are semiconductor active layers, 2 is a semi-insulating semiconductor substrate, 4A and 4B are source electrodes, 5A and 5B are drain electrodes, and 6A16B. 9A, 9B, 9B' and 9BI are gate electrodes, 7mm and 7B are Schottky junctions, 10A, 10B. 10B' and 10B' are heterozygous, 8A, 8B111
B111B' and 11B# indicate field effect transistors, respectively. Applicant: Nippon Telegraph/Wtcho Corporation

Claims (1)

【特許請求の範囲】 少くとも第1及び第2の半導体能動層がそれ等に共通の
半絶縁性半導体基板上に形成され、上記w41の半導体
能動層と、該第1゛の半導体能動層に、上記半絶縁性半
導体基@側とは反対側番こ於てオーミックに連結せる亀
1の゛ソース電極及び第1のドレイン電極と、上記第1
゛の□半導体能動層に、上記半絶縁性半導体基板側と゛
は反対側に於ける上記第1のソース電極及び上記all
のドレイン電極間に於て、上記w!1の半導体能動層と
の間でショットキ接谷又はPN接合を形成すべく連結せ
る第1のゲート電極とを含′んで第1の電界効果トラン
ジスタが構成され、上記第2の半導体能動層と、鍍銅2
の半導体能動層に、上記半絶縁性半導体基板側とは反対
側に於て連結せ□る第2のソース電極及び第2のドレイ
ン電極と、上記第2の半導体能動層に、上記半絶縁性半
導体基111@とは反対側に於ける上記第2のソース電
極及び上記第2のドレイン電極間に於て、上記第2の半
導体能動層との間でショットキ接合又はPN接合を形成
すべく連結せる第2のゲート電極とを含んで、上記tJ
41の電界効果トランジスタとは異なるピンチオフ電圧
を有するWj42の電界効果トランジスタが構成されて
なる構成を有する半導体装置に於て、上記m1及び#1
2の半導体能動層が、同じ第1の半導体で且同じ厚さ、
不純物11R等の条件で形成され、 上記第1の半導体、上記第1の半導体とは異なる第2の
半導体、上記第1及i第2の半導体とは異なる第3の半
導体、及び金属中より選ばれた1つを第1のゲート電極
用材料、他の1つを#!2のケート電極用材料とすると
き、上記第1の電界効果トランジスタの第1のゲート電
極電界効果トラレジスタの第2のゲート電極が上記18
2のゲート電極用材料で形成され、上記第1の半導体能
動層の上記第1のゲート電極下の領域と、上記第2の半
導体能動層の上記第2のゲート電極下の領域とが、同じ
厚さ、不純物濃度等の条件を有する事を特徴とする半導
体装置。
[Claims] At least a first and a second semiconductor active layer are formed on a common semi-insulating semiconductor substrate, and the semiconductor active layer of W41 and the first semiconductor active layer are formed on a common semi-insulating semiconductor substrate. , the source electrode and the first drain electrode of the turtle 1 are ohmically connected on the side opposite to the semi-insulating semiconductor substrate @ side, and the first
In the semiconductor active layer of ゛, the first source electrode on the semi-insulating semiconductor substrate side and the opposite side ゛ and the above all
Between the drain electrodes of w! a first gate electrode coupled to form a Schottky junction or PN junction with the first semiconductor active layer; the second semiconductor active layer; Copper plating 2
a second source electrode and a second drain electrode connected to the semiconductor active layer on the side opposite to the semi-insulating semiconductor substrate; A connection is made between the second source electrode and the second drain electrode on the side opposite to the semiconductor substrate 111 to form a Schottky junction or a PN junction with the second semiconductor active layer. and a second gate electrode to provide the tJ
In a semiconductor device having a configuration in which a Wj42 field effect transistor having a different pinch-off voltage from that of the Wj41 field effect transistor is configured, the above m1 and #1
the two semiconductor active layers are made of the same first semiconductor and have the same thickness;
formed under conditions such as impurity 11R, selected from the first semiconductor, a second semiconductor different from the first semiconductor, a third semiconductor different from the first and second semiconductors, and a metal. One of them is the material for the first gate electrode, and the other one is #! When the gate electrode material of No. 2 is used, the first gate electrode of the first field effect transistor and the second gate electrode of the field effect transistor are
2, the region under the first gate electrode of the first semiconductor active layer and the region under the second gate electrode of the second semiconductor active layer are the same. A semiconductor device characterized by having certain conditions such as thickness and impurity concentration.
JP14594681A 1981-09-16 1981-09-16 Semiconductor device Pending JPS5848468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14594681A JPS5848468A (en) 1981-09-16 1981-09-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14594681A JPS5848468A (en) 1981-09-16 1981-09-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5848468A true JPS5848468A (en) 1983-03-22

Family

ID=15396692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14594681A Pending JPS5848468A (en) 1981-09-16 1981-09-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5848468A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791072A (en) * 1984-06-15 1988-12-13 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making a complementary device containing MODFET
JPH05500648A (en) * 1989-10-24 1993-02-12 メルヴィン・サイモン・アンド・アソシエーツ・インコーポレーテッド circular escalator
JP2013541199A (en) * 2010-09-13 2013-11-07 アナログ デバイシス, インコーポレイテッド Junction field effect transistor for voltage protection

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509378A (en) * 1973-05-23 1975-01-30
JPS544577A (en) * 1977-06-13 1979-01-13 Fujitsu Ltd Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509378A (en) * 1973-05-23 1975-01-30
JPS544577A (en) * 1977-06-13 1979-01-13 Fujitsu Ltd Semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791072A (en) * 1984-06-15 1988-12-13 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making a complementary device containing MODFET
JPH05500648A (en) * 1989-10-24 1993-02-12 メルヴィン・サイモン・アンド・アソシエーツ・インコーポレーテッド circular escalator
JP2013541199A (en) * 2010-09-13 2013-11-07 アナログ デバイシス, インコーポレイテッド Junction field effect transistor for voltage protection

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