JP3201447B2 - Semiconductor circuit device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky junction field effect transistor.
n Field-Effect Transisto
r), or a Schottky gate FET, or a metal-semiconductor field effect transistor (MESFET: Me).
tal-Semiconductor Field-E
The present invention relates to a semiconductor circuit device also referred to as an “effect transistor” and a manufacturing method thereof.

[0002]

2. Description of the Related Art As is well known, the above-mentioned semiconductor circuit device includes:
This is a transistor having a basic configuration as shown in FIG. A relatively high-resistance n-type semiconductor layer 2 serving as a channel is formed on a semi-insulating substrate 1. This n-type semiconductor layer 2
A metal gate 3 that makes Schottky contact with the channel 2c is joined on top of this, and a source 4 and a drain 5 that make ohmic contact with the channel 2c respectively are joined so as to sandwich this gate 3.

The principle of operation of this FET is that a depletion region 6 is generated at the junction between the gate 3 and the channel 2c due to the reverse voltage applied to the gate 3, and the channel 2 as a path for electrons is generated. The point is to narrow the width. Therefore, in this FET, the drain current is controlled by changing the channel width by the gate voltage.

Conventionally, the following three manufacturing methods have been known as methods for manufacturing such a semiconductor circuit device.

[0005] The first manufacturing method is described here by taking as an example the case where two transistors are formed on one substrate. As shown in FIG. 2 to FIG.
It consists of steps.

A) A semi-insulating semiconductor substrate 1 made of a III-V group compound semiconductor is prepared. For example, a GaAs substrate is used.

[0007] B) A patterned mask layer 10 A is formed on the substrate 1. Using this mask layer 10A as a mask, n-type impurity ions 11A are implanted to form ion implanted regions 2A.

C) After removing the mask layer 10A, a patterned mask layer 10B is formed on the substrate 1. Using this mask layer 10B as a mask, n-type impurity ions 11
B is implanted to form an ion implantation region 2B.

D) After removing the mask layer 10B, the substrate is heat-treated to activate the implanted ions, and the ion-implanted regions 2A and 2B are used as operation layers (n-type semiconductor regions). Subsequently, metal gates 3 that make Schottky contact are formed on the ion implantation regions 2A and 2B, respectively.

E) A source electrode 4 and a drain electrode 5 which are in ohmic contact with both sides of the gate 3 on the ion-implanted regions 2A and 2B are respectively formed.

The second manufacturing method will be described here by taking as an example the case where two transistors are formed on one substrate. This method includes the following five steps, as shown in FIGS.

A) A semi-insulating semiconductor substrate 1 made of a III-V compound semiconductor is prepared. For example, a GaAs substrate is used. A conductive semiconductor layer 2 is grown on the substrate 1.

B) A patterned mask layer 10A is formed on the conductive semiconductor layer 2. Using the mask layer 10A as a mask, the conductive semiconductor layer 2 is etched to a desired thickness.

C) The mask layer 1 patterned on the remaining surface of the conductive semiconductor layer 2 while leaving the mask layer 10A.
OB is formed. Using the mask layers 10A and 10B as masks, the conductive semiconductor layer 2 other than those having the mask layers 10A and 10B is removed by etching.

D) After removing the mask layers 10A and 10B, metal gates 3 which are in Schottky contact with each other are formed on the conductive semiconductor layers 2 and 2, respectively.

E) A source electrode 4 and a drain electrode 5 are formed on both sides of the gate 3 on each of the conductive semiconductor layers 2 and 2 in ohmic contact, respectively.

The third manufacturing method will be described here by taking as an example a case where one transistor is formed on one substrate. This method includes the following five steps, as shown in FIGS.

A) A semi-insulating semiconductor substrate 1 made of a III-V compound semiconductor is prepared. For example, a GaAs substrate is used.

B) A patterned mask layer 10A is formed on the substrate 1. Using this mask layer 10A as a mask, n-type impurity ions 11A are implanted to form ion implanted regions 2A.

C) The mask layer 10B is left as it is, and a patterned mask layer 10B is formed on the remaining portion of the substrate 1, that is, on the ion implantation region 2A. Using this mask layer 10B as a mask, n-type impurity ions 11B are implanted into both sides of the ion-implanted region 2A.
B and 2B are formed.

D) After removing the mask layers 10A and 10B, the substrate is heat-treated to activate the implanted ions, and the ion-implanted regions 2A and 2B are used as operating layers. Subsequently, a metal gate 3 that makes Schottky contact is formed on the ion implantation region 2A.

E) A source electrode 4 and a drain electrode 5 which are in ohmic contact with each other are formed on the ion-implanted regions 2B on both sides of the gate 3, respectively.

According to the first manufacturing method and the second manufacturing method, two transistors having mutually different characteristics can be formed on one substrate. But,
Compared to the second manufacturing method where etching is repeated twice,
The first manufacturing method using the ion implantation method is clearly easier to implement.

Further, according to the third manufacturing method, the n-type semiconductor region joined to the source electrode and the n-type semiconductor region joined to the drain electrode have sufficiently high n-type impurity concentrations, There is an advantage that the source electrode resistance and the drain electrode resistance can be reduced. A semiconductor circuit device having a structure in which the source electrode resistance and the drain electrode resistance are reduced can be manufactured by a manufacturing method using an etching process, as in the second manufacturing method. However, it is apparent that the third manufacturing method is easier to implement than the method of manufacturing by this etching process.

[0025]

As described above, of the above-mentioned conventional manufacturing methods, the first manufacturing method and the third manufacturing method are superior to other manufacturing methods. However, the first and third manufacturing methods and the semiconductor circuit devices obtained by these manufacturing methods have the following problems, respectively.

In the semiconductor circuit devices manufactured by the above-described first and third manufacturing methods, the n-type semiconductor region serving as an operation layer is formed by ion implantation into a semi-insulating semiconductor substrate. Therefore, the characteristics of the formed operation layer depend on the material characteristics of the semi-insulating semiconductor substrate that is the base material. This semi-insulating semiconductor substrate material often contains an amount of impurities that are not desirable due to the characteristics of the operation layer and cannot be ignored. Therefore, these conventional manufacturing methods have a first problem that the desired characteristics cannot be realized in the manufactured semiconductor circuit device.

Further, as described above, since the n-type semiconductor region serving as the operation layer is formed by ion implantation into the semi-insulating semiconductor substrate, the semi-insulating semiconductor substrate portion and the operation layer are not formed. One, no boundaries. That is, the surface of the n-type semiconductor region serving as the operation layer and the surface of the semi-insulating semiconductor substrate are the same surface. This means that there is no layer that prevents electrons in the n-type semiconductor region from moving to the surface of the semi-insulating semiconductor substrate. On the other hand, a defect layer is often formed on the surface of a semi-insulating semiconductor substrate during or after the manufacture of a device. When this defect layer is present on the surface of the semi-insulating semiconductor substrate, there is no layer that prevents the electrons in the n-type semiconductor region from moving to the surface of the semi-insulating semiconductor substrate as described above. At the defect layer. As a result, when the transistor is turned on, noise is generated from the defective layer, and the performance of the device is significantly reduced. This is the second problem in the conventional manufacturing method and the semiconductor device manufactured by the method.

Although no solution has been proposed for the first problem, the following solution has been proposed for the second problem.

The solution is a method described in the following three documents. Japanese Patent Application Laid-Open No. 04-216636 (Japanese Patent Application No. 02-411177), "GaAs SURFA
CEPASSIVATION BY InGaP TH
IN FILM "Mat. Res. Soc. Symp.
Proc. Vol 240, pp777-781, and “Si-implanted InGaP / GaAs”
metal-semiconductor field
d-effect transistors "App
l. Phys. Lett. 60 (16), 20 Apr
il 1992. These are three documents. The solution described in these documents is to form an InGaP layer having an energy band gap wider than that of the GaAs substrate body on the substrate body made of GaAs, and to disperse impurity ions in the GaAs substrate body through the InGaP layer. To form an impurity ion implanted region to be an operation layer. According to this method, since the InGaP barrier layer having a wide energy band gap is interposed between the substrate surface and the impurity ion-implanted region, the impurity ion-implanted region serving as the active layer is formed on the defect layer existing on the substrate surface. The electrons do not move and reach.

However, in this method and the semiconductor circuit device obtained by this method, if the efficiency and the performance are to be further improved, the following new problems arise.

That is, conventionally, if a heat-resistant metal is used as a gate electrode material, the gate electrode is used as a mask,
There has been proposed a method of efficiently manufacturing a semiconductor circuit device by implanting impurity ions into a substrate, performing heat treatment as it is, and activating the impurity ion implanted regions. About this method, for example, “Reac
tsply sputtered WSiN fill
msuppresses As and Gaou
tdiffusion "J. Vac. Sci. Tech.
nol. B 6 (5), Sep / Oct 1988. ,
pp-1526-1529, and this document reports that WSiN is ideal as a heat-resistant metal for such a gate electrode.

When the manufacturing method of using such a heat-resistant metal as a gate electrode material and implanting impurity ions using the gate electrode as a mask is applied to the manufacture of the semiconductor circuit device having the InGaP barrier layer, The following problems occur and are not practical.

That is, the heat treatment causes a reaction between the gate electrode and the InGaP layer, deteriorating the Schottky junction characteristics and causing an ohmic junction. The problem is that, after completing the impurity ion implantation into the substrate and activating the impurity ion implantation region by heat treatment, even when forming a gate electrode, heat may be applied to the device later, Occurs similarly.

According to the present invention, as described above, when forming an InGaP layer suitable as a barrier layer for preventing electrons from reaching the defect layer existing on the substrate surface from the impurity injection region serving as the operation layer, this layer is used. When the gate electrode and the Schottky junction receive heat, the Schottky junction characteristics are deteriorated to form an ohmic junction, and the above-mentioned operation layer is affected by the material characteristics of the substrate, and the expected characteristics are degraded. It is an object of the present invention to comprehensively solve the problem that it cannot be obtained and to obtain a semiconductor circuit device having high characteristics.

[0035]

According to the present invention, there is provided a semiconductor circuit device comprising: a semi-insulating semiconductor substrate comprising a first III-V compound semiconductor; A semi-insulating barrier layer formed of InGaP having a band gap, formed on the semi-insulating semiconductor substrate, and formed on an upper portion of the semiconductor substrate in contact with the barrier layer, wherein the semiconductor substrate is a base material an n-type semiconductor region in which n-type impurity ions are diffused; and a semiconductor having a narrow energy band gap compared to the InGaP and containing no In as a component, and formed on the barrier layer. A heat-resistant metal gate electrode formed on the protective layer on the n-type semiconductor region and Schottky-bonded with the protective layer; A source electrode and a drain electrode formed at both positions of the protective layer on the type semiconductor region and sandwiching the gate electrode, and the protective layer and the ohmic connection to the n-type semiconductor region via the barrier layer. It is characterized by having.

On the other hand, in the first method of manufacturing a semiconductor circuit device according to the present invention, a first III-V compound semiconductor is formed on a semi-insulating semiconductor substrate as compared with the first III-V compound semiconductor. With wide energy band gap
Forming a semi-insulating barrier layer made of GaP, forming a semi-insulating protective layer made of a semiconductor that does not contain In as a component and has a narrower energy band gap than that of InGaP; Forming a patterned mask layer on the layer, injecting n-type impurity ions into the substrate using the mask layer as a mask to form an n-type impurity ion-implanted region, and removing the mask layer; Depositing a heat treatment protection film on the layer, heating the substrate to activate each of the impurity ion implanted regions to form an n-type semiconductor region, and forming an opening at a position on the n-type semiconductor region of the heat treatment protection film. Providing, forming a gate electrode made of a heat-resistant metal, providing an opening at both sides of the gate electrode of the heat treatment protection film, forming a source electrode and a drain electrode, Characterized in that it has.

In a second method of manufacturing a semiconductor circuit device according to the present invention, a patterned first mask layer is formed on a semi-insulating semiconductor substrate made of a first III-V compound semiconductor. Implanting n-type impurity ions into the substrate by using as a mask to form a first impurity ion-implanted region; and, after removing the first mask layer, depositing the first impurity ion on the semi-insulating semiconductor substrate. Forming a second mask layer having a pattern different from that of the second mask layer, implanting n-type impurity ions using the second mask layer as a mask, and forming a second impurity ion implanted region; Forming a semi-insulating barrier layer made of InGaP having a wider energy band gap than the first group III-V compound semiconductor on the substrate;
Forming a semi-insulating protective layer made of a semiconductor having no energy band gap as compared with P and containing no In as a component, depositing a heat-treated protective film on the protective layer, and heating the substrate. Activating each of the impurity ion-implanted regions to form an n-type semiconductor region; providing an opening at a position on the n-type semiconductor region of the heat treatment protection film to form a gate electrode made of a heat-resistant metal; Forming an opening on both sides of the gate electrode of the heat treatment protection film to form a source electrode and a drain electrode.

Further, in the third method of manufacturing a semiconductor circuit device according to the present invention, a semi-insulating semiconductor substrate made of a first III-V compound semiconductor is formed on a semi-insulating semiconductor substrate as compared with the first III-V compound semiconductor. With wide energy band gap
Forming a semi-insulating barrier layer made of GaP, forming a semi-insulating protective layer made of a semiconductor that does not contain In as a component and has a narrower energy band gap than that of InGaP; A first mask layer having a required pattern is formed on the layer, and n-type impurity ions are implanted from the protective layer side using the first mask layer as a mask to form a first impurity ion implanted region. Forming a gate electrode made of a heat-resistant metal on the protective layer on the ion-implanted region after removing the mask layer; and forming a pattern different from the first mask layer on the protective layer. A second mask layer, and n-type impurity ions are implanted from the protective layer side using the second mask layer and the gate electrode as a mask to form a second impurity ion implanted region. That a step, after removing the second mask layer, depositing a heat-treated protective film on the protective layer, the substrate is heated to activate the respective impurity ion implantation region n
A step of forming a source semiconductor region and a step of forming a source electrode and a drain electrode on both sides of the gate electrode of the heat treatment protective film.

Further, in a fourth method of manufacturing a semiconductor circuit device according to the present invention, a patterned first mask layer is formed on a semi-insulating semiconductor substrate made of a first III-V compound semiconductor. Implanting n-type impurity ions into the substrate by using as a mask to form a first impurity ion implanted region; and removing the first mask layer.
Forming a semi-insulating barrier layer made of InGaP having a wider energy band gap than the first group III-V compound semiconductor; and having a narrow energy band gap compared to the InGaP, Forming a semi-insulating protective layer made of a semiconductor containing no, a step of forming a gate electrode made of a heat-resistant metal on the protective layer on the ion-implanted region, and a step of forming the first electrode on the protective layer. Forming a second mask layer having a pattern different from that of the mask layer; using the second mask layer and the gate electrode as a mask, implanting n-type impurity ions from the protective layer side; Forming an implanted region and, after removing the second mask layer, depositing a heat-treated protective film on the protective layer and heating the substrate to activate the impurity ion implanted region Forming an n-type semiconductor region;
Providing openings on both sides of the gate electrode of the heat treatment protective film, forming a source electrode and a drain electrode,
It is characterized by having.

[0040]

In each of the structures of the apparatus and the manufacturing method of the present invention, the semiconductor substrate is composed of a single semi-insulating semiconductor substrate alone, and a single semi-insulating semiconductor substrate and a semi-insulating semiconductor substrate formed thereon by epitaxial growth. There is a configuration including a semiconductor layer. In the present invention, when the purity of the constituent material of the single semi-insulating semiconductor substrate used as the substrate is high, the epitaxially grown semi-insulating semiconductor layer is omitted, and the substrate is constituted only by the single semi-insulating semiconductor substrate. It is also possible. However, in many cases, commercially available substrate materials contain a considerable amount of impurities and have poor surface characteristics. Therefore, it is usually better to form an epitaxial layer on a single substrate to form a substrate for lamination, implant impurity ions into the epitaxial layer, and form impurity ion implanted regions in the epitaxial layer. In this case, since the epitaxial layer serving as the base of the impurity-implanted region can be easily made to have high purity, the characteristics of the impurity-implanted region serving as the operation layer can be improved. In addition, the epitaxial layer has high purity, good surface characteristics, and the lattice constant of the layer can be controlled. Therefore, the thickness of the InGaP barrier layer formed on the layer can be easily controlled, and the barrier characteristics can be easily controlled. There is also an advantage that the improvement in is easy.

In the structure of the present invention, in the impurity ion-implanted region formed in the semiconductor substrate below the barrier layer using the substrate as a base, the source electrode is more likely to be formed than the region located below the gate electrode. In addition, a structure in which the impurity ion concentration is higher in a region located below the drain electrode can be achieved. Furthermore, a configuration in which the thickness of the region located below the gate electrode is significantly smaller than the thickness of the region located below the source electrode and the drain electrode. Note that, as described above, when the semi-insulating semiconductor substrate has a configuration including a single semi-insulating semiconductor substrate and a semi-insulating semiconductor layer formed thereon by epitaxial growth, the impurity ion implanted region is It is formed in a semiconductor layer by epitaxial growth.

In the present invention, the presence of the semi-insulating protective layer prevents the reaction between the InGaP layer and the gate electrode made of a heat-resistant metal, and does not deteriorate the Schottky junction of the gate electrode. The formation of this protective layer was made based on the following findings. That is, when the InGaP layer is used as the barrier layer, the cause of the degradation of the Schottky junction of the gate electrode is, for example, when WSiN is used as the heat-resistant gate metal material, tungsten in the metal material and indium in the InGaP layer are different. Was found to be reacted by heat. Therefore, as described above, it is important that the constituent material of the protective layer does not contain indium. In order to fulfill the role of such a protective layer, the thickness of the protective layer is desirably 250 Å or less. Moreover,
The thickness is desirably 50 to 250 Å.

As a heat-resistant metal material constituting the gate electrode, WSiN is preferable.

In the structure of the present invention, a structure in which a plurality of impurity-implanted regions, gate electrodes, source electrodes, and drain electrodes are provided on one substrate is also possible. In this case, the characteristics of each element can be differently configured individually, and each element can be functionally connected to form a semiconductor circuit element in which one large-scale circuit is formed on one substrate. It is possible. In order to form a plurality of elements on one substrate in this manner, in the method of the present invention, the first impurity ion implantation step using the mask layer may be repeated a plurality of times by changing the opening position of the mask.

[0045]

Embodiments of the present invention will be described below.

(Embodiment 1) The method of manufacturing a semiconductor circuit device according to the present invention shown in FIGS. 17 to 24 includes the following sequential steps.

First, as shown in FIG. 17, a semi-insulating semiconductor substrate 21 made of GaAs is prepared as a first semi-insulating III-V compound semiconductor.

Then, the semi-insulating semiconductor substrate body 21
A semi-insulating barrier layer 22 made of InGaP having a wider energy band gap than the first semi-insulating III-V compound semiconductor and having a thickness of, for example, 100 A is formed thereon.
And a semiconductor having an energy band gap narrower than InGaP and a thickness of, for example, 100 A
The semi-insulating protective layer 23 made of aAs is formed in that order by a known epitaxial growth method. As a result, a semiconductor substrate 24 having a configuration in which the semi-insulating barrier layer 22 and the semi-insulating protective layer 23 are laminated on the semi-insulating semiconductor substrate main body 21 in that order is obtained (FIG. 18).

Next, a mask layer 25 having a required pattern is formed on the semiconductor substrate 24 by various methods known per se (FIG. 19).

Next, with respect to the semiconductor substrate 24, n is applied from the side of the semi-insulating protective layer 23 via the protective layer 23 and the barrier layer 22.
For example, an Si ion 26 as a type impurity is
Acceleration energy of 0 keV, for example, 1.5 × 10 ¹³ / c
By performing an implantation process at an implantation amount of m ² , an n-type impurity ion implantation region 27 is formed on the semi-insulating barrier layer 22 side of the semi-insulating semiconductor substrate main body 21 (FIG. 20).

Next, a mask layer 25 is formed on the protective layer 23.
It is itself removed by various known methods (FIG. 2).
1).

Next, on the protective layer 23, a heat-treated protective layer 2 made of, for example, SiN and having a thickness of, for example, 1500A.
8 is formed by various methods known per se (FIG. 22).

Next, the substrate is heated at a temperature of, for example, 800 ° C. for 10 minutes to activate the n-type impurity ion-implanted region 27.
An n-type semiconductor region 29 is formed from the n-type impurity ion implanted region 27 on the semi-insulating barrier layer 22 side of FIG.
3).

Next, after removing the heat-treated protective layer 28 on the protective layer 23, a heat-resistant gate electrode 31 made of, for example, WSiN for forming a Schottky junction 30 with the semi-insulating protective layer 23 is formed on the protective layer 23. And the semi-insulating protective layer 2 at both positions sandwiching the n-type semiconductor region 29 and the semi-insulating gate electrode 31.
3 and a source electrode 32 and a drain electrode 3 ohmically connected to each other via a semi-insulating barrier layer 22.
3 are formed by various methods known per se (FIG. 24). In FIG. 24, reference numeral 34 denotes a protective layer made of an insulating material formed on the semiconductor substrate 24 when forming the gate electrode 31, the source electrode 32, and the drain electrode 33. The ohmic junction between the source electrode 32 and the drain electrode 33 is realized by depositing an electrode metal and then performing a heat treatment at a relatively low temperature (350 to 400 ° C.) to diffuse the electrode metal into the semiconductor. The diffusion is alloyed so that the source electrode 31
And the drain electrode 33 come into ohmic contact with the n-type semiconductor region 29.

The above is the first embodiment of the method for manufacturing a semiconductor circuit device according to the present invention.

According to the method of manufacturing a semiconductor circuit device according to the present embodiment, the n-type semiconductor region 29 as an operation layer is formed on the semi-insulating semiconductor substrate 21 according to the above-described conventional method of manufacturing a semiconductor circuit device. The n-type semiconductor region 29 is used as an operation layer as a planar dimension, a three-dimensional depth, and an n-type impurity. It is easier to form a semiconductor device having a concentration or the like controlled to a desired value than in the above-described conventional method of manufacturing a semiconductor circuit device.

Further, in the semiconductor circuit device of the present embodiment, the n-type semiconductor region 29 as the operation layer does not form the surface of the semiconductor substrate, and is located between the n-type semiconductor region 29 and the surface of the semiconductor substrate. Has a configuration in which a semi-insulating barrier layer 22 and a semi-insulating protective layer 23 are interposed in that order. Therefore, as shown in FIG. 25, even if the defect layer 35 is formed on the surface of the semiconductor substrate 24 at the time of manufacturing the device or after the device is manufactured, the n-type semiconductor region 29 A layer that acts as a barrier between the electrons 36 in the n-type semiconductor region 29 and the defect layer 35 is interposed between the defect layer 35 and the defect layer 35. Therefore, if the semi-insulating barrier layer 22 is formed relatively thick, that is, the semi-insulating barrier layer 22 made of a material made of InGaP has a thickness of 50 A or more, for example, a thickness of 100 A as described above. If formed, the electrons 36 in the n-type semiconductor region 29 are unlikely to reach the defect layer 35 on the surface of the semiconductor substrate 24, and therefore, when operating as a semiconductor circuit device, noise is generated by the defect layer 35. Can be effectively avoided.

This can be confirmed by the following experiment. That is, (a) a semiconductor substrate 24 in which a semi-insulating barrier layer 22 and a semi-insulating protective layer 23 are laminated on a semi-insulating semiconductor substrate main body 21 in that order as shown in FIG. Wavelength 0.51
45 μm), and the intensity of light with respect to the wavelength obtained by emitting light from the semiconductor substrate 24 at that time, that is, the photoluminescence emission intensity was measured. The emission intensity was obtained as shown by a curve A in FIG. On the other hand, a semi-insulating semiconductor substrate body 21 shown in FIG. 17 corresponding to a semi-insulating semiconductor substrate in a semiconductor circuit device manufactured by the above-described conventional method for manufacturing a semiconductor circuit device has a similar structure. When the photoluminescence emission intensity was measured, the emission intensity was obtained as shown by a curve B in FIG. (B) On the semiconductor substrate shown in FIG. 18, a heat treatment protection layer similar to that described above with reference to FIG.
Next, the semiconductor substrate on which the heat treatment protective layer is formed is subjected to the same heat treatment at 800 ° C. for 10 minutes as described above with reference to FIG. 23, and the photoluminescence emission intensity is measured as described above. As a result, the luminous intensity was changed as shown in FIG.
The curve A is obtained on the semi-insulating semiconductor substrate body 21 shown in FIG. 17 corresponding to the semi-insulating semiconductor substrate in the conventional semiconductor circuit device described above. A similar heat treatment protection layer is formed, and then the semi-insulating semiconductor substrate 21 forming the heat treatment protection layer is formed.
Then, after performing the same heat treatment, the same photoluminescence emission intensity was measured, and the emission intensity was obtained as shown by a curve B in FIG. further,
(C) Regarding the semiconductor substrate 24 shown in FIG.
The same photoluminescence emission intensity was measured by changing the thickness of the semi-insulating barrier layer 22, and the result shown in FIG. 28 was obtained.

Further, in the semiconductor circuit device shown in the first embodiment, a gate electrode 31 is formed on a semiconductor substrate by connecting to a semi-insulating protective layer 23 so as to form a Schottky junction 30 therewith. It has the configuration that has been. Therefore,
The Schottky junction 30 between the gate electrode 31 and the semi-insulating protective layer 23 is formed from the gate electrode 31 side as n
A barrier to electrons is formed when the type semiconductor region 29 is viewed. However, since the semi-insulating barrier layer 22 for electrons exists between the semi-insulating protective layer 23 and the n-type semiconductor region 29, as shown in FIG. Even if the layer 22 is formed of a material (for example, GaAs) having only a lower energy of the conduction band bottom than the material of the layer (InGaP), its thickness is not so large, that is, the semi-insulating protective layer 23. However, as described above, for example, in the case of GaAs, if it has a thickness of 50 to 250 A, the energy of the conduction band bottom of the semi-insulating protective layer 23 is reduced by a dotted line as shown in FIG. It increases from the state to the state shown by the solid line. As a result, the energy at the bottom of the conduction band on the surface of the semi-insulating protective layer 23, and thus on the surface of the semiconductor substrate, rises to the energy at or near the bottom of the conduction band of the semi-insulating barrier layer 22. The height of the barrier against electrons by the Schottky junction 30 as viewed from the n-type semiconductor region 29 side as the operation layer from the side is higher than that without the semi-insulating barrier layer 22. For this reason, when this semiconductor circuit device is used as a binary logic circuit element (on / off element), the logic amplitude can be increased as compared with the case where the semi-insulating barrier layer 22 is not provided. The operation margin as a value logic circuit element can be increased.

The semiconductor circuit device shown in the present embodiment has a configuration in which the gate electrode 31 has the semi-insulating protective layer 23 connected so as to form the Schottky junction 30. For this reason, the gate electrode 31 and the semi-insulating protective layer 23 are formed by combining the element of the material forming the gate electrode 31 with the semi-insulating protective layer 23 when relatively high heat is applied to the semiconductor circuit device. If the gate electrode 31 is made of a material using an element that does not easily react with the element of the material constituting the material, that is, the gate electrode 31 is made of a material made of, for example, WSiN as described above. And the semi-insulating protective layer 23 is made of GaAs as described above.
When the semiconductor circuit device is made of a material consisting of
When the semi-insulating protective layer 23 is made of a material made of, for example, GaAs as described above, for example, at 800 ° C. or more, the gate electrode 31 is turned on. It is possible to effectively avoid that the constituent material (for example, WSiN) and the constituent material (for example, GaAs) of the semi-insulating protective layer 23 react with each other. The semi-insulating protective layer 23
Of the semi-insulating protective layer 23 is made of, for example, GaAs, so long as the effect of increasing the operation margin as a binary logic circuit element is not lost. In this case, as shown in FIG.
If the semiconductor circuit device has a thickness of 0A, relatively high heat (such as 800 ° C. or more as described above) is applied to the semiconductor circuit device.
And the gate electrode 31 is made of WSiN which easily reacts with In in the semi-insulating barrier layer,
Elements constituting the material (WSiN) of the gate electrode 31, particularly W and the material (InGa) of the semi-insulating barrier layer 22
It is possible to effectively prevent the elements constituting P), particularly In, from reacting with each other.

This is because the semi-insulating barrier layer 22 is made of InGaP as described above,
When the gate electrode 31 is made of a material made of WSiN and the semi-insulating protective layer 23 is made of a material made of GaAs, heat is applied to this semiconductor circuit device at a temperature of 800 ° C. for 10 minutes. Thereafter, the height of the barrier against electrons by the Schottky junction 30 as viewed from the gate electrode 31 side to the n-type semiconductor region 29 side with respect to the thickness of the semi-insulating protective layer 23 was measured, and the result shown in FIG. 29 was obtained. It will be clear from this.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS.

In the manufacturing method of the semiconductor circuit device shown in the second embodiment, a semiconductor circuit device having first and second transistors having mutually different characteristics is manufactured by the following sequential steps.

First, a semi-insulating semiconductor substrate 21 similar to that of the first embodiment is prepared (FIG. 30).

Then, a second III-V compound semiconductor (for example, GaAs) is formed on the semi-insulating semiconductor substrate 21.
s), a semi-insulating semiconductor layer 40 and a semi-insulating barrier layer (InGaP layer) 22 having an energy band gap narrower than that of InGaP forming the semi-insulating barrier layer 22, and having a thickness of, for example, 100 A. And a semi-insulating protective layer 23 made of a semiconductor having a thickness of, for example, GaAs. As a result, the semiconductor substrate 2 has a configuration in which the semi-insulating semiconductor layer 40, the semi-insulating barrier layer 22, and the semi-insulating protective layer 23 are stacked on the semi-insulating semiconductor substrate 21 in that order.
4 (FIG. 31).

Next, a first mask layer 25A having a required first pattern is formed on the semiconductor substrate 24 by various methods known per se (FIG. 32).

Next, while the semiconductor substrate 24 is masked by the first mask layer 25A, from the semi-insulating barrier layer 22 side, for example, Si ions 26A as n-type impurities are applied at 25 keV, for example. Acceleration energy,
For example, by performing an implantation process at an implantation amount of 1.5 × 10 ¹³ / cm ² , the semi-insulating semiconductor layer 40 is shifted from the semi-insulating barrier layer 22 side to the semi-insulating semiconductor substrate 21 side in the semiconductor substrate 24. A first n-type impurity ion implanted region 27A is formed in a region having a required depth.
3).

Next, the first mask layer 25A is removed from the semiconductor substrate 24 by various methods known per se (FIG. 34).

Next, on the semiconductor substrate 24, at a position different from the position on the first n-type impurity ion implanted region 27A,
Second mask layer 25B having required second pattern
Is formed by various methods known per se (FIG. 35).

Next, while the semiconductor substrate 24 is masked by the second mask layer 25B, for example, Si ions 26B as n-type impurities are applied from the semi-insulating barrier layer 22 side to the above-described ions. Acceleration energy of, for example, 30 keV higher than that of the ion 26
By performing an implantation process at the same implantation amount of 1.5 × 10 ¹³ / cm ² as in A, the semi-insulating semiconductor substrate is placed in the semiconductor substrate 24 from the semi-insulating barrier layer 22 side of the semi-insulating semiconductor layer 40. A first n-type impurity ion implanted region 2
A second n-type impurity ion implanted region 27B is formed in a region having a required depth deeper than that of FIG. 7A (FIG. 3).
6).

Next, the second mask layer 25B is removed from the semiconductor substrate 24 by various methods known per se (FIG. 37).

Next, on the semiconductor substrate 24, for example, SiN
The heat treatment protection layer 28 having a thickness of, for example, 1500 A is formed by various methods known per se (FIG. 38).

Next, for example, 8
The first and second n-type impurity ion implanted regions 27A and 27B are activated by a heat treatment of heating at a temperature of 00 ° C., for example, for 10 minutes.
4, the semi-insulating barrier layer 22 of the semi-insulating semiconductor layer 40
A first n-type impurity ion implanted region 27 is formed in a region having a required depth from the side to the semi-insulating semiconductor substrate 21 side.
A forms the first n-type semiconductor region for operation layer 29A from A, and forms the second n-type semiconductor region for operation layer 29B from the second n-type impurity ion implanted region 27B (FIG. 3).
9).

Next, after removing the heat treatment protection layer 28 from the semiconductor substrate 24, the semi-insulating protection layer 23 and the first and second n-type semiconductor regions 2 for the operation layer are formed on the semiconductor substrate 24.
First and second gate electrode layers 31A and 31B made of, for example, WSiN connected to form first and second Schottky junctions 30A and 30B respectively on 9A and 29B, and a first operating layer At the two positions sandwiching the n-type semiconductor region for use 29A and the first gate electrode 31A, ohmic connections are respectively made through the semi-insulating protective layer 23 and the barrier layer 22.
Source electrode 32A and first drain electrode 33A
And a second source electrode ohmically connected through a semi-insulating protective layer 23 and a barrier layer 22 at both positions across the second operating layer n-type semiconductor region 29B and the second gate electrode 31B. 32B and the second drain electrode 33B are formed by various methods known per se (FIG. 40). In FIG. 40, 34
Are the gate electrodes 31A and 31B and the source electrodes 32A and 3
When forming the 2B and the drain electrodes 33A, 33B, it is a protective layer made of an insulating material formed on the semiconductor substrate 24. The ohmic junction between the source electrodes 32A and 32B and the drain electrodes 33A and 33B is formed at a relatively low temperature (350 to 400 ° C.) after the electrode metal is deposited.
This is realized by heat-treating the metal and diffusing the electrode metal into the semiconductor. The diffusion portion is alloyed, so that the source electrodes 32, 32B and the drain electrodes 33A, 33B
Is ohmically connected to the n-type semiconductor regions 29A and 29B.

The above is the second embodiment of the present invention.

The semiconductor circuit device (FIG. 40) obtained in the second embodiment includes an n-type semiconductor region 29A for a first operation layer, a first gate electrode 31A, a first source electrode 32A, and a first source electrode 32A. A first transistor MA including a drain electrode 33A and a second operating layer n-type semiconductor region 29;
B, second gate electrode 31B, and second source electrode 32B
And a second drain electrode 33B having characteristics different from those of the first transistor MA.
It is evident that the transistor MB of FIG. Therefore, according to the manufacturing method shown in the second embodiment, the semiconductor integrated circuit device includes the first and second transistors MA and MB having mutually different characteristics.
It can be easily manufactured.

In the semiconductor circuit device manufactured by the manufacturing method shown in the second embodiment, the first and second transistors MA and MB include the first and second transistors MA and MB.
The operation-layer n-type semiconductor regions 29A and 29B are formed on a semi-insulating semiconductor layer 4 formed on a semi-insulating semiconductor substrate 21.
0. And
In this case, the semi-insulating semiconductor layer 40 can be easily formed on the assumption that the semi-insulating semiconductor layer 40 contains much less undesirable impurities than the semi-insulating semiconductor substrate 21. 40 can be formed of a material different from the semi-insulating semiconductor substrate 21. Therefore, according to the present method, the semiconductor integrated circuit device is divided into the first and second semiconductor integrated circuit devices.
Transistors MA and MB are provided in semiconductor body 29 for the first and second operation layers in semi-insulating semiconductor substrate body 1.
And 29B have characteristics different from those in the case where they are formed, and the characteristics are excellent.
It can be easily formed.

In the semiconductor circuit device obtained by this method, the first and second transistors MA and MB are the first and second n-type semiconductor regions 2 for operating layers.
9A and 29B do not form the surface of the semiconductor substrate 24, and the first and second n-type semiconductor regions 29 for operation layers
A semi-insulating barrier layer 22 is interposed between each of A and 29B and the surface of the semiconductor substrate 24. For this reason, even if a defect layer is formed on the surface of the semiconductor substrate 24 at the time of manufacturing the semiconductor circuit device or formed after the semiconductor circuit device is manufactured,
Between each of the first and second n-type semiconductor regions for operation layer 29A and 29B and the defect layer, electrons of the first and second n-type semiconductor regions for operation layer 29A and 29B are directed to the defect layer. A layer that acts as a barrier is interposed.
Therefore, the first and second n-type semiconductor regions 29 for the operation layer
The fact that the electrons of A and 29B are unlikely to reach the defect layer on the surface of the semiconductor substrate 24, so that when the first and second transistors MA and MB operate, they generate noise due to the defect layer. Can be effectively avoided.

Further, in the present apparatus, the first and second
Transistors MA and MB are provided on semiconductor substrate 24 with first and second gate electrodes 31A and 31B.
Is formed on the semi-insulating protective layer 23 between them.
And the second Schottky junctions 30A and 30B are formed so as to be connected to each other. Therefore, the Schottky junctions 30A and 30B between the first and second gate electrodes 31A and 31B and the semi-insulating protective layer 23 are respectively connected to the first and second gate electrodes 31A and 31B from the first and second gate electrodes 31A and 31B. A barrier for electrons is formed when the n-type semiconductor regions 29A and 29B for the operation layer 2 are viewed. However, since the semi-insulating barrier layer 22 for electrons is present, a Schottky junction is seen from the first and second gate electrodes 31A and 31B to the first and second n-type semiconductor regions for operation layer 29A and 29B, respectively. The configuration is such that the height of the barrier by 30A and 30B is higher than when the semi-insulating barrier layer 22 is not provided. Therefore, when the first and second transistors MA and MB are used as binary logic circuit elements (ON / OFF elements), the logic amplitude is increased as compared with the case where the semi-insulating barrier layer 22 is not provided. Therefore, the operation margin as a binary logic circuit element can be increased.

Further, in the semiconductor circuit device shown in the second embodiment, the first and second transistors MA and MB have the first and second gate electrodes 31A and 31B respectively having the first and second gate electrodes 31A and 31B. Schottky joint 30
A and a semi-insulating protective layer 23 connected to form 30B. Therefore, each of the first and second gate electrodes 31A and 31B and the semi-insulating protective layer 23 are connected to the first and second transistors MA and MB when relatively high heat is applied. And second gate electrodes 31A and 31A
1B and the material of the material forming the semi-insulating protective layer 23, the material of the material forming the semi-insulating protective layer 23 is not easily reacted with each other.
Damage to Schottky junction can be avoided. That is,
If the first and second gate electrodes 31A and 31B are made of a material made of, for example, WSiN as described above, and the semi-insulating protective layer 23 is made of a material made of, for example, GaAs as described above, When relatively high heat such as 800 ° C. or more is applied to the first and second transistors MA and MB, the material (eg, WSiN) forming the first and second gate electrodes 31A and 31B is changed. It is possible to effectively avoid that the element and the element of the material (for example, GaAs) constituting the semi-insulating protective layer 23 react with each other. The semi-insulating protective layer 23
Of the semi-insulating protective layer 23 is made of, for example, GaAs, so long as the effect of increasing the operation margin as a binary logic circuit element is not lost. In this case, if it has a thickness of, for example, 50 to 250 A, a similar problem occurring between the first and second gate electrodes 31A and 31B and the semi-insulating barrier layer 22 can be avoided. That is, the first and second gate electrodes 31A and 31B are made of a material such as WSiN that easily reacts with the InGaP semi-insulating barrier layer 22, and the first and second transistors MA and MB are, for example, 800 ° C. Even if the above relatively high heat is applied, the first and second gate electrodes 31A and 31A
The element constituting the material of B, in particular, W and the element constituting the material of the semi-insulating barrier layer 22, are effectively prevented from mutually reacting with each other, thereby preventing the Schottky junction from deteriorating. Can be prevented.

Therefore, according to the method of manufacturing the semiconductor circuit device according to the present invention shown in the second embodiment, the semiconductor circuit device is formed by the first and second transistors MA and MB.
Even if it is given relatively high heat, it can be easily manufactured as operating with the desired characteristics.

(Embodiment 3) Next, a third embodiment of a method of manufacturing a semiconductor circuit device according to the present invention will be described with reference to FIGS.

In FIG. 41 to FIG.
The same components as those shown in FIG. 2 are denoted by the same reference numerals, and detailed illumination is omitted.

The method of manufacturing the semiconductor circuit device according to the present invention shown in FIGS. 41 to 51 includes the following sequential steps.

That is, the same semi-insulating semiconductor substrate body 21 is prepared as in the case of the method of manufacturing the semiconductor integrated circuit device shown in the first and second embodiments (FIG. 41).

Then, the semi-insulating semiconductor substrate main body 21
Above, the semi-insulating semiconductor layer 40 and the semi-insulating semiconductor layer 40 similar to the case of the method of manufacturing the semiconductor circuit device shown in the first and second embodiments are applied in accordance with the method of manufacturing the semiconductor circuit device shown in the first and second embodiments. An insulating barrier layer 22 and a semi-insulating protective layer 23 made of, for example, GaAs as a semiconductor having a narrow energy band gap compared to InGaP forming the semi-insulating barrier layer 22 and having a thickness of, for example, 100 A. Are formed in that order by the epitaxial growth method. Therefore, the semiconductor substrate 2 having a configuration in which the semi-insulating semiconductor layer 40, the semi-insulating barrier layer 22, and the semi-insulating protective layer 23 are laminated on the semi-insulating semiconductor substrate body 21 in that order.
4 (FIG. 42).

Next, a first mask layer 25 is formed on the semiconductor substrate 24 in the same manner as in the method of manufacturing the semiconductor integrated circuit device shown in the first and second embodiments (FIG. 43).

Next, ions of the n-type impurity 26 are implanted into the semiconductor substrate 24 while being masked by the first mask layer 25 in the same manner as in the above-described manufacturing method. 24, a first n-type impurity ion implanted region 27 is formed (FIG. 44).

Next, the first mask layer 25 is removed from the semiconductor substrate 24 (FIG. 45).

Next, a second mask layer 25 'is formed on the semiconductor substrate 24 (FIG. 46).

Next, while the semiconductor substrate 24 is masked by the second mask layer 25 ′, an ion 26 ′ of an n-type impurity is implanted into the semiconductor substrate 24 so that the second and second ions are implanted into the semiconductor substrate 24. Third n-type impurity ion implanted regions 27S and 27D are formed (FIG. 47).

Next, the second mask layer 25 'is removed from above the semiconductor substrate 24 (FIG. 48).

Next, a heat treatment protection layer 28 is formed on the semiconductor substrate 24 (FIG. 49).

Next, the heat treatment of the semiconductor substrate 24 causes the n-type semiconductor region 2 for the operation layer to be formed in the semiconductor substrate 24.
9. An n-type semiconductor region 29S for the source electrode and an n-type semiconductor region 29D for the drain electrode are formed (FIG. 50).

Next, after removing the heat treatment protective layer 28 from the semiconductor substrate 24, a Schottky junction 30 is formed on the semi-insulating protective layer 23 and the n-type semiconductor region 29 for the operating layer on the semiconductor substrate 24. A gate electrode layer 31 made of WSiN and an n-type semiconductor region 2 for a source electrode
A source electrode 32 and a drain electrode 33 that are ohmically connected to the 9S and the n-type semiconductor region 29D for the drain electrode through the semi-insulating protective layer 23 and the semi-insulating barrier layer 22, respectively, are formed (FIG. 51). In FIG. 51, when forming the gate electrode 31, the source electrode 32 and the drain electrode 33, the semiconductor substrate 2
4 is a protective layer made of an insulating material formed on The ohmic junction between the source electrode 32 and the drain electrode 33 is formed at a relatively low temperature (350
(.About.400 ° C.) to diffuse the electrode metal into the semiconductor. The diffusion section is alloyed,
As a result, the source electrode 31 and the drain electrode 33 are in ohmic connection with the n-type semiconductor regions 29S and 29D.

The above is the third embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention. It is apparent that the third embodiment has the same operation and effect as those obtained in the first and second embodiments.

(Embodiment 4) FIG. 5 shows a fourth embodiment of the present invention.
This will be described with reference to FIGS. In these drawings, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and the description will be simplified.

First, as the semi-insulating semiconductor substrate 21, Ga
An As substrate is prepared (FIG. 52).

Next, on this substrate 21, for example, MOC
The GaAs semi-insulating semiconductor layer 40 of 1000 Å is epitaxially grown by the VD method (FIG. 5).
3).

On this semiconductor layer 40, for example, MOCV
A 100 Å InGaP semi-insulating barrier layer 22 is epitaxially grown by the D method (FIG. 5).
4).

On this barrier layer 22, for example, MOCV
75 Å semi-insulating protective layer 23 by D method
Grow. It is important that the protective layer 23 be made of a semiconductor crystal containing no In. In this example, Ga
As is used (FIG. 55).

On the substrate 24 thus prepared, a patterned mask layer (photoresist) 25A is formed. Using this mask layer 25A as a mask, n-type impurity ions 26 are formed.
As A, for example, Si ions are implanted under the conditions of, for example, an acceleration energy of 30 keV and an area density of 2.5 × 10 ¹² / cm ² to form an ion implantation region 27A (FIG. 56).

After removing the mask layer 25A, the substrate 2
4, a patterned mask layer 25B is formed. Using this mask layer 25B as a mask, n-type impurity ions 26B
As an example, ions of Si are implanted under the conditions of, for example, an acceleration energy of 40 keV and an area density of 4 × 10 ¹² / cm ² to form an ion implantation region 27B (FIG. 5).
7).

After removing the mask layer 25B, gate electrodes 31A and 31B are formed on the ion-implanted regions 27A and 27B by using WSiN which is a heat-resistant metal to form a Schottky junction (FIG. 58).

Next, a patterned mask layer 25C is formed, and using this and the gate electrodes 31A and 31B as a mask, for example, Si ions as n-type impurity ions 26C, for example, at an acceleration energy of 80 keV and an area density of 5 ×
Ion implantation is performed under the condition of 10 ¹³ / cm ² to form an ion implantation region 27C. That is, the gate electrode 31
Ion implantation regions 27C on both sides of A and 31B in a self-aligned manner.
Is formed (FIG. 59).

After removing the mask layer 25C, 1000 Å of SiO _{2 is used} as the heat treatment protection film 28.
Deposit the film. Then, in order to activate the implanted ions, the substrate is heated at, for example, 950 ° C. for 1 second (FIG. 6).
0).

Thereafter, the gate electrode 3 of the heat treatment protection film 28 is formed.
Both sides of each of 1A and 31B are opened to form source electrodes 32A and 32B and drain electrodes 33A and 33B. These electrodes are formed of a protective layer 23, a barrier layer 22
And ohmic junction with the activated n-type ion implantation region 27C. Here, in the case where a conductive film such as WSiN is used as the heat treatment protection film 28, first, the conductive film is removed. Thereafter, an insulating film such as SiO ₂ is deposited, and this film is regarded as a heat treatment protection film 28, and the subsequent steps are performed (FIG. 61).

Finally, the gate electrode 3 of the heat treatment protection film 28 is formed.
A certain portion of 1A and 31B is also opened. Then, a wiring metal 50 is connected to each electrode to obtain a semiconductor device (FIG. 6).
2).

The ohmic junction between the source electrodes 32A and 32B and the drain electrodes 33A and 33B is
After depositing the electrode metal, a relatively low temperature (350-400
C.) to diffuse the electrode metal into the semiconductor. The diffusion section alloys, so that
Source electrodes 32A and 32B and drain electrodes 33A and 33
B comes into ohmic contact with the activated n-type ion implantation region 27C.

The above is the fourth embodiment of the present invention. In this embodiment, it is apparent that the same operation and effect as those of the above embodiments can be obtained.

This embodiment is different from the above embodiments in that a gate electrode made of a heat-resistant metal is used as a mask for forming an impurity ion implantation region below each ohmic electrode. Thus, in the present embodiment, the efficiency of the semiconductor manufacturing process is further improved. In this embodiment, as described above, after forming the gate electrode, heat treatment is performed to activate the impurity ion implanted region. Therefore, as compared with the conventional example, the gate electrode 3
More attention must be paid to the reaction between 1A, 31B and the protective layer 23, and furthermore to the InGaP barrier layer 22, which easily reacts with metal. However, as described above, the protective layer 23 is made of a semiconductor crystal containing no In and can be formed to a sufficient thickness, so that In of the barrier layer 22 reacts with W of the gate electrodes 31A and 31B to form a gate electrode. The problem of deteriorating the Schottky junction does not occur.

[0112] In the semiconductor circuit device obtained in the above embodiment, the threshold voltage V _T is the built-in potential V _bi of the Schottky electrode, charge q, the dielectric constant epsilon, the channel (27A,
27B), the carrier concentration is N, and the channels (27A, 27
The thickness of B) can be approximately expressed as follows as d.

[0113]

V _T = V _bi − (q / 2ε) * N * d ² Therefore, a desired threshold voltage can be realized by changing the ion implantation conditions to change the carrier concentration and thickness of 27A and 27B. Note that the threshold voltage means a gate voltage at which a current starts to flow to a channel by applying a voltage between a source and a drain or a current stops flowing.

As is well known, a field effect transistor is
A voltage is applied to the source and drain electrodes (both are ohmic electrodes) arranged on both sides of the gate electrode (Schottky electrode), and the resulting current is applied to the gate to change the width of the depletion layer under the gate. Control. In terms of element operation,
It is desirable that the source and the drain have no parasitic resistance.
Therefore, it is desirable that the injection layers in the source and drain regions have a high carrier concentration, are thick, and are as close as possible to the gate. (Contact with the gate region increases the leakage current of the gate). Therefore, the self-aligned ion implantation shown in FIG. 59 of this embodiment can be said to be an ideal method for reducing the parasitic resistance.

(Embodiment 5) Embodiment 5 is different from Embodiment 4 described above.
In this method, after the semi-insulating epitaxial layer 40 is formed on the semi-insulating semiconductor substrate 21, a mask layer is formed, whereby the ion-implanted layers 27A and 27B are formed first. After that, the remaining layers may be formed according to the third and fourth embodiments. That is, if the basic structure is shown, a patterned first mask layer is formed on a semi-insulating semiconductor substrate made of a first III-V compound semiconductor, and this is used as a mask to form an n-type impurity in the substrate. Implanting ions to form a first impurity ion implanted region, and removing the first mask layer;
Forming a semi-insulating barrier layer made of InGaP having a wider energy band gap than the first group III-V compound semiconductor; Forming a semi-insulating protective layer made of a semiconductor containing no, a step of forming a gate electrode made of a heat-resistant metal on the protective layer on the ion-implanted region, and a step of forming the first electrode on the protective layer. Forming a second mask layer having a pattern different from that of the mask layer, using the second mask layer and the gate electrode as a mask, implanting n-type impurity ions from the protective layer side; Forming an implanted region and, after removing the second mask layer, depositing a heat-treated protective film on the protective layer and heating the substrate to activate the impurity ion implanted region Forming an n-type semiconductor region;
Providing openings on both sides of the gate electrode of the heat treatment protective film, forming a source electrode and a drain electrode,
It is a method having.

In Examples 2 and 4 described above, it was shown that two transistors having different characteristics can be manufactured on one substrate. One of the features of the present invention is that a plurality of transistors can be easily formed over one substrate as described above. A specific circuit example of such a semiconductor circuit device will be described below.

An FET in which no current flows when the gate voltage is 0 V (Low Level) is an enhancement type FET
(E-FET) and an FET through which current flows are called a depletion-mode FET (D-FET). These two types of FETs
Are combined as shown in FIG. 63 to realize an inverter. That is, when a Low Level voltage (normally 0 V) is applied to In, no current flows through the E-FET, so the Out voltage becomes High Level (almost V _DD ), and conversely, a High Level voltage is applied to In. Is applied, a current flows through the E-FET, and the voltage of Out becomes Low Level (almost 0 V).

When a plurality of E-FET portions in FIG. 63 are connected in parallel, all the input voltages to the E-FET are Low Le.
A NOR circuit in which the output voltage becomes High Level only at the time of the level, and otherwise becomes the Low Level. FIG. 64 shows a three-input NOR circuit.

When an inverter and a NOR circuit are connected as shown in FIG. 65, an AND circuit can be realized.

That is, two FETs having different threshold voltages
, All logic circuits can be realized.

[0121]

As described above, according to the present invention, an impurity ion implanted region is formed in a substrate, a Schottky junction type gate electrode is formed on the impurity implanted region, and both sides of the gate electrode are formed. In a semiconductor circuit device having a source electrode and a drain electrode formed thereon, an InGaP barrier layer is formed between the substrate and the electrode;
The semiconductor device is characterized in that a protective layer made of a semiconductor not containing In as a component is formed between the aP barrier layer and the electrode, and the gate electrode is made of a heat-resistant metal. Therefore, according to the present invention, the operating layer is not affected by the material properties of the substrate, and the Schottky junction characteristics of the gate electrode are not deteriorated even when receiving heat during or after the manufacture of the device. . As described above, according to the present invention, the characteristics of the device can be significantly improved without complicating the manufacturing process.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a basic structure of a conventional semiconductor circuit.

FIG. 2 is a process diagram showing an example of a method for manufacturing a conventional semiconductor circuit device (two elements).

FIG. 3 is a process chart showing an example of a method for manufacturing a conventional semiconductor circuit device (two elements).

FIG. 4 is a process chart showing an example of a method for manufacturing a conventional semiconductor circuit device (two elements).

FIG. 5 is a process chart showing an example of a conventional method for manufacturing a semiconductor circuit device (two elements).

FIG. 6 is a process chart showing an example of a conventional method for manufacturing a semiconductor circuit device (two elements).

FIG. 7 is a process chart showing another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 8 is a process chart showing another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 9 is a process chart showing another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 10 is a process chart showing another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 11 is a process diagram showing another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 12 is a process chart showing still another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 13 is a process chart showing still another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 14 is a process chart showing still another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 15 is a process chart showing still another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 16 is a process chart showing still another example of a method for manufacturing a conventional semiconductor circuit device (one element).

FIG. 17 is a sectional view of the device in sequential steps for describing the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 18 is a sectional view of the device in sequential steps for explaining the method for manufacturing the semiconductor circuit device of the first example of the present invention.

FIG. 19 is a sectional view of the device in sequential steps for describing the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 20 is a sectional view of the device in sequential steps for explaining the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 21 is a sectional view of the device in sequential steps for describing the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 22 is a sectional view of the device in sequential steps for explaining the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 23 is a sectional view of the device in sequential steps for explaining the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 24 is a sectional view of the device in sequential steps for explaining the method for manufacturing the semiconductor circuit device of the first embodiment of the present invention.

FIG. 25 is a schematic cross-sectional view showing energy of a conduction band bottom of each part for explanation of a semiconductor circuit device manufactured by the method of manufacturing a semiconductor circuit device shown in the first embodiment of the present invention.

FIG. 26 is a graph showing the relationship between photoluminescence emission intensity and wavelength for a semiconductor substrate, for explaining the semiconductor circuit device shown in the first embodiment of the present invention.

FIG. 27 is a graph showing the relationship between the wavelength and the photoluminescence emission intensity of the semiconductor substrate to which relatively high heat has been applied, for explaining the semiconductor circuit device shown in the first embodiment of the present invention. is there.

FIG. 28 is a graph showing the relationship between the thickness of a semi-insulating barrier layer and the photoluminescence emission intensity of a semiconductor substrate for explaining the semiconductor circuit device shown in the first embodiment of the present invention.

FIG. 29 is an n-type semiconductor from the gate electrode side with respect to the thickness of the semi-insulating protective layer after applying relatively high heat, which is used for describing the semiconductor circuit device shown in the first embodiment of the present invention. 4 is a graph showing a height of a barrier against electrons by a Schottky junction viewed from a region side.

FIG. 30 is a cross-sectional view of the device in sequential steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention.

FIG. 31 is a sectional view of the device in sequential steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 32 is a cross-sectional view of the device in sequential steps for describing a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention.

FIG. 33 is a sectional view of the device in successive steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 34 is a sectional view of the device in successive steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention.

FIG. 35 is a sectional view of the device in successive steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 36 is a sectional view of the device in successive steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 37 is a sectional view of the device in sequential steps for describing a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention.

FIG. 38 is a cross-sectional view of the device in a sequential step for describing a second embodiment of the method of manufacturing a semiconductor circuit device according to the present invention.

FIG. 39 is a cross-sectional view of the device in a sequential step for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 40 is a sectional view of the device in successive steps for explaining a second embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 41 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method for manufacturing a semiconductor circuit device according to the present invention.

FIG. 42 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method for manufacturing a semiconductor circuit device according to the present invention.

FIG. 43 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 44 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of the method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 45 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method of manufacturing a semiconductor circuit device according to the present invention.

FIG. 46 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method of manufacturing a semiconductor circuit device according to the present invention.

FIG. 47 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 48 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 49 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 50 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method for manufacturing a semiconductor circuit device according to the present invention;

FIG. 51 is a schematic cross-sectional view in a sequential step for explaining a third embodiment of a method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 52 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 53 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 54 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 55 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 56 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of a method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 57 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of a method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 58 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 59 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 60 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of a method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 61 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 62 is a schematic cross-sectional view in a sequential step for explaining a fourth embodiment of the method of manufacturing a semiconductor circuit device according to the present invention;

FIG. 63 is a circuit diagram showing a specific example of a semiconductor circuit device obtained by the present invention.

FIG. 64 is a circuit diagram showing another specific example of the semiconductor circuit device obtained by the present invention.

FIG. 65 is a circuit conceptual diagram showing still another specific example of the semiconductor circuit device obtained by the present invention.

[Explanation of symbols]

Reference Signs List 21 semi-insulating semiconductor substrate main body 22 semi-insulating barrier layer 23 semi-insulating protective layer 24 semiconductor substrate 25, 25A, 25B, 25 'mask layer 26, 26A, 26B, 26' impurity ion 27, 27A, 27B, 27C, 27D, 27S n-type impurity ion implanted region 28 heat treatment protection layer 29, 29A, 29B n-type semiconductor region 29D n-type semiconductor region for drain electrode 29S n-type semiconductor region for source electrode 30, 30A, 30B Schottky junction 31, 31A, 31B Gate electrode 32, 32A, 32B Source electrode 33, 33A, 33B Drain electrode 34 Protective layer 35 Defect layer 36 Electron 40 Semi-insulating semiconductor layer 50 Wiring metal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuyoshi Asai 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Masami Tokumitsu 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan Nippon Telegraph and Telephone Co., Ltd. (72) Kazumi Nishimura 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Yasuhiro Yamane 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo (56) References JP-A-1-205471 (JP, A) JP-A-4-216636 (JP, A) JP-A-5-235053 (JP, A) IEICE Technical Report, Vo l. 93, No. 417 (issued on January 21, 1994) p. 9-16 (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/812 H01L 29/872 JICST file (JOIS)

Claims (5)

(57) [Claims] 1. A semi-insulating semiconductor substrate comprising a first III-V compound semiconductor; and InGaP having a wider energy band gap than the first III-V compound semiconductor. A semi-insulating barrier layer formed on a semiconductor substrate; and an n-type semiconductor formed on an upper portion of the semiconductor substrate in contact with the barrier layer, wherein n-type impurity ions are diffused using the semiconductor substrate as a base. A semi-insulating protective layer formed of a semiconductor having an energy band gap narrower than that of the InGaP and not containing In as a component, and formed on the barrier layer; A gate electrode made of a heat-resistant metal formed on the protection layer and making a Schottky junction with the protection layer; and a gate electrode on the protection layer on the n-type semiconductor region. Respectively formed on two positions sandwiching the gate electrode, the semiconductor circuit device, characterized in that it comprises the protective layer, and a source electrode and a drain electrode connected to the n-type semiconductor region and the ohmic through the barrier layer. 2. A semi-insulating barrier made of InGaP having a wider energy band gap than a first III-V compound semiconductor on a semi-insulating semiconductor substrate made of a first III-V compound semiconductor. A step of forming a layer; a step of forming a semi-insulating protective layer made of a semiconductor having no energy band gap as compared with the InGaP and containing no In as a component; and a mask patterned on the protective layer. A layer is formed, and using this as a mask, n-type impurity ions are implanted into the substrate, and n
Forming a type impurity ion implanted region; removing the mask layer; depositing a heat-treated protective film on the protective layer; heating the substrate to activate each of the impurity ion implanted regions; Forming an opening at a position on the n-type semiconductor region of the heat treatment protection film to form a gate electrode made of a heat-resistant metal; and forming an opening at both sides of the gate electrode of the heat treatment protection film. Forming a source electrode and a drain electrode, and a method of manufacturing a semiconductor circuit device. 3. A patterned first mask layer is formed on a semi-insulating semiconductor substrate made of a first III-V group compound semiconductor, and n-type impurity ions are implanted into the substrate using the first mask layer as a mask. Forming a first impurity ion-implanted region; and, after removing the first mask layer, forming a second pattern having a different pattern from the first mask layer on the semi-insulating semiconductor substrate.
Forming a second impurity ion-implanted region by implanting n-type impurity ions using the mask layer as a mask; and removing the second mask layer. Forming a semi-insulating barrier layer made of InGaP having a wider energy band gap than the first group III-V compound semiconductor; having a narrow energy band gap compared to the InGaP; Forming a semi-insulating protective layer made of a semiconductor containing no, a heat treatment protective film is deposited on the protective layer, and the substrate is heated to activate each of the impurity ion implanted regions to form an n-type semiconductor region. Forming an opening at a position on the n-type semiconductor region of the heat treatment protection film to form a gate electrode made of a heat-resistant metal; and forming the gate of the heat treatment protection film. An opening provided on both sides the position of the pole, a method of manufacturing a semiconductor circuit device characterized by having the steps of forming a source electrode and a drain electrode. 4. A semiconductor device comprising a semi-insulating semiconductor substrate made of a first III-V compound semiconductor and having a wider energy band gap than the first III-V compound semiconductor.
forming a semi-insulating barrier layer made of nGaP, forming a semi-insulating protective layer made of a semiconductor that does not contain In as a component and has a narrow energy band gap as compared with the InGaP; A first mask layer having a required pattern is formed on the layer, and n-side impurity ions are implanted from the protective layer side using the first mask layer as a mask to form a first impurity ion implanted region. Forming a gate electrode made of a heat-resistant metal on the protective layer on the ion-implanted region after removing the mask layer; and forming a pattern different from the first mask layer on the protective layer. Forming a second mask layer, and using the second mask layer and the gate electrode as masks, implanting n-type impurity ions from the protective layer side to form a second impurity ion implanted region. Forming, after removing the second mask layer, depositing a heat-treated protective film on the protective layer, heating the substrate to activate each of the impurity ion-implanted regions to form n-type semiconductor regions. And forming a source electrode and a drain electrode on both sides of the gate electrode in the heat treatment protective film, and forming a source electrode and a drain electrode. 5. A patterned first mask layer is formed on a semi-insulating semiconductor substrate made of a first III-V group compound semiconductor, and n-type impurity ions are implanted into the substrate using the first mask layer as a mask. Forming a first impurity ion-implanted region; and removing the first mask layer, forming an InGaP having a wider energy band gap on the substrate than the first III-V compound semiconductor. Forming a semi-insulating barrier layer made of a semiconductor, having a narrower energy band gap than InGaP, and forming a semi-insulating protective layer made of a semiconductor not containing In as a component; Forming a gate electrode made of a heat-resistant metal on the protective layer on the region; forming a second mask layer having a different pattern from the first mask layer on the protective layer; Using the second mask layer and the gate electrode as a mask, implanting n-type impurity ions from the protective layer side to form a second impurity ion implanted region; and removing the second mask layer Depositing a heat-treated protective film on the protective layer, heating the substrate to activate the impurity ion-implanted region to form an n-type semiconductor region, and a position on both sides of the gate electrode of the heat-treated protective film. Forming a source electrode and a drain electrode in the opening, and a method for manufacturing a semiconductor circuit device.