JP3198757B2 - Electrostatic induction thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a static induction thyristor.

[0002]

2. Description of the Related Art The prior art is disclosed in, for example,
There is one disclosed in JP-A-7-172765. FIG.
FIG. 2 is a sectional view showing the structure of the above conventional example. In FIG. 5, reference numeral 1 denotes a p + -type anode region, 2 denotes an n − -type base region, 3 denotes an n + -type cathode region, and 4 denotes a p + -type gate region. Reference numeral 5 denotes an insulating film, which is in contact with the base region 2, the cathode region 3, and the gate region 4, respectively. Reference numeral 6 denotes an anode electrode, and 7 denotes a cathode electrode, which are ohmically connected to the anode region 1 and the cathode region 3, respectively.
Reference numeral 8 denotes a gate electrode, which forms a junction gate with the gate region 4 and forms an insulating gate by being in contact with the insulating film 5.

In this example, the above-mentioned structure is used as a unit structure, and a large number of such unit structures are continuously formed in the left-right direction of the drawing. Here, a portion of the base region 2 sandwiched between the insulating films 5 is referred to as a “channel region”.

Next, the operation will be described. First, the cathode electrode 7 is grounded (to 0 V), and a positive potential is applied to the anode electrode 6. Even if the gate electrode 8 is grounded in this state, the gate electrode 8 is not turned off. That is, this element has a normally-on characteristic. Next, when a negative potential is applied to the gate electrode 8,
The pn junction between the gate region 4 and the base region 2 is reverse-biased, a depletion layer is formed in the channel region in front of the cathode region 3, and the current path is cut off to turn off.
To turn on this element, 0 V or a positive potential is applied to the gate electrode 8. Then, the depletion layer formed in the channel region in front of cathode region 3 disappears, and the interrupted current path opens. At this time, the insulating film 5 in the channel region
Electrons are accumulated in the vicinity, and the barrier against electrons on the front surface of the cathode region 3 is quickly lowered. Then, the electrons flow through the channel region and proceed to the front surface of the anode region 1 to eliminate the barrier against holes there. Then, holes are injected from the anode region 1 into the base region 2 and recombine with electrons. Turn on in this way. In this element, once the current starts flowing, the on state is maintained even if the positive potential applied to the gate electrode 8 is removed and the negative potential is applied. Gate electrode 8 to turn off from on state
A large negative potential. Then, holes in the base region 2 are swept out to the gate region 4 and recombine and disappear at the boundary between the gate region 4 and the gate electrode 8. Further, a depletion layer extends from the vicinity of the insulating film 5, the channel region is pinched off, the current path is cut off, and the device is turned off. As described above, this device has an advantage that the switching speed is high because the insulating gate in conjunction with the junction gate is added to the ordinary static induction thyristor. That is, at the time of turn-on, the turn-on is fast because an electron accumulation layer is formed at the insulated gate interface. Also, turn
At the time of off, a depletion layer is formed near the insulating film to easily enter a pinch-off state, so that turn-off is fast.

[0005]

However, the above-mentioned prior art has the following problems. First, the device has normally-on characteristics. In a normally-on element, in order to maintain the off state, a negative potential must be continuously applied to the gate with respect to the cathode. Therefore, when using the element, special measures and considerations are required for safety. Second, it is difficult to form a gate contact hole in the trench with this device structure. In the example shown in FIG. 5, an insulating gate is formed in a trench dug from the surface, and a gate electrode 8 is connected to the gate region 4 at the bottom of the trench. Such a gate contact hole must be formed at the bottom of the trench. In the case of this element, the groove depth is several μm in order to have a sufficient blocking gain.
is necessary. However, it is difficult to form a contact hole at the bottom of such irregularities by ordinary planar technology. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the related art, and has as its object to provide an electrostatic dielectric thyristor having a normally-off characteristic and a structure that is easy to manufacture.

[0006]

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention has a configuration as described in the claims. That is, in the first aspect of the present invention, the anode region, the base region, and the cathode region form layers in order from the bottom of the semiconductor substrate. Further, a groove is dug from the surface of the cathode region to the middle of the base region. Inside the groove, there is an insulating electrode which is insulated from the cathode region and the base region by an insulating film and kept at the same potential as the cathode region. The portion composed of the insulating electrode and the insulating film is called a fixed insulating electrode. This insulating electrode is made of a conductive material having a work function such that a depletion region is formed in an adjacent base region via an insulating film. further,
A gate region is provided in contact with the insulating film and the base region and not in contact with the cathode region. The portion of the base region sandwiched between the fixed insulating electrodes is called a channel region. The anode region, the base region, the cathode region, the insulating film, the insulating electrode, the fixed insulating electrode, the gate region and the channel region are, for example, an anode region 51, a base region 52, a cathode region 53 in the embodiment of FIG. Insulating film 56, insulating electrode 57, fixed insulating electrode 5
8, the gate region 54 and the channel region 62 respectively. In the invention according to claim 2,
According to the first aspect of the present invention, a region of the same conductivity type as the gate region and connected to the gate region is provided at the interface between the insulating film and the base region at the tip of the fixed insulating electrode, that is, in the vicinity of the bottom surface of the groove. It is provided. The above-mentioned region corresponds to, for example, ap + region 59 in the embodiment of FIG.

[0007]

In the off state, a potential barrier for majority carriers is formed in the channel region by the depletion layer around the fixed insulating electrode, and electrically disconnects the cathode region and the base region. In the ON state, by applying a predetermined potential to the gate region, minority carriers are supplied from the gate region to the insulating film interface of the fixed insulating electrode in contact with the gate region,
An inversion layer is formed, an electric field from the fixed insulating electrode to the channel region is shielded, and a neutral region is restored in the channel region, thereby electrically connecting the cathode region and the base region.
With such a configuration, when the gate voltage is set to 0 V, the depletion layer extends to the channel region and cuts off the current path, so that an electrostatic induction thyristor exhibiting normally-off characteristics can be realized. In addition, since the gate electrode is formed on a flat portion of the surface, a contact hole is easily formed, so that the structure is easy to manufacture. Claim 2
In the invention described in (1), a region connected to the gate region is provided below the fixed insulating electrode. With such a structure, the cathode region and the gate region are not necessarily sandwiched by the fixed insulating electrode. Therefore, there is no need to make them adjacent to each other, so that the design can be made flexible. Therefore, for example, a lattice-shaped planar arrangement as shown in FIG. 4 described later is also possible.

[0008]

The present invention will be described below in detail with reference to examples. 1 and 2 are diagrams showing a first embodiment of the present invention,
FIG. 1 is a sectional view of an electrostatic induction thyristor, and FIG. 2 is a plan view excluding a surface electrode. 1 and 2, reference numeral 51 denotes a p-type anode region; 52, an n-type base region;
Is an n + -type cathode region, and 54 is a p-type gate region. A groove is dug between the cathode region 53 and the gate region 54. The insulating film 56 is in contact with the side and bottom surfaces of the groove. Reference numeral 57 denotes ap + -type insulating electrode, and the insulating film 5
6, the inside of the groove is filled. This insulating film 56
And the insulating electrode 57 form a fixed insulating electrode 58.
The insulating electrode 57 is made of a conductive material having a work function that forms a depletion region in an adjacent base region via an insulating film. Reference numeral 61 denotes an anode electrode, 63 denotes a cathode electrode, and 64 denotes a gate electrode. Anode electrode 61
Is in ohmic connection with the anode region 51. Also,
Gate electrode 64 is in ohmic contact with gate region 54. The cathode electrode 63 is in ohmic connection with the cathode region 53 and is also in ohmic connection with the insulating electrode 57. That is, the potential of the insulating electrode 57 is fixed to the same value as that of the cathode electrode 63. The portion of the base region 52 sandwiched between the two fixed insulating electrodes 58 is called a channel region 62. Channel region 62
Is H (interval between two fixed insulating electrodes), and the length of the channel region 62, that is, the length in the depth direction from the bottom surface of the cathode region 53 to the bottom surface of the fixed insulating electrode 58 is L. In the present embodiment, the above-described structure is used as a unit structure, and a large number of such unit structures are continuously formed in the left-right direction of the drawing. FIG. 2 is a plan view (displayed excluding the electrodes 63 and 64 on the surface) when the unit structure is formed in a stripe shape, and shows two units.

Next, the operation of the embodiment will be described. First, the cathode electrode 63 is grounded (to 0 V), and the anode electrode 61
To a positive potential. In this state, when the potential of the gate electrode 64 is 0 V, the channel region 62 is
A depletion layer is formed due to the build-in electric field from the transistor and the transistor is in an off state. That is, this element has normally-off characteristics. In a normal electrostatic induction thyristor, when the anode electric field is strengthened, the potential barrier of the channel is lowered so that a current can flow. In this embodiment, in order to prevent this, the channel length L shown in FIG. It is formed to be about three times the channel thickness H. For example, the channel thickness H is 2 μm, and the channel length L is about 6 μm. In addition, the fixed insulating electrode 5
The width of the buried groove 8 is also about 2 μm. With such a design, it has been confirmed by numerical calculation that the channel does not open even if the anode electric field increases. Such a fine structure can be easily formed by, for example, a technique for manufacturing a trench capacitor used in a memory. Further, the p + -type insulating electrode 57 can also be realized by depositing polysilicon having a thickness of about 1 μm under blanket conditions by a CVD method and flattening it. By making the cell structure finer, the current density can be improved.

Next, to turn on the device, a positive potential is applied to the gate electrode 64. Then, holes are supplied to the interface of the insulating film 56 in contact with the p-type gate region 54 to form an inversion layer, and the electric field from the fixed insulating electrode 58 forming the depletion layer in the channel region 62 is shielded. As a result, the depletion layer of channel region 62 recedes, and the potential for electrons in front of cathode region 53 decreases,
The electrons flow to the base region 52. The electrons that have flowed reach the front surface of the anode region 51 and increase the potential there,
Since the junction formed between the base region 52 and the anode region 51 is forward-biased, holes are also injected from the anode region 51, the base region 52 and the channel region 62 enter a high injection level state, and the element is turned on. Once turned on, the main current continues to flow even if the positive potential applied to the gate electrode 64 is released.

Next, to turn off the device, a negative potential is applied to the gate electrode 64. Then, the holes filling channel region 62 are directly transferred to gate region 5.
4 or through the inversion layer at the interface of the insulating film 56 to flow into the gate region 54, the potential barrier against electrons is formed again in the channel region 62, and the electron current from the cathode region 53 stops. Then, the junction on the front surface of the anode region 51 is again turned off, and the base region 52
Excess minority carriers in the element flow off to the gate region 54, and the device is turned off. Note that this element is similar to the conventional element in that turn-on and turn-off are fast.

FIGS. 3 and 4 show a second embodiment of the present invention. FIG. 3 is a sectional view of an electrostatic induction thyristor.
FIG. 4 shows a plan view excluding the surface electrode. FIG. 4 shows a case where the unit elements are arranged in a lattice. This embodiment is different from the embodiment of FIG. 1 in that ap + region 59 is provided below a fixed insulating electrode 58. The p + region 59 is connected to the gate electrode 54. With such a structure, the cathode region 53 and the gate region 54 are not necessarily connected to the fixed insulating electrode 58.
This eliminates the necessity of adjoining each other so that the design can be made flexible. Therefore, a grid-like arrangement as shown in FIG. 4 is also possible. Other than that, the operation of the element is the same as that of the embodiment shown in FIGS. In the first and second embodiments, the same operation is performed even when the p-type and the n-type of the semiconductor constituting each region are reversed.

[0013]

As described above, according to the present invention, the following effects can be obtained. (1) Since the normally-off characteristics do not require special measures and considerations for safety during use as in normally-on devices, the range of application is widened and peripheral circuits are simplified. (2) In the conventional technique, a contact hole with the p-type region must be formed at the bottom of the groove in order to obtain a blocking gain, which is difficult with a normal planar manufacturing technique. However, according to the present invention, since the current block is realized by the fixed insulating electrodes and the contact with the gate region can be made on the surface, the manufacturing process is simplified. (3) The cell size can be reduced for the above reasons, so that the current density increases and the degree of integration can be increased. (4) Turn-on is fast.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a plan view of the first embodiment of the present invention.

FIG. 3 is a sectional view of a second embodiment of the present invention.

FIG. 4 is a plan view of a second embodiment of the present invention.

FIG. 5 is a sectional view showing an example of a conventional electrostatic induction thyristor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Anode region 5 ... Insulating film 2 ... Base region 6 ... Anode electrode 3 ... Cathode region 7 ... Cathode electrode 4 ... Gate region 8 ... Gate electrode 51 ... Anode region 58 ... Fixed insulating electrode 52 ... Base region 59 ... P + region 53: cathode region 61: anode electrode 54: gate region 62: channel region 56: insulating film 63: cathode electrode 57: insulating electrode 64: gate electrode

Continuation of the front page (56) References JP-A-5-75140 (JP, A) JP-A-7-78964 (JP, A) JP-A-4-127474 (JP, A) JP-A-57-172765 (JP) , A) JP-A-3-289141 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/74

Claims (2)

(57) [Claims] A first conductivity type semiconductor substrate serving as an anode region having a second conductivity type base region on one main surface thereof; and a higher impurity concentration than the base region on one main surface of the base region. A plurality of grooves dug from the main surface of the cathode region toward the base region with the cathode region interposed therebetween, and an insulating film is formed inside the groove. An insulating electrode insulated from the cathode region and the base region, and having an insulating electrode kept at the same potential as the cathode region, wherein the insulating electrode forms a fixed insulating electrode together with the insulating film, and A portion of the base region adjacent to the cathode region, the portion being sandwiched by the fixed insulating electrode. Cha It has Le region, further contact with the insulating film and the base region of the periphery of the fixed insulating electrode, not in contact with the cathode region,
An electrostatic induction thyristor having a gate region of a first conductivity type. 2. The static induction thyristor according to claim 1, wherein the same conductivity type as that of the gate region is provided at an interface between the insulating film and the base region at a tip portion of the fixed insulating electrode, that is, a portion near a bottom surface of the groove. And a region connected to the gate region is provided.