JPH03203335A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to reduce irregularity in the electrical characteristics of a device within the surface of the device by a method wherein the channel width and the gate width are decided on a mask at the time of a design, a gate length is decided by buried diffusion and the effect of the thickness of an epitaxial growth is made negligible. CONSTITUTION:An n-type epitaxial layer 2 is formed on an n<+> semiconductor substrate 1 and p-type diffused regions 3, which are used as buried gate regions and respectively have inner side surfaces opposing to each other at an interval to match to a channel width, are formed on the layer 2. Moreover, an n-type epitaxial layer 2a, in which the regions 3 are buried, is grown. A p-type upper surface gate regions 3a for connecting the layer 3 to the upper surface are formed through selective diffusion of P-type impurities based on a planer technique. n<+> and p<+> ohmic layers 4 and 5 for making surface electrodes are formed, an insulating film 6 is formed, openings are formed in the film 6 to form a source electrode 4a to connect to the layer 4 and a gate electrode 5a to connect with the layer 5 and the substrate 1 is used as a drain. Accordingly, a gate length is decided by buried diffusion and the effect of the thickness of an epitaxial growth can be neglected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a junction field effect transistor (hereinafter referred to as J-FET).
The present invention relates to a semiconductor device having a J-FET, and particularly to a semiconductor device having a J-FET characterized in that white variation in electrical characteristics does not depend on in-plane variation in epitaxial growth.

[Conventional technology]

Conventionally, for example, this type of N-channel J-FET has an internal structure as shown in the cross-sectional view of FIG.
The distance between the upper and lower gate regions 11 and 14 of the N-type epitaxial layer (channel layer) 12 interposed between the P-type lower gate region (substrate) 11 and the P-type upper gate region 14,
That is, it was controlled by the channel width d.

According to such a method of controlling electrical characteristics, variations in the epitaxial layer 12 within the plane of the wafer appear as variations in the electrical properties of the wafer of the product.

In FIG. 4, 15 is an N'' source region, and 16 is an N'' source region.
is the N1 drain region.

[Problem to be solved by the invention]

In the semiconductor device having the above-described conventional J-FET, it is difficult to avoid variations of approximately ±lθ% in the thickness and resistivity of the channel region formed by epitaxial growth. The variation in thickness results in variation in channel width, and the variation in resistivity is caused by variation in impurity concentration, and this variation causes the disadvantage that electrical characteristics become unstable. This tendency becomes stronger as the wafer becomes larger, so J-FE
This makes it difficult to increase the diameter of the T.

Next, we will consider the influence of variations in the channel region on the electrical characteristics using theoretical formulas.

ND is the donor impurity concentration, d is the channel length, W is the gate width, L is the gate length, and in the conventional J-FET,
The gate width W and gate length as shown in the schematic cross-sectional view of FIG. 5(a) and the gate pattern diagram of FIG. 5(b) are parameters determined on the mask at the time of design, but the electrical characteristics This depends on the thickness and resistivity of the epitaxial layer, and the channel width d and donor impurity concentration ND greatly depend on the epitaxial characteristics.

[Means to solve the problem]

In the present invention, the channel width d and gate width W are determined on the mask at the time of design, and the gate length is determined by buried diffusion, so that these are not influenced by epitaxial characteristics. ing. for that,
In the present invention, the schematic cross-sectional view of FIG. 3(a) and the schematic cross-sectional view of FIG. 3(b)
As shown in the buried gate pattern diagram in FIG. A laterally extending gate region GA having a gate length is buried, and a source and a drain are formed in upper and lower epitaxial layers EA with this gate region GA in between.

〔Example〕

Next, the present invention will be explained by examples.

FIG. 1 is a sectional view of an embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate of one conductivity type, e.g. N-type epitaxial layer formed by burying the buried region 3, 3a
is a P-type upper gate region for connecting the P-type buried region 3 to the surface, 4 is an N+ neo-oc region for making contact with the source electrode 4a, and 5 is for making contact with the gate electrode 5a. P''' ohmic region.

Thus, a J-FET is formed in which the current between the source electrode 4a and the drain electrode provided on the substrate 1 is controlled by the control voltage applied to the gate electrode 5a.

FIGS. 2(a) to (e) are cross-sectional views in the order of steps for explaining the manufacturing method for manufacturing the J-FET shown in FIG. 1. First, in FIG. 2(a), An N-type epitaxial layer 2 is formed on an N+ semiconductor substrate 1, and as shown in FIG. A P-type diffusion region 3 having an inner side surface is formed.Next, as shown in FIG. As shown in (d), a P-type top gate region 3a for connecting the P-type buried layer 3 to the top surface is formed by selectively diffusing P-type impurities using the Brainer technique.Next, as shown in FIG. Then, an N+ ohmic layer 4 and a P+ ohmic layer 5 are formed for forming a surface electrode, and an insulating film 6 is formed.A window is formed in the insulating film 6 to form a source electrode 4a connected to the N" ohmic layer 4, and a P+ ohmic layer 4. ``A J-FET is completed in which the gate electrode 5a connected to the ohmic layer 5 is formed and the substrate 1 is used as the drain.

In addition, although the above example describes an N-channel J-FET in which one conductivity type is N type and the opposite conductivity type is P type, it is also possible to use a P channel with a similar configuration in which one conductivity type is P type and the opposite conductivity type is N type. It goes without saying that the present invention is similarly applicable to J-FETs.

〔Effect of the invention〕

As explained above, the present invention makes it possible to ignore the influence of epitaxial growth thickness, thereby reducing in-plane variations in electrical characteristics by improving diffusion accuracy. It also has the effect of increasing the number of people.

P-type buried gate region, 4...N+ neo-oc region, 4a...source electrode, 5...P+
Ohmic region, 5a...gate electrode, 6...
...Insulating film, d...Channel width, L...
...Gate length, W...Gate width.

Claims (1)

[Claims] An epitaxial layer of one conductivity type in which gate regions of opposite conductivity types extending laterally and having a thickness corresponding to a predetermined gate length and opposing inner surfaces separated by a predetermined channel width are pressed into a substrate of one conductivity type. forming an upper gate region of an opposite conductivity type extending from the upper surface of the epitaxial layer to the gate region of the opposite conductivity type; 1. A semiconductor device comprising a junction field effect transistor having a gate electrode extending from an upper gate region of an opposite conductivity type and a drain electrode extending from the substrate of one conductivity type.