JPS60257577A - Junction type field-effect transistor - Google Patents

Abstract

PURPOSE:To manufacture a JFET, which operates at high speed and high frequency and is fitted to an integration to a high degree, by forming a reverse conduction type cylindrical region to a p type or an n type operating layer and shaping a gate electrode forming an ohmic contact. CONSTITUTION:An insulating film 7 is formed in a region held by a source electrode 2 and a drain electrode 3 shaping ohmic contacts on the surface of a semiconductor substrate 6, and one or a plurality of bored holes are shaped. A reverse conduction type cylindrical region is formed to a p type or an n type operating layer 14 in the lower section of the bored holes, and a gate electrode 11 shaping an ohmic contact is formed to the upper sections of the region and the bored holes. Currents flowing through the source electrode 2 from the drain electrode 3 are modulated by the expansion and contraction of depletion layers formed on junction surfaces among p type gate regions 15 and the n type operating layer 14 by voltage applied to the gate electrode 11, and amplification action and switching action are realized. Accordingly, mutual conductance increases and the degree of integration can be improved even in the same gate width, and phase differences among gates are difficult to be generated, thus displaying an effect of which the lowering of the gains of extra-high frequency is inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a junction field effect transistor having a pn junction.

[Prior art]

Conventional devices include those shown in FIGS. 1(a) to 1(c).

FIG. 1(a) is a plan view of a conventional gallium arsenide junction field effect transistor (hereinafter referred to as GaA8JFET), FIG. 1(b) is a cross-sectional view taken along line AA' in FIG. 1(a),
FIG. 1(C) is a sectional view taken along the line B-B' of FIG. 1(a).

In FIGS. 1(a) to (c), 1 is a gate electrode, 2 is a source electrode, 3 is a tongue-in electrode, and 4 is the source electrode 2.
and an n-type active layer that is in ohmic contact with the tunnel electrode 3; 5 is a p-type gate region that is in ohmic contact with the gate electrode 1 that forms a pn junction with the n-type active layer 4; It is a semiconductor substrate.

Next, the operation will be explained.

In the conventional GaAa JFET, the depletion layer is expanded and contracted at the junction between the p-type gate region 5 and the n-type active layer 4 due to the voltage applied to the gate electrode 1 (mainly expansion and contraction in the direction perpendicular to the surface of the semiconductor substrate 6). ) modulates the current flowing from the tunnel electrode 3 to the source electrode 2, thereby realizing an amplification effect and a switching effect.

As described above, in the conventional GaAs JFET, the p-type gate region 5 is formed only on one surface of the semiconductor substrate 6, so an increase in the gate width directly leads to an increase in the device area. For this reason, for example, when a GaAs JFET is used as a basic element of a memory IC, if the gate width is increased in order to increase the mutual fundance GIIl, the element area increases and the degree of integration begins to decrease.

In addition, in order to use it as a high-output FET, if the gate width is left unchanged and the gate region 5 is made long, a phase difference will occur in the input signal between the input end of the thin gate region 50 and the other end, especially in the case of ultra-high frequencies. However, the phase difference becomes noticeable, leading to a decrease in power amplification gain, and has five drawbacks.

[Summary of the invention]

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and provides a JFET that operates at high speed and high frequency and is suitable for high integration.

An embodiment of the present invention will be described below with reference to FIG.

[Embodiments of the invention]

Figure 2(a) is a plan view of the GaAs JFET of the present invention, Figure 2(b) is a cross-sectional view taken along line A-A' in Figure 2(a), and Figure 2(C) is a plan view of the GaAs JFET of the present invention. B −B in &)
A cross-sectional view 7 taken along the line 7 is shown.

In FIGS. 2(a) to (c), 11 is a gate electrode;
4 is an n-type active layer that is in ohmic contact with the source electrode 2 and the tunnel electrode 3; 15 is a p-type active layer that is in ohmic contact with the gate electrode 11 and forms a pn junction with the n-type active layer 14; type gate region, and p
One or more mold gate regions 15 are formed in a cylindrical shape in a region sandwiched between the source electrode 2 and the tunnel electrode 3 .

T is an insulating film for electrically insulating the n-type active layer 14 and the gate electrode 11;
There is an opening at the top of 5. Note that 2.3.6 is the same as in FIG. 1, so the explanation will be omitted.

Next, the operation will be explained.

In the GaAs JFET of the present invention, the p-type gate region 15 and offi are separated by the voltage applied to the gate electrode 11.
The expansion and contraction of the depletion layer (mainly expansion and contraction in the horizontal direction with respect to the surface of the semiconductor substrate 6) that occurs at the junction surface with the active layer 14 modulates the current flowing from the tunnel electrode 3 to the source electrode 2, resulting in amplification and switching effects. has been realized.

In the above embodiment, the p-type gate region 15 has a cylindrical shape, but it may also have a rectangular or square columnar shape. Further, in the above embodiment, the active layer 14 is n-type, and the gate region 15 is
It doesn't matter if the person is p-type or vice versa. Furthermore, the semiconductor material may be GaAs, silicon, or other group 1-2 compound semiconductor.

〔Effect of the invention〕

As explained above, the junction type transistor of the present invention is formed by depositing a source electrode and a tone-in electrode to form an ohmic contact on the surface of a semiconductor substrate having a top surface Kp type or n type active layer, thereby forming an ohmink contact. An insulating film is formed in the region sandwiched between the source electrode and the drain electrode, and one or more openings are provided in the region where the insulating film is formed. The p-type or n-type operating layer has a cylindrical region of a conductivity type opposite to that of the operation layer, and further forms ohmic contact with the cylindrical region of a reverse conductivity type at the upper part of the opening. Since the structure includes a gate electrode, the mutual conductance can be increased even with the same gate width, and the degree of integration can be increased by 7. Furthermore, since phase differences between gates are less likely to occur, there is an effect of suppressing a decrease in gain at ultra-high frequencies.

[Brief explanation of the drawing]

Figure 1 (, &) to (e) are conventional GaAa JFETs.
FIGS. 2(a) to 2(e) are cross-sectional views showing the internal structure of a G1As JFET according to an embodiment of the present invention. In the figure, 2 is a source electrode, 3 is a do-V in electrode, 4 is an n-type active layer, 5 is a p-type gate region, 6 is a semiconductor substrate, T is an insulating film, 11 is a gate electrode, and 14 is an n-type operating layer of, 15
is a p-type gate region. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Kouri Oiwa (2 others), 1 B' (b)

Claims (1)

[Claims] On the surface of a semiconductor substrate having a p-type or n-type active layer on the upper surface, a source electrode and a tongue-in electrode are deposited to form an ohmic contact, and are sandwiched between the source electrode and the drain electrode forming an ohmic contact. An insulating film is formed in the area where the insulating film is formed, and one or more openings are provided in the area K where the insulating film is formed.
Alternatively, a cylindrical region of a conductivity type opposite to that of the n-type active layer is provided in the n-type active layer, and a gate electrode is further provided to form an ohmic contact with the cylindrical region of the opposite conductivity type and the upper part of the opening. A junction field effect transistor characterized by: