JPS58148463A - Mes type field effect transistor - Google Patents

Abstract

PURPOSE:To implement amplifying and switching actions, by modulating the current flowing from a drain electrode to a source electrode based on the expansion and contraction of a depletion layer formed in an operating layer beneath a gate electrode in the vertical (longitudinal) direction with respect to mainly a wafer surface. CONSTITUTION:An N type crystal layer is formed on a semiinsulating GaAs substrate 7. An insulating film 9 is made of a silicon oxide film or silicon nitride film and deposited on the surface of said crystal layer. One or a plurality of circular openings 8 are formed by machining a part of the insulating film 9, which is held between the source electrode 2 and the drain electrode 3. A numeral 11 shows cylindrical holes which are provided by piercing a GaAs N type crystal layer 10 beneath the openings 8 down to the semiinsulating substrate with the insulating film 9 as a mask. A part of the gate electrode metal 12, which is deposited on the insulating film, forms a Schottky barrier junction 13 on the surface of the GaAs crystal layer in the cylindrical hole 11 through each opening 8. Since the Schottky barrier junction is formed in the vertical direction on the surface of the GaAs wafer, a gate width wg can be increased without increasing the area of the element.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MES field effect transistor using a Schottky barrier junction.

A description will be given below using a gallium arsenide MES field effect transistor (hereinafter abbreviated as GaAsFET) as an example.

Figure 1(a) is a pattern diagram showing the electrode arrangement of a conventional GaAsFET, with a gate electrode (1) made of aluminum or a metal layer forming a Schottky barrier junction with GaAs such as titanium, platinum, or gold sandwiched therebetween. A source electrode (2) and a drain electrode (3) that form ohmic contact with GaAs such as gold, germanium, and nickel are arranged at both ends thereof. The region surrounded by the broken line is an active layer (4), and the regions (5) other than the active region (4) are subjected to ion implantation or mesa etching to isolate the elements. Further, (6) indicates a gate electrode pad. Figure 1(b) shows the A in Figure 1(,a).
This figure shows a cross-sectional view of a conventional GaAsFET when cut at -A'. The gate electrode (1) is formed either directly on the surface of the active layer (4) with a concentration ND in the range of 10"-10", or after digging GaAs to a predetermined thickness of the active layer to form a so-called recess structure. It has a structure in which it is adhered to the surface.

In the QaAs FET of this structure, the gate electrode (1)
The current flowing from the drain electrode (3) to the source electrode (2) is modulated by the expansion and contraction of the depletion layer formed in the lower operating layer (4) mainly in the direction perpendicular to the wafer surface (vertical direction). , realizes amplification and switching functions.

As described above, in the conventional GaAsFET, the gate electrode (1) is formed only on one surface of the GaAs wafer, so an increase in the gate electrode (1i) directly leads to an increase in the device area. For that, for example, note IJI
When a GaAsFET is used as a basic element for a high-output FET, even if the gate width wg is increased in order to increase the mutual conductance gm, the degree of integration will immediately decrease. If the positive wg is made longer, the gate voltage will be thinner! There is a phase difference in the input signal between the input end and the tip of M (1), and especially when the frequency reaches ultra-high frequencies above the X band, the phase difference becomes significant and causes a reduction in power amplification gain. It had drawbacks.

The present invention was made to eliminate the above-mentioned drawbacks of the conventional transistors, and aims to provide a MES field effect transistor that operates at high speed and high frequency and is suitable for high integration.

An embodiment of the present invention will be described below.

Figure 2 (al is a pattern diagram showing the electrode arrangement of the GaAsFET according to the present invention, and Figure 2 (b) is a cross-sectional view taken along line B-B in Figure 2 (a). Figure 2 (a) and In (b), (8) is a semi-insulating GaAs substrate (7)
An insulating film (9) made of silicon oxide film or silicon nitride film is deposited on the surface of the n-type crystal layer produced above
U is a circular hole consisting of one or more holes formed by processing the insulating film (9) in the region narrowed by the source electrode (2) and drain electrode (3) of the insulating film ( 9) as a mask, remove the GaAs n below the opening (8).
This is a cylindrical hole drilled through the mold crystal layer up to the semi-insulating substrate. (2) is a gate electrode metal deposited on the insulating film by vapor deposition or plating, and Ga on the surface of the cylindrical hole (b) is passed through the opening (8).
A Schottky barrier junction is formed on the surface of the As crystal layer. In this case, since the Schottky barrier junction (to) has a cylindrical shape, in addition to the impurity concentration Nd of the active layer, the thickness A of the n-type crystal layer Q is as shown in FIG. 2(b).
By determining the diameter of the window (g) and the spacing between adjacent openings (8) to predetermined values, the drain/drain flowing from the drain electrode (3) to the source electrode (2) can be The current can be modulated by utilizing the expansion and contraction of the depletion layer extending laterally from the Schottky barrier junction.

In a GaAs FBT with such a structure, the Schottky barrier junction is formed perpendicularly to the surface of the GaAs wafer, so the depth of the hole (b), that is, the n-type crystal layer α
By increasing the thickness A of O, the gate width wg can be increased without increasing the device area, and as a result, compared to, for example, a memo IJ IC using a conventional structure FET with the same gate width. This has the advantage that the degree of integration can be significantly improved. At the same time, as shown in FIG. 2(b), since the length L of the gate electrode metal υ can be shortened, the phase difference of the input signal between the input end Q41 and the tip +161 of the Schottky barrier junction (to) It also has the advantage of being able to reduce the power amplification gain due to the phase difference in an ultra-high frequency band of X or higher.

In the above embodiment, the case where the shape of the opening (8) is circular has been described, but the same effect can be obtained even if the opening (8) is made rectangular or square by providing appropriate dimensions and arrangement. Further, in the above embodiment, GaA is used as the semiconductor material.
Although the present invention has been described for the nine cases using S, it can also be applied to field effect transistors using silicon or other F-M compound semiconductors, such as InP.

As described above, according to the present invention, a Schottky barrier electrode is formed in a region sandwiched between a source electrode and a drain electrode of an insulating film formed on a semiconductor surface at a predetermined interval and shape in the gate electrode arrangement direction. %G through one or more apertures
Since it is formed on the surface of a cylindrical hole drilled through the aAs crystal layer to the semi-insulating layer, it is possible to increase the degree of integration of the device and has the effect of suppressing the decrease in gain in the ultra-high frequency band above the X band. .

[Brief explanation of drawings]

Fig. 1(a) is a pattern diagram showing the electrode arrangement of a conventional GaAsFET, Fig. 1(a) is a cross-sectional view taken along line A-A in Fig. 1(a), and Fig. 2(a) is a pattern diagram showing the electrode arrangement of a conventional GaAsFET. The pattern diagram of the GaAsFET according to the example, FIG. 2(b) is as shown in FIG.
It is a sectional view taken along EH of a). (1)...Gate electrode, (25...Source electrode, (3
)...Dray/electrode, (4)...Operating area, (8)
...opening hole, (9)...insulating film, 00...n-type crystal layer, α di...hole, @...gate electrode metal, αJ...
・Schottky barrier bonding. Agent Patent Attorney Makoto Kuzuno - Figure 1 (4) Figure 2 (Shi) Procedural amendment (spontaneous) Mr. J., Commissioner of the Japan Patent Office, Indication of the case Patent application No. 57-81! GOg No. 2, title of the invention MES field effect transistor 3, relationship with the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Katayama Jinhachibe 4, Agent address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, Subject of amendment (1) Scope of claims in the specification (2) Detailed description of the invention in the specification 6. Contents of amendment (1) The scope of claims is corrected as shown in the attached appendix. (2) "Titanium/gold" in the second line of page 2 of the specification is corrected to "titanium-gold". (3) Same, page 2, line 8, "gold/gold" is corrected to "gold-gold". (4) "Gold-germanium-nickel" in the 5th line of page 2 is corrected to "gold-germanium-nickel." (5) "Cylindrical" in page 4, page 155 is corrected to "cylindrical". (6) Same, on page 4, first digit, "cylindrical" is corrected to "cylindrical". (7) Same, page 6, first line, "cylindrical shape" is corrected to "cylindrical shape". 7. Document showing the scope of claims after the amendment to the list of attached documents The above claims include first and second electrodes forming ohmic contact with the semiconductor and an insulating film on the whole surface of the semiconductor. It is worn,
- or a plurality of openings are formed at a predetermined interval in a region of the insulating film where the first and second ohmic electrodes are narrowed.
A structure 1 which is provided with a cylindrical hole, which is provided with the same size and is formed by penetrating the semiconductor crystal layer below the opening with a semi-insulating crystal rt, is provided with the semiconductor and the The eighth part forms a Schottky barrier junction at the surface of the cylindrical hole.
An MES field effect transistor characterized by comprising an electrode.

Claims (1)

[Claims] First and second electrodes forming ohmic contact with the semiconductor, and an insulating film are deposited on the whole surface of the semiconductor,
- or a plurality of openings are provided at predetermined intervals and dimensions in a region narrowed by the 1st and 20th ohmic electrodes of the insulating film, and the semiconductor below the openings. In a structure comprising a cylindrical hole drilled through the crystal layer to the semi-insulating crystal layer, a third electrode forming a Schottky barrier junction with the semiconductor and a surface portion of the cylindrical hole. A MES field effect transistor characterized by comprising: