JPS63209179A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To augment a source-drain current while the breakdown strength in a conventional structure is maintained and to contrive to improve an output by forming gate electrodes in opposition to each other on the upper and lower surfaces of an active layer. CONSTITUTION:An N-type active layer 2 consisting of GaAs is formed on a semi-insulative GaAs substrate 6 and a first gate electrode 1A, which has a gate length of 0.3 mum and consists of WSi, is formed on the surface of this layer 2. A second gate electrode 1B, which is connected electrically to the electrode 1A outside of the active layer region, is formed in opposition to this electrode 1A on the bottom surface part of the layer 2. When the thickness of the active layer in a conventional field-effect transistor is assumed to be (t), the thickness of the active layer in this case comes to 2t. Thereby, the conventional gate-drain breakdown strength is maintained and also, the source- drain current can be augmented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor, and more particularly to the structure of a field effect transistor using a compound semiconductor.

[Conventional technology]

Conventionally, a field effect transistor using a compound semiconductor has a gate electrode 1 on an active layer 2 made of N-type GaAs formed on a semi-insulating GaAs substrate 6, as shown in FIG.
It has a structure in which source and drain electrodes 3 and 4 are formed.

[Problem that the invention seeks to solve]

In the above-mentioned conventional field effect transistor, the drain-source current DS + voltage DS becomes the curve shown in Fig. 5 when the gate-source voltage VGS is used as a parameter, and the output that can be extracted is the I shown in the figure. 05
It is approximately proportional to the product of maX and VB. ID here! i
maX and VB are the maximum current that can flow between the drain and source and the breakdown voltage between the gate and drain, respectively, and if the impurity concentration and thickness of the active layer 2 are N and t, respectively, I DS
maX and VB are approximately proportional to Nt and 1/Nt, respectively. Therefore, for example, if the thickness of the active layer is doubled and Ios□X is
There was a problem in that even if the voltage was doubled, the withstand voltage would drop and no improvement in output could be expected.

An object of the present invention is to provide a field effect transistor that can maintain the conventional gate-drain breakdown voltage and increase the source-train current.

[Means for solving problems]

The field effect transistor of the present invention includes an active layer formed on a semi-insulating substrate, and a first active layer formed on the surface of this active layer.
and a second gate electrode that is opposite to the first gate electrode and formed at the bottom of the active layer, and that is electrically connected to the first gate electrode outside the active layer region. be done.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

In FIG. 1, an N-type G
An active layer 2 made of aAs is formed, and a first gate electrode IA made of WSi having a gate length of 0.3 μm is formed on the surface of this active layer 2. A second gate electrode IB is formed on the bottom surface of the active layer 2, facing the first gate electrode IA, and electrically connected to the first gate electrode IA outside the active layer region.

In FIG. 1, 5 is an N+ type GaAs layer, 3 is a source electrode, and 4 is a drain electrode.

The active layer 2 can be easily formed by forming a second gate electrode IB made of WSi on the semi-insulating gap substrate 6, and then using a crystal growth method such as MOCVD.

The source electrode 3 and the drain electrode 4 are formed on an N+ type GaAs layer 5 formed by ion implantation, and are, for example, A
It is composed of uGe-Ni-Ti-Pt-Au.

FIG. 2 is a diagram showing the extension of the depletion layer and the lines of electric force in the vicinity of the gate in a breakdown state in order to explain the operation of the first embodiment, especially the withstand voltage.

In the case of a conventional field effect transistor, the lower half region of the center line 10 indicated by the dashed line in FIG.
It is a s-substrate. Therefore, the thickness of the active layer is t, the maximum source/drain current corresponding to this thickness is 1°S□, and the withstand voltage in this case is vBo.

In the first implementation shown in FIG. 2, the active layer thickness is 2t.
The maximum current is twice that of IDS□X, but the reason why the breakdown voltage is maintained at VB□ at this time will be explained below.

As shown in FIG. 2, it is clear that in the structure of the first embodiment, the depletion layer or the lines of electric force are approximately symmetrical with respect to the center line.

Now, when the depletion layer extends by 2 toward the drain side, and assuming that the concentration of the active layer is N, approximately N·2t−f lines of electric force terminate at the gate. However, from the above, the number of electric lines of force terminating at each upper and lower gate is -(N・2t-/)=
N, t, ff.

The electric field E in each of the upper and lower gates depends on the gate length, so when E reaches the breakdown electric field E□X, the active layer thickness is t even in the case of this structure where the active layer thickness is 2t. The same applies to the conventional structure.

Therefore, the withstand voltage in this structure is also the withstand voltage VB□ of the conventional case, and the active layer thickness is doubled. 5maX 2
Even if the voltage is doubled, the withstand voltage will remain the same as before. It is clear from the above explanation that the same thing can be said not only when the thickness of the active layer is increased but also when the concentration N is increased.

FIG. 3 is a sectional view of a second embodiment of the invention.

In the field effect transistor having a recessed structure, the gate electrode 7 above the active layer 2 is /l', and the gate electrode 8 below the active layer is, for example, a P+ type layer formed by ion implantation.

Even if the upper and lower gate electrodes are configured in this manner, there is an advantage that I DS maX can be doubled while maintaining the conventional VH2, as in the case of the first embodiment.

〔Effect of the invention〕

As explained above, in the field effect transistor according to the present invention, by forming gate electrodes facing each other on the upper and lower surfaces of the active layer, it is possible to increase the source-drain current while maintaining the breakdown voltage of the conventional structure. This has the effect of improving output.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the first embodiment of the present invention, FIG. 2 is a diagram showing the depletion layer and electric lines of force in FIG. 1 for detailed explanation of the present invention, and FIG. 4 is a sectional view of the second embodiment of the invention, FIG. 4 is a sectional view of a conventional field effect transistor, and FIG. 5 is a sectional view of fDs in the field effect transistor.
It is a figure showing a VDS curve. 1... Gate electrode, IA... First gate electrode, I
B... second gate electrode, 3... source electrode, 4...
...Drain electrode, 5...N'' type GaAs layer, 6...
・Semi-insulating GaAs substrate, 7... Af gede electrode, 8
...Gate electrode, 10...Center line. iA: 尤ff) Day F'j1 bag, /E -IF! 'q
f"L electric 1'l 2: death vt gi II!r O 2 times 7: A1 ke" not set 3: 5'' electric, j-
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Claims (1)

[Claims] an active layer formed on a semi-insulating substrate; a first gate electrode formed on the surface of the active layer; and a first gate electrode formed at the bottom of the active layer opposite to the first gate electrode; A field effect transistor comprising a gate electrode and a second gate electrode electrically connected outside the active layer region.