JPS61202470A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61202470A JPS61202470A JP60043122A JP4312285A JPS61202470A JP S61202470 A JPS61202470 A JP S61202470A JP 60043122 A JP60043122 A JP 60043122A JP 4312285 A JP4312285 A JP 4312285A JP S61202470 A JPS61202470 A JP S61202470A
- Authority
- JP
- Japan
- Prior art keywords
- normally
- region
- fet
- ohmic
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 108091006146 Channels Proteins 0.000 abstract 5
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101150055505 RFS1 gene Proteins 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、少なくとも２つの電界効果トランジスタ（以
下ｒＦＥＴＪと略す）から成るインバータを含む半導体
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device including an inverter consisting of at least two field effect transistors (hereinafter abbreviated as rFETJ).
従来の技術
従来のＧ ａ Ａ ｔｓ半導体装置のＥ／Ｄ型インバー
タを第３図に示す。第３図（、）は、Ｅ／Ｄ型インバー
タの基本構成回路図で、第３図（ｂ）は第３図（、）を
実現した従来のＥｌＤ型インバータの断面模式図である
。１は半導体基板、２，２′はチャネル領域、３．３′
はオーミック領域、４，４′はオーミック電極、６，５
′はゲート電極、６，６′は空乏領域、。2. Description of the Related Art A conventional E/D type inverter of a Ga Ats semiconductor device is shown in FIG. FIG. 3(,) is a basic configuration circuit diagram of an E/D type inverter, and FIG. 3(b) is a schematic cross-sectional view of a conventional EID type inverter that realizes FIG. 3(,). 1 is a semiconductor substrate, 2 and 2' are channel regions, and 3.3'
is an ohmic region, 4, 4' are ohmic electrodes, 6, 5
' is a gate electrode, and 6 and 6' are depletion regions.
ｖＤＤは駆動用電源、ｖ、ｎは入力電圧、ｖｏｕ、は出
力電圧、ＧＮＤ は接地である。第３図（、）の負荷用
のノーマリオン型ＦＥＴａと駆動用のノーマリオフ型Ｆ
ＥＴ７は第３図（ｂ）のノーマリオン型ＦＥＴ８とノー
マリオフ型ＦＥＴ７に対応している。従来のインバータ
は第３図（ロ）のように構成され、同一基板上に２つの
ＦＥＴ があり、これらのチャネル長方向が同方向であ
る。vDD is a driving power supply, v and n are input voltages, vou is an output voltage, and GND is a ground. Figure 3 (,) normally-on type FETa for load and normally-off type F for drive
ET7 corresponds to the normally-on type FET8 and the normally-off type FET7 shown in FIG. 3(b). A conventional inverter is constructed as shown in FIG. 3(b), and has two FETs on the same substrate, and their channel lengths are in the same direction.
また活性層３，３′の厚さはノーマリオフ型ＦＥＴｙよ
りノーマリオン型ＦＥＴａＯ方が厚い。Further, the active layers 3 and 3' are thicker in the normally-on type FETaO than in the normally-off type FETy.
発明が解決しようとする問題点
上記のような従来のインバータ構成では、ソース、ドレ
インのオーミック領域と、ノーマリオン型ＦＥＴ のチ
ャネル領域と、ノーマリオフ型のチャネル領域形成のた
めのイオン注入工程を別々に行なっている。このため、
注入時のイオン注入量と加速電圧の制御が難しく、また
注入イオン活性化のために行なう熱処理の不安定によシ
ノーマリオン型ＦＥＴとノーマリオフ型ＦＥＴ各々の閾
値電圧７丁の同時制御が困難であり歩留りの低下となっ
ている。またゲート金属とチャネル領域表面のショット
キ接触が悪いために相互コンダクタンス９ｍが上がらな
い。Problems to be Solved by the Invention In the conventional inverter configuration as described above, the ion implantation process for forming the source and drain ohmic regions, the normally-on FET channel region, and the normally-off channel region is performed separately. I am doing it. For this reason,
It is difficult to control the ion implantation amount and accelerating voltage during implantation, and the instability of the heat treatment performed to activate the implanted ions makes it difficult to simultaneously control the seven threshold voltages of each of the synormal-ion type FET and normally-off type FET, which reduces yield. has decreased. Furthermore, the mutual conductance 9m does not increase because of poor Schottky contact between the gate metal and the surface of the channel region.
本発明は、かかる点に鑑みてなされたもので簡易な構成
で、ノーマリオン型ＦＥＴとノーマリオフ型ＦＥＴの閾
値電圧ｖＴの同時制御可能な構造の半導体装置を提供す
ることを目的としている。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a simple structure and a structure in which the threshold voltage vT of a normally-on type FET and a normally-off type FET can be controlled simultaneously.
本発明は上記の問題点を解決するため、ノーマリオン型
ＦＥＴとノーマリオフ型ＦＥＴの各々のチャネル方向を
結晶軸〈０１〒〉方向と結晶軸くｏ〒〒〉方向とするも
のであｐ、ゲート金属として、埋め込み可能な金属とす
るものである。In order to solve the above-mentioned problems, the present invention sets the channel directions of the normally-on type FET and the normally-off type FET to be the crystal axis <01〒> direction and the crystal axis o〒〒> direction. The metal is a metal that can be embedded.
作用
本発明は上記した構成により、従来のイオン注入工程と
熱処理工程で起こるＥ／Ｄ型インバータを構成するＦＥ
Ｔの閾値電圧ｖＴを精度よく安定に制御できるのである
。Operation The present invention has the above-described structure, and the FE that constitutes the E/D type inverter that occurs in the conventional ion implantation process and heat treatment process.
The threshold voltage vT of T can be controlled accurately and stably.
実施例
以下、本発明の実施例を第１図、第２図を用いて詳細に
説明する。Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to FIGS. 1 and 2.
第１図は本発明の半導体装置の一実施例を示すＥ／Ｄ型
インバータの断面模式図である。FIG. 1 is a schematic cross-sectional view of an E/D type inverter showing an embodiment of the semiconductor device of the present invention.
第１図において、（１００）ＧａＡｓ半絶縁性基板１上
にチャネル長方向が結晶軸〈０１〒〉方向と同じ方向に
なるようにＦＥＴのンース、ドレイン領域となるオーミ
ック領域３が形成され、両オーミンク領域をはさんでチ
ャネル領域２が形成されている。一方、チャネル長方向
が結晶軸＜ｏＴ；＞方向と同じ方向にも前記同様のオー
ミック領域３′とチャネル領域２′が形成されている。In FIG. 1, ohmic regions 3 that will become the source and drain regions of the FET are formed on a (100) GaAs semi-insulating substrate 1 so that the channel length direction is in the same direction as the crystal axis <01〒> direction. A channel region 2 is formed across the ohmink region. On the other hand, an ohmic region 3' and a channel region 2' similar to those described above are also formed in the direction in which the channel length direction is the same as the crystal axis <oT;> direction.
ここで＜０１１＞方向に形成されたＦＥＴのドレインと
なるオーミック領域３と＜ｏＴ１″〉方向に形成された
ＦＥＴのソースとなるオーミック領域３′は同一領域で
形成されている。オーミック領域３，３′上にオーミッ
ク電極４．４′が形成され、オーミック領域をはさんで
、チャネル領域２，２′の中央部にシ町ット電極５，５
′が形成されている。＜０１１〉方向に形成されたオー
ミック領域３、チャネル領域２、オーミック領域３でＥ
／Ｄ型インバータの駆動用ＦＥＴであるノーマリオフ型
ＦＥＴ７が構成され、＜ｏｉｒ＞方向に形成されたオー
ミック領域３′、チャンネル領域２′、オーミック領域
３′でＥ／Ｄ型インバータの負荷用のＦＥＴであるノー
マリオン型ＦＥＴが構成される。〈０１１〉方向に形成
されたＦＥＴ７のソース電極４を接地ＧＮＤに落とし、
ゲート電極６を入力ｖｉｎとし、く０〒ｉ〉方向に形成
されたＦＥＴ８のソース電極４とゲート電極５′を短絡
し電源ＶＤＤ に接続し、ドレイン電極４′を出力Ｖ。Here, the ohmic region 3 formed in the <011> direction and serving as the drain of the FET and the ohmic region 3' formed in the <oT1'' direction and serving as the source of the FET are formed in the same region.Ohmic region 3, Ohmic electrodes 4, 4' are formed on 3', and cut electrodes 5, 5 are formed at the center of the channel regions 2, 2' across the ohmic region.
' is formed. E in the ohmic region 3, channel region 2, and ohmic region 3 formed in the <011> direction.
A normally-off type FET 7, which is a driving FET for a D-type inverter, is configured, and an ohmic region 3', a channel region 2', and an ohmic region 3' formed in the <oir> direction serve as a FET for a load of an E/D-type inverter. A normally-on type FET is constructed. The source electrode 4 of the FET 7 formed in the <011> direction is dropped to the ground GND,
The gate electrode 6 is set as the input vin, the source electrode 4 and the gate electrode 5' of the FET 8 formed in the 0〒i> direction are short-circuited and connected to the power supply VDD, and the drain electrode 4' is set as the output V.
Ｕ、とすることによりＥ／Ｄ型インバータが構成される
。U, an E/D type inverter is constructed.
この場合＜０１１＞方向とく０１１″〉方向に形成され
るチャネル領域２，２′は、１回のイオン注入で行なわ
れ１回の熱処理により形成されている。In this case, the channel regions 2, 2' formed in the <011> direction and the <011''> direction are formed by one ion implantation and one heat treatment.
チャネル領域表面上に形成されたゲート電極の金属にＰ
、を含んだ金属を用い、Ｐ、埋め込み（拡散）用のシン
クによシ、ＧａＡｓ基板表面の表面準位のショットキ特
性劣化を回避するため深い所にショットキ接合を得てい
る。この時Ｐ、埋め込み用シンク時間により結晶軸＜０
１１＞方向と＜０１１ ＞方向のＦＥＴのゲート金属の
ｐｔ拡散が異なり、＜ｏｊ’；＞方向０ＦＥＴ よｐ＜
ｏ１〒〉方向のＦＥＴ の方が１６５倍程変速いため同
じシンク時間でも＜０；；＞方向のＦＥＴが早くエンハ
ンスされる。よって、同一不純物濃度を有するチャネル
領域でも、ＦＥＴのチャネル長方向を結晶軸＜０；；＞
方向とく０１１′〉方向にすることにより、ゲート金属
Ｐ、のシンク時間を制御することによりノーマリオフ型
ＦＥＴとノーマリオン型ＦＥＴが構成できる。P is added to the metal of the gate electrode formed on the surface of the channel region.
, a Schottky junction is obtained in a deep place to avoid deterioration of the Schottky characteristic of the surface level of the surface of the GaAs substrate. At this time, P, the crystal axis < 0 due to the embedding sink time
11> direction and <011> direction FET gate metal pt diffusion is different, <oj';> direction 0FET yop<
Since the FET in the o1〒〉 direction changes about 165 times faster, the FET in the <0;;> direction is enhanced faster even with the same sink time. Therefore, even in channel regions having the same impurity concentration, the channel length direction of the FET is aligned with the crystal axis <0;;>
By setting the direction to the 011'> direction, a normally-off type FET and a normally-on type FET can be configured by controlling the sink time of the gate metal P.
第２図において、３８０ ’ＣのＰｔシシンによる上記
の＜０１１〉方向のＦＥＴ７の閾値電圧ｖＴＥと＜０１
１）方向ｏＦＥＴ８（７）閾値電圧ｖＴＤの関係をシン
ク時間で記述した。In FIG. 2, the threshold voltage vTE of the FET 7 in the <011> direction due to the Pt current of 380'C and the <01>
1) The relationship between directional oFET8 (7) threshold voltage vTD was described in terms of sink time.
第２図の関係から、シンク時間により両ＦＥＴの閾値電
圧が変化し、シンク時間２０分の時くｏ〒〒〉方向のＦ
ＥＴ８の閾値電圧が＋０．１■で＜ｏｌｉ＞方向のＦＥ
Ｔ７の閾値電圧が一〇、ＳＶとなり、それぞれノーマリ
オフ型ＦＥＴ 、ノーマリオン型ＦＥＴが実現される。From the relationship shown in Figure 2, the threshold voltage of both FETs changes depending on the sink time, and when the sink time is 20 minutes, the FET in the direction of
FE in the <oli> direction when the threshold voltage of ET8 is +0.1■
The threshold voltage of T7 becomes 10 and SV, and a normally-off type FET and a normally-on type FET are realized, respectively.
また１回のイオン注入と熱処理によりＦＥＴの設定閾値
電圧に対するバラつきは６０％程度であるため、従来の
ノーマリオン型ＦＥＴとノーマリオフ型ＦＥＴの２回の
チャネル領域のイオン注入によるＥ／Ｄ型インバータの
歩留シは２６チ程度となる。しかし本実施例の半導体装
置による素子構成によれば、１回のイオン注入のみでＥ
／Ｄ型インバータがつくられ歩留りも５０％程度となる
。Furthermore, since the variation in the set threshold voltage of the FET is about 60% due to one ion implantation and heat treatment, the E/D type inverter is The yield will be about 26 pieces. However, according to the element configuration of the semiconductor device of this embodiment, only one ion implantation is required to achieve E.
/D type inverter is manufactured and the yield is about 50%.
以上のことにより１回のイオン注入で、ゲート金属であ
るＰ、のシンク時間を変化することによシ両ＦＥＴの閾
値電圧を精度よく安定に再現できることがわかる。From the above, it can be seen that the threshold voltages of both FETs can be accurately and stably reproduced by changing the sink time of P, which is the gate metal, with one ion implantation.
なお、本発明の実施例で用いた半導体基板１は、あらか
じめ導電体層が形成された液相成長または気相成長、Ｍ
ＢＥなどのエピタキシーによる半導体基板であってもよ
い。Note that the semiconductor substrate 1 used in the embodiments of the present invention was manufactured by liquid phase growth or vapor phase growth, M
A semiconductor substrate formed by epitaxy such as BE may also be used.
また、本発明の一実施例で説明したゲート金属はＰ、に
限らず半導体基板に対してショットキ効果をもつ金属で
、シンクによる埋込み可能な金属であればよい。Furthermore, the gate metal described in the embodiment of the present invention is not limited to P, but may be any metal that has a Schottky effect on the semiconductor substrate and that can be embedded by a sink.
更に、本発明の一実施例で説明した化合物半導体基板は
、Ｇ ａ Ａ ｇに限らず、その他のＩｎＰ などの
■−ｖ族化合物半導体またはＺｎＳ などのｎ−■族
化合物半導体であってもよい。Further, the compound semiconductor substrate described in one embodiment of the present invention is not limited to GaAg, but may be other ■-v group compound semiconductors such as InP or n-■ group compound semiconductors such as ZnS. .
一方、本発明の実施例では、ショットキゲートのＦＥＴ
について説明したが、導電型半導体層に対しｐ−ｎ接合
を形成する金属を用いたｐ−ｎ接合型トランジスタであ
ってもよい。On the other hand, in the embodiment of the present invention, the Schottky gate FET
However, a p-n junction transistor using a metal forming a p-n junction with a conductive semiconductor layer may be used.
発明の効果
以上述べてきたように、本発明の半導体装置は、安定に
精度よ（ＦＥＴの閾値電圧を制御可能な極めて簡易な素
子構成である。したがって実用的に極めて有用である。Effects of the Invention As described above, the semiconductor device of the present invention has an extremely simple element configuration that can stably and accurately control the threshold voltage of the FET. Therefore, it is extremely useful in practice.
例のチャネル長方向が＜０１１＞、＜ｏｒ１″〉方向と
同一である ＦＥＴのゲート金属Ｐ、のシンク時間に対
する閾値電圧の変化を示す図、第３図（、）は従来のＥ
／Ｄ型インバータの基本回路図、第３図（ｂ）は第３図
（、）の回路を実現した従来のＥ／Ｄ型インバータの断
面図である。
１・・・・・半導体基板、２，２′・・・・・・チャネ
ル領域、３．３′・・−・・・オーミック領域、４，４
′−・・・・・オーミック電極、５．６′・・・・・・
ゲート電極、６．６′・・・・・・空乏層、７・・・・
・ツーマリオフ型ＦＥＴ 、ｓ・・・・・ツーマリオン
型ＦＥＴ 。
１・−のＡ５ｔｖｌ＆社４返
７°°−メーフリ不７譬ＦＥｒ
第２図
４ンシタｇ’ｒｆｓ１（骨２Figure 3 (,) is a diagram showing the change in threshold voltage with respect to the sink time of the gate metal P of an FET in which the channel length direction is the same as the <011> and <or1''> directions.
3(b) is a sectional view of a conventional E/D type inverter that realizes the circuit shown in FIG. 3(,). 1... Semiconductor substrate, 2, 2'... Channel region, 3.3'... Ohmic region, 4, 4
′-・・・Ohmic electrode, 5.6′・・・・・・
Gate electrode, 6.6'...depletion layer, 7...
・Two-mullion-type FET, s...Two-mullion-type FET. 1.-A5tvl & company 4 return 7°°-Meefurifu7manFEr Fig. 2 4nshita g'rfs1 (bone 2
Claims (2)
電界効果トランジスタを有するインバータを含み、前記
インバータが第１のノーマリオン型電界効果トランジス
タと第２のノーマリオフ型電界効果トランジスタより成
り、前記第１の電界効果トランジスタのチャネル長方向
は＜０＠１＠＠１＠＞方向にあり、前記第２の電界効果
トランジスタのチャネル長方向は結晶軸＜０１＠１＠＞
方向にあり、前記第１の電界効果トランジスタのソース
・オーミック領域と第２の電界効果トランジスタのドレ
イン・オーミック領域とが共通であることを特徴とする
半導体装置。(1) An inverter having at least two field effect transistors on 100 planes of a compound semiconductor substrate, the inverter comprising a first normally-on field effect transistor and a second normally-off field effect transistor, and the first The channel length direction of the field effect transistor is in the <0@1@@1@> direction, and the channel length direction of the second field effect transistor is along the crystal axis <01@1@>.
1. A semiconductor device, wherein the source ohmic region of the first field effect transistor and the drain ohmic region of the second field effect transistor are common.
は、化合物半導体基板に埋め込み可能な金属であること
を特徴とする特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the gate metal of the first and second field effect transistors is a metal that can be embedded in a compound semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60043122A JPS61202470A (en) | 1985-03-05 | 1985-03-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60043122A JPS61202470A (en) | 1985-03-05 | 1985-03-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61202470A true JPS61202470A (en) | 1986-09-08 |
Family
ID=12655029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60043122A Pending JPS61202470A (en) | 1985-03-05 | 1985-03-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61202470A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01273359A (en) * | 1988-04-26 | 1989-11-01 | Nec Corp | Semiconductor integrated circuit |
| JP2012010582A (en) * | 2010-05-26 | 2012-01-12 | Semiconductor Energy Lab Co Ltd | Photoelectric conversion device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5979577A (en) * | 1982-10-29 | 1984-05-08 | Fujitsu Ltd | Semiconductor integrated circuit device |
-
1985
- 1985-03-05 JP JP60043122A patent/JPS61202470A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5979577A (en) * | 1982-10-29 | 1984-05-08 | Fujitsu Ltd | Semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01273359A (en) * | 1988-04-26 | 1989-11-01 | Nec Corp | Semiconductor integrated circuit |
| JP2012010582A (en) * | 2010-05-26 | 2012-01-12 | Semiconductor Energy Lab Co Ltd | Photoelectric conversion device |
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