JPS61161771A - Schottky gate field effect transistor - Google Patents
Schottky gate field effect transistorInfo
- Publication number
- JPS61161771A JPS61161771A JP273685A JP273685A JPS61161771A JP S61161771 A JPS61161771 A JP S61161771A JP 273685 A JP273685 A JP 273685A JP 273685 A JP273685 A JP 273685A JP S61161771 A JPS61161771 A JP S61161771A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- low concentration
- active layer
- concentration layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 4
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ショットキーゲート電界効果トランジスタ、
特に高周波領域で使用可能な０−Ａｓシゴ、トキーゲー
ト電界効果トランジスタ（以下Ｇ ａ Ａ ａＭＥＳＦ
ＥＴと称す）の構造に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a Schottky gate field effect transistor,
In particular, 0-As gate field effect transistors (hereinafter referred to as G a A a MESF) that can be used in the high frequency region
ET).
従来、Ｇ ＆Ａ ｓ ＭＥ Ｓ Ｆ Ｅ Ｔは能動層と
なるＮ型領域をＶＰＥ、ＭＯＣＶＤ、ＭＢＥ 等Ｏｚ
ピＩＸ−？ シ、 ル技術及びイオン注入技術等で形成
しゲートとなるショットキー電極を能動層上に直接形成
した構造となっていた。Conventionally, G&A's MESFET uses VPE, MOCVD, MBE, etc. for the N-type region that becomes the active layer.
Pi IX-? It had a structure in which a Schottky electrode, which served as a gate, was formed directly on the active layer using silicone or ion implantation technology.
上述した従来構造のＧ ａ Ａ ｓ Ｍ Ｅ Ｓ Ｆ
Ｅ Ｔはゲートのピンチオフ電圧（Ｖｐ ）及び相互コ
ンダクタンス（ｔｍ）等の要求によりＦＥＴ能動層とな
るＮ型領域の濃度は５Ｘ１０ ”儒−ｅ〜５Ｘ１０”備
−程度必要であシ、ゲート・ソース間容量（Ｃｒｓ）、
ゲート・ドレイン間容量（Ｃｆｄ）等はゲート長（Ｌｒ
）及びゲート巾（Ｗｒ）の大きさがきまると大巾な改善
の余地がなかった。The above-mentioned conventional structure G a A S M E S F
ET, the concentration of the N-type region that becomes the FET active layer needs to be about 5X10" due to requirements such as the pinch-off voltage (Vp) and mutual conductance (tm) of the gate, and the concentration of the gate and source Interval capacity (Crs),
The gate-drain capacitance (Cfd) etc. is determined by the gate length (Lr
) and gate width (Wr), there was no room for significant improvement.
Ｇ ａ Ａ ｓ Ｍ １８ Ｆ Ｅ Ｔの高周波特性を
改善する方法としては相互コンダクタンス（ｆｍ ）の
向上及ヒゲート・ドレイン問答Ｊｌ （Ｃｙｓ ）の低
減が必要である。In order to improve the high frequency characteristics of GaAsM18FET, it is necessary to improve the mutual conductance (fm) and reduce the gate-drain Jl (Cys).
９ｍの向上の為にはＮ型能動層濃度を増加させることが
必要となシこのことｔｊ：ｃｆｓの増加の原因となって
いる。従って従来技術ではゲート長（Ｌｒ）を短かくす
る方向で改善を計っているが、リソグラフィー技術の限
界に近づいている。9m, it is necessary to increase the N-type active layer concentration, which causes an increase in tj:cfs. Therefore, in the prior art, improvements have been made in the direction of shortening the gate length (Lr), but this is approaching the limit of lithography technology.
本発明の目的は上述した従来構造のＦＥＴの欠点を回避
し、ＦＥＴ能動層となるＮ型領域の濃度が直接ゲート・
問答ス間容量（Ｃｐｓ）及びゲート・ドレイン間容量（
Ｃｒｄ）に影響を及はさないＦＥＴ−の構造を提供する
ことＫある。The purpose of the present invention is to avoid the above-mentioned drawbacks of the conventional FET structure, and to ensure that the concentration of the N-type region serving as the FET active layer is directly connected to the gate.
Q&A space capacitance (Cps) and gate-drain capacitance (
It is possible to provide a FET structure that does not affect Crd).
本発明忙よるＭＥＳＦＥＴは、半絶縁性半導体基板上に
形成した５Ｘ１０ ” 〜５Ｘ１７ ”Ｏｆｆ −”
（７）濃度の一導電型能動層と、このＮ型能動層上ＫＩ
ＸＩＯ”・備−１以下の一導電型低濃度層と、ソース及
びドレインとなる領域に形成された前述の低濃度層を貫
通する一導電型高濃度層と、前述の低濃度層上く形成さ
れたゲート電極となるショッ電極−電極ト、前述の高濃
度層上に形成されたソース電極及びドレイン電極とを有
している。The MESFET according to the present invention is a 5X10" to 5X17"Off-" MESFET formed on a semi-insulating semiconductor substrate.
(7) Concentration of one conductivity type active layer and KI on this N type active layer
A low-concentration layer of one conductivity type of XIO". It has a shot electrode to serve as a gate electrode, and a source electrode and a drain electrode formed on the above-mentioned high concentration layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の一実施例の工程順に示
した断面図で、まず同図（ａ）Ｋ示す様に半絶縁性Ｇ
ａ Ａ ｍ基板１に選択イオン注入法によりＦＥＴ能動
層２を形成する。次に同図（ｂ） Ｋ示す様に、能動
。FIGS. 1(a) to 1(f) are cross-sectional views showing the steps of an embodiment of the present invention. First, as shown in FIG. 1(a)K, a semi-insulating G
a FET active layer 2 is formed on substrate 1 by selective ion implantation. Next, as shown in Figure (b) K, the active
.
層２よシも濃度の低いＧａＡｓ単結晶３をｖｐｇ。Layer 2 and GaAs single crystal 3 with low concentration are vpg.
ＭＯＣＶＤ法等圧よシ成長する。次に同図（Ｃ）に示す
様に各々ソース及びドレイン領域となる部分を選択イオ
ン注入法により低濃度層３を貫通する高濃度層４，５を
形成する。次に同図（ｄ）に示す様にＦＥＴ部分以外の
不要な低濃度層３を工、チングする。次に同図（ｅ）Ｉ
ＩＣ示す様にゲートとなるシヨ。Growth is carried out using the MOCVD method. Next, as shown in FIG. 3C, high concentration layers 4 and 5 are formed to penetrate through the low concentration layer 3 by selective ion implantation in portions that will become the source and drain regions, respectively. Next, as shown in FIG. 3(d), unnecessary low concentration layer 3 other than the FET portion is etched. Next, in the same figure (e) I
As shown in the IC, it becomes a gate.
トキー電極６を蒸着法、スパッタ法及び選択工。Tokey electrode 6 is formed by vapor deposition method, sputtering method, and selective processing.
チング法で形成する。次に同図（ｆ）に示すようにソー
ス電極８及びドレイン電極９を形成する。Formed using the ching method. Next, as shown in FIG. 3(f), a source electrode 8 and a drain electrode 9 are formed.
以上説明した本発明の構造によると、例えば低濃度層３
の濃度をｌ×ｌＱ”ｃｒＰＭ””、厚さを１００ＯＡ及
び能動層をｌＸｌ０”ｌｔ”Ｋした場合ゲートバイアス
（ＶＧ ）がＯｖの時にゲート電極直下の空乏層の広が
シは低濃度層３がない場合の広がりに低濃度層厚さを加
えた値に近似することができる。この理由は低濃度層３
を空乏化させる為にわずかの電圧（０，１Ｖ以下）で充
分であることである。According to the structure of the present invention explained above, for example, the low concentration layer 3
When the concentration of is l×lQ"crPM"", the thickness is 100OA, and the active layer is lXl0"lt"K, when the gate bias (VG) is Ov, the depletion layer directly under the gate electrode expands as the low concentration layer 3. It can be approximated to the value obtained by adding the thickness of the low concentration layer to the spread when there is no
A small voltage (less than 0.1 V) is sufficient to deplete the ions.
以上のことから本発明の構造によるとピンチオフ電圧（
ｖｐ）への影響をｔｌとんど与えずソース・ゲート間容
量は低濃度層３の厚さの空乏層広が部分だけ低下させる
ことが可能となる。又相互コンダクタンス（ｆｍ ）
Ｋはほとんど影響をおよぼさないことも明らかである。From the above, according to the structure of the present invention, the pinch-off voltage (
It is possible to reduce the source-gate capacitance by only the portion where the depletion layer spreads in the thickness of the low concentration layer 3 without affecting tl (vp). Also, mutual conductance (fm)
It is also clear that K has little effect.
以上、説明したように、本発明によるＦＥＴ構造を用い
ることにより他のＦＥＴ特性Ｋｆｉとんど影響を及埋す
ことなくゲート・ソース間容量及びゲート・ドレイン間
容量を低下させることが可能となりＦ’ＥＴの高周波特
性例えばｆ ７ （ｆ ７ ｏｃ−’−）Ｐｇ
の向上が容易に可能となりその効果は大きい。As explained above, by using the FET structure according to the present invention, it is possible to reduce the gate-source capacitance and the gate-drain capacitance without affecting other FET characteristics Kfi. It is possible to easily improve the high frequency characteristics of 'ET, for example f 7 (f 7 oc-'-)Pg, and the effect is great.
第１図（ａ）〜（ｆ）は本発明の一実施例をその製造工
程順に示した断面図である。
１・・・・・・半絶縁性Ｇ ａ Ａ ｍ基板、２・・・
・−・ＦＥＴ能動層、３・・・・・・低濃度層、４−・
・・・・ソース高濃度層、５・・・・・・ドレイン高濃
度層、６・・・・・・ゲート・シッットキー電極、７・
・・・・・絶縁膜、８・・・・・・リース電極、９・・
・・・・ドレイン電極。
゛＼、、４FIGS. 1(a) to 1(f) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. 1...Semi-insulating GaAm substrate, 2...
・-・FET active layer, 3...Low concentration layer, 4-・
. . . Source high concentration layer, 5 . . . Drain high concentration layer, 6 . . . Gate Schittky electrode, 7.
...Insulating film, 8...Leath electrode, 9...
...Drain electrode.゛＼、、４
Claims (1)
動層領域と、該能動層領域上に形成された前記一導電型
の低濃度層と、該低濃度層を貫通する前記一導電型高濃
度のソースおよびドレイン領域とを有することを特徴と
するショットキーゲート電界効果トランジスタ。an active layer region of one conductivity type on which a Schottky gate is formed; a low concentration layer of one conductivity type formed on the active layer region; and a high concentration layer of one conductivity type penetrating the low concentration layer. CLAIMS 1. A Schottky gate field effect transistor having a doped source and drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP273685A JPS61161771A (en) | 1985-01-11 | 1985-01-11 | Schottky gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP273685A JPS61161771A (en) | 1985-01-11 | 1985-01-11 | Schottky gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61161771A true JPS61161771A (en) | 1986-07-22 |
Family
ID=11537614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP273685A Pending JPS61161771A (en) | 1985-01-11 | 1985-01-11 | Schottky gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61161771A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6399579A (en) * | 1986-10-16 | 1988-04-30 | Hitachi Ltd | Manufacture of field effect transistor |
| JPS63187667A (en) * | 1987-01-30 | 1988-08-03 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-01-11 JP JP273685A patent/JPS61161771A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6399579A (en) * | 1986-10-16 | 1988-04-30 | Hitachi Ltd | Manufacture of field effect transistor |
| JPS63187667A (en) * | 1987-01-30 | 1988-08-03 | Hitachi Ltd | Semiconductor device |
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