JPS63187667A - Semiconductor device - Google Patents

Abstract

PURPOSE:To lower parasitic resistance by broadening a steep hetero-junction with the exception of a section in which two-dimensional carriers are stored, for example, a GaAs/AlGaAs hetero-junction is disordered. CONSTITUTION:Undoped GaAs 11, N-type GaAs 12 and N<+> GaAs 13 are formed onto semi-insulating GaAs 10, and Zn ions 15 are implanted into source-drain regions. A photo-resist 30 is removed, and SiN is shaped onto the whole surface, and annealed. Consequently, an Al composition can be disordered without largely reducing the carrier concentration of N-type AlGaAs and GaAs in the source- drain regions. Accordingly, contact resistance between a source electrode 20 and a contact layer 16 and parasitic resistance between a gate 22 and the source electrode 20 can be lowered, thus increasing the mutual conductance of an element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the formation of an ohmic contact to a two-dimensional carrier formed at a heterojunction interface, and particularly relates to the formation of an ohmic contact to a two-dimensional carrier formed at a heterojunction interface.
The present invention relates to a semiconductor device that can operate at high speed by reducing inter-gate resistance or parasitic base resistance.

[Conventional technology]

A two-dimensional electron gas (Tw) is formed at the heterojunction interface between n-type AlGaAs (aluminum gallium arsenide) and undoped GaAs (gallium arsenide).

Dimensional Electron Gas
:2DEG) is called a field effect transistor (Fisld Effect Transistor:F
The technical concept of using FETs in the active layer is described in, for example, Japanese Patent Application Laid-Open No. 160473/1983, and
is generally a two-dimensional electron gas field effect transistor (2D
It is called EG-FET). 2DEG-FET
The biggest challenge in improving performance is the source-gate resistance (R
sr). Figure 2(a) shows the conventional structure 2.
A cross-sectional view of DEG-FET is shown in FIG. 2(b), which shows a band diagram near the source electrode.

That is, on a semi-insulating Ga As substrate 1o, an undoped Ga As 11 is deposited with a film thickness of 1 μm to form an ri type A.
ffxGat-xAs (x-0,3) 12 to 50n
The film thickness is around m, and the film thickness of n+GaAs13 is 50 m.
It is formed to have a thickness of about nm. Gate electrode 22 is n-type A
A Schottky junction is made to ΩGaAs, and the source/drain electrodes 20 and 21 form an alloy junction with n+GaAs13. Here, φa1 is the source voltage %20 and n+ type G
This is the Schottky barrier height with aAs13.

The energy band diagram of the conducting part near the source electrode 20 (A-A') is shown in FIG.
As MESFET (Metal Sem1condu
ctor Fj, aldEffect Transis
2DEC-FET, unlike the ohmic contact of
In the case of n”GaAs13 and n-type A Q GaAs
It is formed as a heterojunction between 12 and n-type AlGa
Since a heterojunction is also formed between As12 and undoped GaAs 11, a potential barrier is formed between 2DEG14 and ohmic metal 20, and n+
Contact specific resistance Rc occurred between GaAs13 and 2DEG, which was a major obstacle to reducing Rsz.
In the AsMESFET, the source electrode 20 and the n+ type GaA
Only the contact specific resistance RcTL' with s13 is a problem, but in the case of Rsr of the 2DEG-FET, reducing the contact specific resistance R6 between the heterojunctions becomes a problem.

In addition, as a method of reducing Rsg, a method of activating 81 ions by implanting them into the source/drain region is also used.
A high-temperature process with an activation temperature of around 800° C. is required, and there is a problem in that the layer below the gate electrode becomes disordered. In addition, when using a highly heat-resistant gate metal as a mask material for ion implantation, 1. The threshold voltage of the transistor (V
The so-called short channel effect, in which t h ) shifts to the negative side, has been a problem.

Furthermore, the impurity distribution in AlGaAs changes during the heating process, resulting in a problem of a shift in density.

In addition, as a field effect transistor that utilizes two-dimensional electron gas accumulated at the heterojunction interface, for example, Japanese Journal of Applied Physics No. 19
Volume (1980) PJ) L225-227 (Japa
nese Journal of Appl, ied
Physics.

Vo12.19 Nn5 (1980) PPL225
A field effect transistor using two-dimensional electron gas, so-called H E, was reported by Mimura et al.
MT is attracting attention. HEMT has a cross-sectional structure as shown in Figure 8, and is made of AlGaA with a low single-electron affinity.
A donor impurity is added to the s layer 124, and electrons generated by ionization of the donor impurity become G
It moves to the aAs layer 122 side and forms a two-dimensional electron gas 123. Since the two-dimensional gas travels in the undoped GaAs layer 122 and is less susceptible to scattering of ionized donors,
It can operate at high speed, especially at low temperatures.

Furthermore, gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) heterojunction bipolar transistors (Heterojmtion Bipolar
Transistor (abbreviated as HBT) is conventionally known as MBEC (all EC epitaxy method) or MODV.
Using a crystal growth method such as D (organometallic pyrolysis method),
n-GaAs (collector layer) P+GaAs (base layer) n -A Q GaA's (emitter layer) n+G
After sequential crystal growth of aAs (cap M), the emitter region, emitter electrode, base region, and base electrode are formed.

It is customary to process the collector electrode, collector region, etc. (for example, IEDM 1985 Proceedings, pp. 328-331 (IEDM 1985. P P 32
8-331). However, as is well known, in the case of a Si bipolar transistor, the emitter concentration is 10"an-3, and the base concentration is 10"a++-
” Since the emitter side has a high concentration of about two fingers, after forming the base region, the emitter region can be formed using ion implantation, making it possible to realize an extremely fine n-p junction region, resulting in an extremely fine Fine emitters can be formed (for example, Electronics Letters, Vol. 19 (
1,983) page 283 (Electronics
Lett, Vo Q, 19 Na 8 .

(See April 1983, p. 283). On the other hand, in the case of conventional HBT, in order to lower the base resistance and because there is an upper limit on the emitter concentration, the impurity concentration in the base region is 1016 to 101 g-'''δ, and the impurity concentration of AlGaAs in the emitter region is IQ 17 to 101.
It is customary to form the base region 8an-8 lower than the base region.

Unlike Si bipolar transistors, it has a drawback in that it is not possible to form an emitter region by ion implantation after forming the base region.

Furthermore, since the emitter region is formed using an epitaxial growth method such as MBE/MOC:VD, there is a problem that, unlike ion implantation, it is extremely difficult to process the emitter region finely (~0.5 μm level). was occurring.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, since the heterojunction between the source (or drain) and gate is formed too steeply, a contact specific resistance Rc occurs, making it impossible to reduce the source-gate resistance Rsg.

The purpose of the present invention is to maintain the gate and the heterojunction in the vicinity of the gate sharply (that is, the p, QB ratio・Structure in which the heterojunction between gates gradually collapses (Fig. 1 (a), (b)).

(c), (d) and (e)).
The object of the present invention is to improve the performance of 2DEG-FET by providing a structure that reduces the contact specific resistance Rc at the heterojunction.

Figure 1 (a), (b), (c), (
d) and (e) are examples of cross-sectional views of the 2DEG-FET of the present invention and the spatial distribution of the AI2 composition in the corresponding main parts (first
(b) (c)) and the energy band diagram of the conduction band (
FIG. 1(d)(s)) are shown. In FIG. 1(a), 11 is an undoped GaAs layer, 12 is an n-type AlGaAs layer with an Al2 composition fixed at 0.3, and 12' is a layer with an Af1 composition of
As shown in Figure 1(b), the distribution of AQ is graded (
As a result, in the vicinity of the source electrode, the conduction barrier ΔEC (see FIG. 1(b)) due to the heterojunction disappears.

13 is an n+GaAs layer, 20.21 is a source/drain electrode, and 22 is a gate electrode.

A first object of the present invention is to propose a structure of a semiconductor device with a small parasitic resistance value.

Furthermore, in the HEMT structure, source electrons 25 and 2
Since the A Q GaAsJl 24 with a large band gap is present between the channel part 23 of the dimensional electron gas, it is difficult to reduce the parasitic resistance of the source and gate electrodes.

As a countermeasure to the above problem, AρGa
An ohmic electrode contact layer 135 is formed on the As layer 134. The contact layer uses GaAs, which has a smaller band gap than AlGaAs, and is doped with a high concentration, so that the contact resistance is small. Further, the thickness of the contact layer 35 is increased to several hundreds of Å or more,
There are two electron flow paths, 139 and 140, and a large current can be obtained. That is, the parasitic resistance between the source and gate electrodes can be effectively reduced. However, if the mutual contactance is 3
In order to achieve 00 mS/re or more, it is necessary to further reduce the parasitic resistance.

A second object of the present invention is to provide a field effect transistor in which the parasitic resistance between the source and gate electrodes is extremely small.

Furthermore, in the above conventional technology, the emitter region is doped with impurities by an epitaxial method.

The structure was not suitable for miniaturizing the emitter size. In addition, 6-prong HBT and G
Forming aAs MESFETs on the same substrate also has the disadvantage that it is difficult to produce high-performance MESFETs.

A third object of the present invention is to be suitable for forming fine emitters,
The object of the present invention is to provide an HBT which can have a planar structure and which can be easily formed with a GaAsFET on the same substrate.

[Means for solving problems]

The first purpose is to remove impurities that become p-type after ion implantation and heating (hereinafter referred to as p-type impurities) or atoms that remain neutral after heating (hereinafter referred to as neutral impurities) in the source and drain regions. This can be achieved by configuring half-core regions that are annealed at a relatively low temperature of around 600'C after diffusion or ion implantation into one or both of them.

Literature (e.g. Applied Physics.

Letters, Volume 38, (1981) Page 776 Ap
pl.

Puzs, Lett, 38 (1981) p.
776), it is known that when a p-type impurity such as Zn is diffused into a GaAs/AlGaAs superlattice, AQM molecules are diffused and the superlattice collapses.

Diffusion of Afl occurs even in the case of a single heterojunction;
The steep heterojunctions of GaAs/AlGaAs/GaAs (layers 11, 12, 13) have i atoms diffused into Al1, and AQ
are spatially distributed as shown in FIG. 1(b), and there is no contact resistance between the heterojunctions.

In addition, when neutral atoms such as F and Ar ions are implanted, annealing at a low temperature of around 650°C (about the crystal growth temperature during crystal growth such as MBE) diffuses F and AryK atoms and restores the original structure. The carrier concentration of the n-type Q a A S pAlGaAs region can be maintained.

During the annealing process, implanted atoms diffuse and as a result An
The compositional disorder occurs in F, A r
In addition to P (proton), As, Br Xs.

There are atoms such as Ne.

In addition, in the present invention, the amount of impurity atoms added is 1X101δ~
5 X 10”cm-3, annealing temperature is 500~
It can be carried out at 900°C.

Various mixed crystal semiconductors can be used as semiconductors, but the main ones are GaAs/AlGaAs and InP/GaA.
It is s.

The second object is achieved by making the semiconductor contact layer for the ohmic electrode as thick as 500 Å or more and providing a lattice structure on the surface of the contact layer.

Note that if the thickness of this contact layer exceeds 2 μm, the greater effect of the present invention cannot be obtained, and the economic cost will increase.

Furthermore, the third objective is to use epitaxial techniques such as MBE/MOCVD to avoid doping the emitter region above the base layer (undoped to 10+12Iaa).
-” or higher p type) is formed, then an emitter region and a base extraction region are formed using ion implantation to form I (B T), and an active layer is formed using ion implantation. This is achieved by forming an A s F IET.It is possible to create an HBT in this way.
-” is one order of magnitude larger than the emitter region, so 1017~
In forming the emitter region where 10"an-8 n-type impurity is implanted, the n-type impurity entering the p-type region can be ignored. Also, in the process of annealing the implanted n-type impurity, the n-type impurity in the base region If measures are taken to prevent impurities from moving significantly, the Dp junction position and the heterojunction position will almost match, and the characteristics of the HBT will not be impaired.

After embedding the collector region in the semi-insulating GaAs substrate, undoped GaAs, p+Ga
As.

After sequentially forming undoped AQ GaAs and GaAs, n+ ions are implanted into the emitter region, and p+G
P+ ion implantation may be performed to form a lead-out region of the aAs base layer. Alternatively, by reversing the emitter and collector layers and epitaxially growing the emitter layer on the entire surface by MBE, etc., or selectively forming it in a semi-insulating substrate, after epitaxially growing the base region p+GaAs layer, an undoped GaAs layer is formed. The collector layer may be selectively formed in the plane using n+ ion implantation. Ga
The outline of the present invention is shown in Fig. 10 (a) and (b) with the case where the present invention is applied to As/AlGaAs and HB I in mind.
Explain using.

On the semi-insulating GaAa substrate 10 is an n+GaAs 11- collector layer 12, which is a p+GaAs collector.
An As13 layer is formed by MBE/MOCVD or the like as in the conventional example, and an undoped (~p-1013 residual level of 1 δ level) AlGaAs14. Each layer of GaAs 15 is successively formed (FIG. 10(a)).

Using the ion implantation method, the p+ Bebe extraction region 21.
The base electrodes 34 are formed respectively, and the n-type emitter region 20 is formed by ion implantation, and the n-type active layer 24 of the GaAsFET is formed using the undoped layers 15 and 14. n tenth layer 23
etc. are also formed using the ion implantation method. 31.32 are source and drain electrodes, 30 is a gate electrode, 33.35
are the emitter electrode and collector electrode, respectively, and 522
is the n+ extraction area from the collector area 11. The reason why the emitter region can be formed using the ion implantation method in this way is that the doping level on the emitter side is nearly an order of magnitude lower than that on the base side, as shown in Figure 10 (C). It hardly affects the impurity level in the base region.

This takes advantage of the unique properties of a heterojunction, which allows the doping level of the base region to be increased by using a heterojunction.

[Effect]

In the first method, the heterojunction of the source/drain region is changed from Ga As to A by diffusion of A Q H atoms.
It shows a continuous change to lGaAs.

At this time, the potential barrier caused by the band gap of the heterojunction disappears for electrons, and an ohmic mechanism similar to that of normal homojunction GaAsME and SF[T occurs.

Furthermore, since the gate electrode-sized heterojunction is located on a steep island, n-type GaAs can be accurately and selectively removed by etching to form the gate electrode.

In particular, when neutral atoms such as F and Ar atoms are implanted, it is possible to cause disorder in the AR at relatively low temperatures and to keep n-type impurities such as Si atoms in an activated state. be.

Furthermore, when n-type impurity atoms such as Zn are implanted, a p-type GaAs region is formed under the two-dimensional electron gas, and short channel effects and the like associated with shortening of the gate length are reduced.

In the second method described above, by using a thick (500 Å or more) conductive type contact layer 1 doped with a high concentration in the ohmic fim contact layer, the contact resistance can be reduced and the electron flow paths can be set in two ways (the third (shown in FIG. 39.40), and the parasitic resistance between the source and gate ff1t4 is also reduced.

Further, the lattice structure provided on the surface of the contact layer allows a large contact area with the ohmic "ftL pole" and a large amount of electron injection near the edge of the bottom of the recess, so that the contact resistance can be significantly reduced.

Furthermore, from a quasi-macroscopic perspective, the increase in the contact area with the electrode due to the recess means that the m-7 flow path increases as shown by the arrow in the contact layer 1.5 in Figure 1, which results in parasitic resistance. is effectively reduced.

In the third method, the emitter layer is left in an undoped state as described above, and then the emitter region + GaAsFET region can be formed using the ion implantation method, so the emitter region can be made as fine as the FET. It becomes possible to do so. The base extraction region can be easily formed with a planar structure using an ion implantation method.

Furthermore, since the emitter region is formed by ion implantation, the emitter region consists only of the implanted portion, and as a result, it is possible to extremely reduce the parasitic capacitance between the emitter and the base.

〔Example〕 Hereinafter, the present invention will be described in detail with reference to examples.

Example 1 FIGS. 3(a) and 3(b) show an example in which the present invention is applied to an AuGaAs/GaAs 2DEG-FET.

This will be explained using (c).

M B E (Molecular Beam Epi
Taxy: Molecular beam epitaxy)
500 nm of undoped GaAs1l on aAs1O
, n-type Ga containing Si to the extent of IXIQ16a++-"
After forming n+GaAs13 containing 50 nm of As12 and 2X10" δ mark -88 degrees of Si to a thickness of about 20 nm to 160 nm, Zn ions 15 are added to the source/drain regions at 1xlO130-8 at an accelerating voltage of 120 keV.
Inject at a soft dose (Fig. 3(a)).

Next, after removing the photoresist 30, a SiN film JFg with a thickness of 200 nm was formed on the entire surface, and lamp annealing was performed at 600° C. to 800° C. for 20 minutes. Thereafter, the gate electrode 22. Source/drain voltages t420, 21 were formed (Fig. 3(b)
)).

However, without destroying the heterojunction below the gate electrode part, the n-type AlGa in the source/drain region can be
In order to cause the Af1 composition to become disordered without greatly reducing the carrier concentration of Asv GaAs, it is necessary to perform heat treatment after implantation, regardless of which atoms are implanted. At that time, it is necessary to prevent defects from occurring in the Schottky junction of the gate electrode to AlGaAs by heat treatment.

FIG. 3(c) shows that it is also possible to implant Zn15 or the like which causes AQ disorder using the high heat-resistant gate metal 22' as a mask material.

Zn behaves as a p-type impurity after annealing, but n-type GaAs13. By increasing the Si concentration of n-type AlGaAs12 to a sufficiently high level (~2 x 10" δα-8 level),
The n-type region can be maintained as n-type without being inverted to p-type.

In addition, implanting Zn into the undoped GaAs portion and subjecting it to heat treatment makes it weakly p-type, but this is effective in suppressing the so-called short channel effect.

This is a remarkable effect of implanting impurities that become p-type after annealing.

That is, when Si is implanted as usual, ohmic contact is improved, but an n+ region is formed diagonally below the 2DEG layer, causing a so-called short channel effect. The short channel effect is an effect in which the threshold voltage V th shifts to the negative side in the process of shortening the gate length Lx from 1 μm to 0.3 μm, for example.

In order to disorder the Af1 composition without greatly reducing the chiaria degree of the n + Ga As region 13, in addition to Zn atoms, in addition to p-type impurities such as Be + Ge, F, Ar, and Ne are added. , Xe, protons, etc., which are neutral atoms after heating may be used.

For example, in the case of Ar, the AQ composition becomes disordered when A r + 10 is accelerated at 150 keV Ya pressure, 4 X 10"QI+-' (7) dose, and heated at 680°C for 20 minutes. Ohmic improvement If the level of disorder.

An improvement effect could be obtained even at a dose level of 1Xl0"am""8.

In this embodiment, when n+-GaAs13 is used to reduce the source/gate resistance Rsz, its film thickness should be adjusted.

For example, it is necessary to increase the thickness to 160 nm.

1020an'''3 of As instead of n-type GaAs12
n+Ge containing 8 degrees may also be used. in this case,
The disorder of the heterojunction is caused by the AlGaAs layer 12' and Ga
This occurs mainly between the As layers 11.

Example 2 2DEG-HB T using two-dimensional electron gas as base layer
FIGS. 4(a) and 4(b) show examples in which the present invention is applied to
).

using MBE on a semi-insulating GaAs1O substrate.

Be 1. X], P+G containing 019an-8
GaAs16500n, undoped GaAs1l 30
Onm, n-type An containing 2X1018an-8 Si
40 parts m of GaAs12, 50 parts m of p+AlGaAs L7 containing 2×101θ−3 Bs, and 20 Onm of p+GaAs18 having the same doping level were formed.

Subsequently, using SiN30' as a mask in the base region, Zn was applied at an accelerating voltage of 250 keV.

After implanting a dose of 3XLO130-2 and removing S x N, 5iO2 (film thickness 200 nm) was deposited by CVD. Next, l-I2 was annealed at 650°C for 30 minutes.
＃Do it with Iki. Following the normal process, emitter electrode 2
5. Base electrode 23. A collector electrode 24 was formed in each case (FIG. 4(b)).

In addition to Zn, the implanted ions in this example include F,
G e r B e, A, s, A r,
Protons etc. may also be used.

In the above embodiments, the case where an n-channel is used has been described in detail, but when using an n-channel (two-dimensional hole gas), Si, Se, etc. are used instead of Zn as implanted ions.
, etc. are valid.

Also, the semiconductor material is InP/InGaAsP.

It is also effective in other heterozygous systems such as InAQAs/InAsP.

Another ionic species that can disorder the heterojunction is fluorine atom F. In this case, heating in GaAs at a relatively low temperature of 650 to 700 °C for nearly 2 hours without activation leads to disorder of the heterojunction and the expansion of the atoms in the GaAs, resulting in a change in the external shape. I'm leaving.

Example 3 An example of causing disorder using F atoms will be explained.

The case where the area under the gated NA is a superlattice will be explained with reference to FIG. On the semi-insulating GaAs substrate 1o,
Undoped G a A, sLl, 1 using the MBE method
After forming μm, undoped A Q x Gat-x A
s (approximately selected in the range of 0, 3 < x < l, O) layer 40 is 3r + rn, Si is 5
A Q x
After forming 8 periods of a superlattice 42 in which Gax-xAs 40 and GaAs 41 are alternately stacked 42, 5 Si
X I Q "an-" containing n10 a A s
i3 was formed to have a thickness of 16 Onm.

After that, the n+ GaAs 13 where the gate part will be formed is selectively recessed using the photoresist 1~ as a mask, and then 10 parts of SiN is formed using photo-CVD, and SiN is deposited only on the n+ GaAs sidewalls by anisotropic dry etching. After that, add LaB522' as the gate metal.
Onm was deposited and the gate electrode was lift-off formed.

Next, the F atom was accelerated to 101 keV with ν pressure.
Ion implantation was performed at a dose of row 2, and 5iOz was 20On.
After the deposition of M, annealing was performed at 650° C. for 2 hours.

Next, source/drain salt Nu 20.

As No. 21, an alloy was formed using A.sub.G e/N.sub.i/A.sub.u.

In this example, F atoms were annealed at 650°C, but the superlattice 42 is easily broken at 400°C,
The heterojunction can also be disordered by time annealing. The disordered region is indicated by dotted lines 50.

Example 4 An example in which the present invention is applied to a heterojunction MIESFET is shown in No. 61d.

By MBE, undoped GaAs 1l is further deposited to a thickness of 0.3 μm on semi-insulating GaAs substrate 1o, and undoped Al2xG
at-xAs(x”0.3)48 0.2 μm, Si 3×1018an-3 containing n+GaAs13′ 1
0 part m, undoped A1xGaz-xAs (x~0
．． 3) 20 nm of 49 and 3×I of Sl
60nm of n+GaAs13 containing O"cu-3 was formed.Subsequently, 5iOz 48 & 30Onm CV
Gate ” using gate photoresist
114 parts of SiC2, n+GaAs L3 were selectively removed.

After that, turn on 5iN44 for 15 seconds from the optical CV D m
After Inn formation and backward dry etching, the photoresist was removed. Furthermore, after depositing 300 m of WSi22” on the entire surface,
A gate electrode was processed using gate photoresist. After that, the F ions were irradiated with an accelerating voltage dose I of 100 keV.
X 10 "an-2 was implanted, and annealing was performed at 650° C. for 2 hours using a CVDSiO2 cap to form SD electrodes 20.21.

The dotted line area indicated by 50 is the disordered area.

As mentioned above, in Examples 3 and 4, an example was shown in which disordering was formed using F ions, but the accelerating voltage is usually 30 keV ~
200keV, dose is 101zaI+-2~1
0 "an-", annealing conditions are often performed at 400°C to 700°C.

In addition to FJM, CQ, Br, I, At, etc. are also effective.

Example 5 This will be explained using FIG.

An undoped GaAs layer 112 (
n-type AQ GaAs, W 114 (thickness 3
An n+ GaAs layer 115 (F% 2000) doped with 8 x 1018 an-'' Si was successively formed. After that, the recess structure of the gate forming part and the n '' were formed using electron beam direct writing technology. G a As contact 1 to form a surface lattice structure. The grooves of the lattice structure extend in the <Oll> direction, and grooves with a depth of 600 mm were formed by wet etching using a resist as a mask.

Next, AQ was used as the gate electrode, and AuGe/Ni/Au were used as the source/drain electrodes, and each was formed by lift-off.

In the above embodiment, AuGaAs, which is a deuterium supply layer,
Between the layer 14 and the undoped GaAs layer 112, the number 1 is
Good heterogeneity can be obtained by providing a zero undoped AlGaAs spacer layer. An interface can be obtained and higher speed operation is possible.

Further, the lattice structure of the contact layer can be provided only in the source electrode contact layer or only in a part of the contact layer, and the effect is great.

Further, by partially adjusting the period of the lattice structure and the width and depth of the grooves, the current path can be controlled and the performance of the cable can be improved.

In the embodiment described above, 2 accumulated at the - pair of hetero interfaces
Although it is a field effect transistor that uses dimensional electron gas, the semiconductor layer structure below the contact layer can have any structure, and other compound semiconductors can be applied to the semiconductor materials forming each layer including the contact layer. It goes without saying that it can be done.

Example 6 An example in which an HBT and a GaAs MESFET are formed on the same substrate will be explained using FIG. 11.

On a semi-insulating GaAs1O substrate, 400 m layers of n+GaAs rII211 containing 3 x 10"cya-8 of Si and 300 layers of n-GaAs 12 containing Ix1013cn""δ of Sj were formed by MBE (molecular beam epitaxy). m.

Be 5 x 101δQl! -8 containing p+GaA
s213 to 1100n, undoped (p-: ~10
”am-δ level) A Q-Ga knee xA s (x
”0.3) 214 to 1100n undoped GaAs21
5 was formed to a thickness of 200 nrn (FIG. 11(a)).

After forming 500 m layers of 5iO2240 on the entire surface using thermal CVD, a window is opened to take out the base region using lithography. Using 5iOz240 as a mask, Mg ions 221 were implanted at a dose of 8×1014Ca11-'' at an acceleration voltage of 250keV, and then 5iOz was implanted at 20
After the entire surface of the 0 layer m was coated, Mg ions were activated using lamp annealing.

Subsequently, photoresist 241 and photo-CVD are applied inside it.
5iN242 was deposited by the method, and Si ions 220 were implanted at an acceleration voltage of 175 keV and a dose of 3XIO''-2, followed by conventional heat treatment to selectively form an emitter layer.

Thereafter, the formation of the base electrode, collector electrode, or FET portion was performed as shown in FIG. 10(b).

In this example, an npn type HBT was explained, but a pn type HBT was explained.
The present invention can be similarly applied to np-type HBTs.

In this way, the present invention uses an epitaxial technique such as MBE only for the base layer where controllability is most required, and forms the emitter or collector region by ion implantation.
Transistors, FETs, resistors SBD (Schottky barrier diodes), etc. can be easily formed in the substrate.

〔Effect of the invention〕

According to the present invention, in a 2DEG-FET, by making a steep heterojunction broad, for example by disordering a GaAs/AlGaAs heterojunction, except for the part where two-dimensional carriers are accumulated, The parasitic resistance Rs+r is extremely small, and 2 D E
In G-HBT, a semiconductor device with extremely low parasitic base resistance can be obtained.

Furthermore, according to the present invention, the contact resistance between the source electrode and the contact layer and the parasitic resistance between the gate and source electrodes can be significantly reduced, and the mutual conductance of the device can be reduced by 3 to 4 compared to the conventional one.
The percentage has improved.

Furthermore, according to the present invention, since the emitter region is formed by ion implantation, the parasitic capacitance between the emitter and the base can be extremely reduced, and the GaAs MESFET can be extremely easily formed in the undoped layer formed on the top of the base layer. , it becomes possible to easily form multiple I-I B Ts and FETs on the same substrate.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a transistor and its energy band diagram for explaining the present invention in detail, and Figure 2 is a diagram of a conventional transistor.
ET cross-sectional view and energy band diagram. Figure 3 is a cross-sectional view of an embodiment in which the present invention is applied to 2DEG-HBT. Figure 4 is a cross-sectional view in the case where the present invention is applied to 2DEB-HB 'I''. Figure 5 is a diagram for explaining Example 3, and Figure 6 is Example 4.
FIG. 7 is a cross-sectional view of Example 5 of the present invention (A,
FIG. 8 is a cross-sectional view of a known example, FIG. 9 is a cross-sectional view of an example in which an improvement is added to the known example shown in FIG. 8, FIG. 10 is a cross-sectional structural diagram of the present invention, and FIG. 11 is an embodiment. 6 is a process sectional view of step 6. 11-...and-bu Ga As, 12-n-
A Q GaAs, 1, 2- n-type A Q x Gai
-xA s , 12' ・=A Q In formation is gr
adad AlGaAs, 13-n+GaAs, 1
4 ・2 D E G, 16.18-p+GaAs
, 17...PEAΩGaAs -20,21...
Source/drain electrode, 22... Gate electrode, 23.
...Base electrode. 24...Collector electrode, 25...Emitter electrode,
111°121.131 = semi-insulating GaAs substrate, 1
12゜122.132--Undoped GaAs layer, 1
．． 13゜123.133...Two-dimensional electron gas, 114
, 124゜134- n-type AQ GaAs layer, 11
5,135-...n medium-sized GaAs contact layer, 116
, 125° 136...source electrode, 117, 126,
137...Drain electrode, 118, 127, 128.
...Gate electrode, 139,140...Electron flow path, 2
10...Substrate, 211-n+GaAs, 212-n
-GaAs. 213-P+GaAs, 214-undoped A Q
GaAs, 215-... undoped GaAs,
220...Si ion, 221...Mg ion 5
240... whisper 2121 /l finished, ni-7''kesu As 12 Ushijiku Atj Eva S 73 type 6 Ku, 4s /4 2.k ahead electron η゛'S 25 death 3 Figure 75 Takumi z6 Iman 〉 3o BoL Shinst'fJ 3 Fig. 22' Spring 9-machi-cho [Kobana-L Menono L Fig. 5 Fig. 2 Fig. 13 Side 6a-A5 4g, i', A-71
・1) z (jLt=tlsj3 "mutual" frAs 42 supercase χ 7 7 wealth /ρ Figure Z/Z %-qaAs

Claims (1)

[Claims] 1. Having a heterojunction between a semiconductor layer (I) that does not substantially contain impurities and another semiconductor layer (II) made of a mixed crystal,
an electrode for controlling two-dimensional carriers induced at the heterojunction interface; and at least one electrode electrically connected to the two-dimensional carriers.
In a semiconductor device having more than one electrode, the mixed crystal of the semiconductor layer (II) is spatially modulated, except for the region where the two-dimensional carrier is controlled and its vicinity, and the semiconductor layer (II) is continuously modulated. ) A semiconductor device characterized by being connected to. 2. In the semiconductor device according to claim 1, the semiconductor layer (I) is made of GaAs, the semiconductor layer (II) is made of AlGaAs, and an electrode for controlling the two-dimensional carrier and its surroundings are provided. 1. A semiconductor device characterized in that a heterojunction interface other than that of the semiconductor device is disordered. 3. A patent characterized in that neutralized atoms are ion-implanted into the disordered region, or atoms having a conductivity opposite to that of the region controlling the two-dimensional carrier are ion-implanted. A semiconductor device according to claim 1. 4. A semiconductor device characterized in that it is a field effect transistor comprising a semiconductor contact layer for an ohmic electrode with a lattice structure whose surface is modulated. 5. The semiconductor according to claim 4, wherein in the surface lattice structure formed in the semiconductor contact layer for ohmic electrode, the angle between the cross-sectional side wall of the recess and the bottom surface is 90 degrees or more. Device. 6. The ohmic electrode contact layer is made of n-type GaA
It consists of an s layer, and the dopant concentration is 1×10^1^7
cm^-^3 or more and 1 x 10^2^0 cm^-^3 or less, the thickness of the contact layer is 500 Å or more, and the depth of the recess formed in the contact layer is equal to or greater than the thickness of the contact layer. 5. The semiconductor device according to claim 4, wherein the semiconductor device has a diameter of between 20% and 80%. 7. The semiconductor contact layer for the ohmic electrode is made of an n-type GaAs layer, the main surface is the (100) plane, and the direction in which the grooves of the lattice structure extend is the <0@1@1> direction. A semiconductor device according to claim 4 characterized by: 8. In a bipolar transistor having an emitter layer, a base layer, and a collector layer in which at least one of the emitter layer and the collector layer is epitaxially grown without substantially containing impurities, at least one of the emitter region and the collector region is in the substrate. A semiconductor device characterized by having a structure selectively doped with impurities.