JPS6211512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FET (field effect transistor) integrated circuit, particularly an integrated circuit using a normally-off type FET.

Many FET integrated circuits use normally-off type FETs, but in such integrated circuits, the inverter is of a resistive load type as shown in FIG. 1A. In this diagram, 1 is the resistive load, 2 is the FET, IN is the input terminal,
OUT is the output end, and _VDD is the power supply. To briefly explain the operation of this circuit, the resistance 1 _is
A voltage is applied between the source and drain of FET2 through the resistor 1, and when an H level signal is input from the input terminal IN to the gate of FET2, FET2 turns on and current flows through the resistor 1 to the source and drain. Therefore, the potential at the output terminal OUT becomes L level. Conversely, the signal applied to the input terminal IN is L.
When the level is reached, FET2 turns off and the output terminal
The potential of OUT rises to the H level potential of power supply _VDD . That is, an inverter operation is performed. Figure 2 is
It is a graph showing the current-voltage characteristics (IV characteristics) of FET2 etc. In the figure, 5 indicates the load line, and 6 indicates the load line.
7 shows the IV characteristics when the gate-to-source voltage V _GS of FET2 is 0.6V, and 7 shows the IV characteristics when V _GS is 0V, and _ID is the drain current, V _DS
indicates the drain-source voltage. When the input signal is at H level, e.g. V _GS = 0.6V, the operating point is P _1. When the input signal is at L level, e.g. V _GS = 0 V, the operating point is P ₂ , and the L level voltage from terminal OUT is V ₁ . and _V2 , an H level voltage is output. FIG. 1B shows a planar pattern of a device that realizes the device shown in FIG.

By the way, FET inverters that use a resistive load have the disadvantage of slow operating speed (switching speed), and to speed up this, a third load resistor is used instead of the first load resistor.
It is preferable to use an active load 8 as shown in the figure. However, in order to short-circuit the gate and source of the FET to create an active load, that is, a constant current source 8, the FET 8 must be a normally-on type, and if it is a normally-off type, it will be turned off and the circuit will not operate. However, normally off type
In an integrated circuit using FETs, if only the load portion is made of a normally-on type FET, it is necessary to increase the thickness of the epitaxial layer in that portion, for example, which unnecessarily complicates the manufacturing process. Note that FIG. 3B shows a plane pattern of a device that realizes A in the same figure, and 9, 10, and 11 are FET8.
drain, gate, and source electrodes. Figure 4 shows the operating characteristics of Figure 3, where 14 is the load line, 15 is the gate voltage of FET1 when the gate voltage _VGS is +0.6V, and 16 is the same when _{the VGS} is 0V.
Shows _DS characteristics. P ₁ and P ₂ are the operating points.

Therefore, the present invention aims to achieve the same constant current characteristics as a normally-on FET with a short circuit between the gate and source using a resistive element, and to obtain a high-speed inverter without complicating the manufacturing process.
As is known, when a high electric field is applied to gallium arsenide (GaAs), the carrier drift velocity exhibits a saturation phenomenon. Therefore, by shortening the distance between the electrodes of the GaAs layer that realizes the resistance element and applying a high electric field that saturates the carrier drift velocity, the voltage-current characteristic of the resistance element becomes similar to curve 14 in Figure 4. It will exhibit constant current characteristics. The present invention attempts to use such a resistive element as a load resistor of an inverter, and is characterized by: an integrated circuit including a circuit consisting of a field effect transistor and a load resistor connected in series with the field effect transistor;
The load resistor is composed of a semiconductor layer and a pair of ohmic electrodes attached to it, and the distance between the electrodes is defined as the length of the interelectrode semiconductor layer over which a high electric field greater than the electric field at which the carrier drift velocity is saturated is applied to the load resistor. The reason is that it has constant current characteristics. Next, the present invention will be explained in detail based on examples.

FIG. 5A is an equivalent circuit diagram of an embodiment of the present invention;
FIG. B is an explanatory diagram showing a planar pattern of a device realizing the circuit. In the figure, 17 is the load resistance, 2 is
These are FETs, and these constitute an inverter. The resistor 17 is constructed by attaching ohmic electrodes 18 and 19 to a GaAs semiconductor layer, and the distance L ₂ between these electrodes is sufficiently shorter than L ₁ in FIG. 1, so that the carrier drift velocity is saturated in the GaAs semiconductor. Apply a high electric field of at least 3KV/cm (approx. 3KV/cm for GaAs). To give a numerical example, W ₂
= 10 μm, L ₂ = 1 μm, and when V _DD =1 V, the electric field applied to the resistor 17 is 10 KV/cm. In addition
The width _W1 of FET2 is 20 μm. This is because the FET carrier drift speed is saturated in high electric fields and I
_{The D} - V _DS characteristic shows a saturation characteristic as shown in curve 5 in Figure 4, but the load line must be below this (if it is like the dotted line in Figure 4, there will be a difference in the output at L and H times. ), so the gate width of FET2 W ₁
The width of the resistance element 17 is made smaller. Under these conditions, the resistor 17 exhibits constant current characteristics, whereas the resistor 17 in FIG. 1 has a sufficiently large _L1 .
Although they are the same GaAs semiconductor resistors, they exhibit linear characteristics.

The connection method and operation of _this inverter are almost the same as those shown in FIG. ' is connected to ground, the gate electrode 4 of FET2 is the input terminal IN, the connection point between the load resistor 17 and the drain of FET2 is the output terminal OUT, and when the input voltage is H or L level voltage, L or H level produces an output of However, since the resistance element 17 has constant current characteristics, the operating speed of this inverter is high.

FIG. 6 shows another embodiment, in which the resistance element 17 is connected to the source side and the FET 2 is operated as a source follower. In this case as well, if a constant current characteristic is used for the element 17 instead of a linear resistance element, the operating speed will be improved.

FIG. 7 is a diagram showing the manufacturing process of the integrated circuit of the present invention. In the figure, 32 is an insulating GaAs substrate, 31, 3
1' is the n-type epitaxially grown on the substrate.
GaAs semiconductor layer, 33 to 36 are ohmic electrodes,
37 is a shotgun type gate electrode. Next, to briefly explain the manufacturing process, first, on the substrate 32,
GaAs layers 31, 31' are formed by epitaxial growth and patterning (FIG. 71), and ohmic electrodes 33 are formed on these semiconductor layers 31, 31'.
~ Install 36. (Fig. 7 2) Electrodes 35, 36
constitutes the resistor 17 together with the semiconductor layer 31', and therefore the distance between the electrodes 35 and 36 is made sufficiently small. The n-type impurity concentration of the semiconductor layers 31 and 31' is 1
×10 ¹⁷ cm ^-3 and the thickness is approximately 0.1 μm.
Attaching an aluminum electrode 37 to the semiconductor layer 31,
This is used as a gate electrode. (FIG. 7 3) Even if no voltage is applied to the semiconductor layer near this shotgun type gate electrode 37, the same state as if a voltage of about 0.8V was applied, the depletion layer expands to a depth of about 0.1 μm. The thick semiconductor layer will pinch off, so the FET will be normally off.

The phenomenon in which the carrier drift speed becomes saturated is
It is noticeable in compound semiconductors such as GaAs, but can also be seen in semiconductors such as silicon.
FIG. 8 shows the relationship between electric field E and carrier velocity v of gallium arsenide (GaAs) and silicon (Si), where 40 in the figure is the vE characteristic of GaAs and 41 is that of Si. Therefore, the resistance element 17 used in the present invention
can also be manufactured using silicon.

As described in detail above, according to the present invention, it is possible to obtain a FET integrated circuit which has a high operating speed and whose manufacturing process is not complicated, which is extremely beneficial.

[Brief explanation of the drawing]

FIG. 1A is an equivalent circuit diagram of a conventional resistive load inverter, and FIG. 1B is an explanatory diagram showing its plane pattern.
Figure 2 is a graph showing the IV characteristics of the same circuit, and Figure 3 is a graph showing the IV characteristics of the same circuit.
Figure A is an equivalent circuit diagram of an inverter using a FET load, Figure B is an explanatory diagram of its plane pattern, Figure 4 is a graph showing the IV characteristics of the same circuit, and Figure 5 A is an embodiment of the present invention. FIG. 6A is an equivalent circuit diagram of another embodiment of the present invention, FIG. 6B is an explanatory diagram of the plane pattern, and FIGS. 7 1 to 3 8 is a longitudinal sectional view showing the manufacturing process of the integrated circuit of the present invention, and FIG. 8 is a graph showing the relationship between electric field and carrier velocity. In the drawing, 2 is a field effect transistor, 17 is a load resistor, 31, 31' are semiconductor layers, 33, 34, 3
5 and 36 are ohmic electrodes, 37 is a shot key
This is the gate electrode.

Claims (1)

[Claims] 1 In an integrated circuit comprising a circuit consisting of a field effect transistor and a load resistor connected in series thereto, the load resistor is composed of a semiconductor layer and a pair of ohmic electrodes attached to it, and the distance between the electrodes is determined by the carrier drift speed. 1. A field effect transistor integrated circuit characterized in that the load resistor has a constant current characteristic as long as a high electric field greater than the electric field at which the interelectrode semiconductor layer is applied to the interelectrode semiconductor layer.