JPS58103174A - Manufacture of junction type field effect transistor - Google Patents

Abstract

PURPOSE:To make noises low, by forming a source and a drain by ion implantation with an Si3N4 film as a mask, performing side etching of polysilicon which is to become a gate diffusing source at the lower part of the Si3N4 film, reducing the gate width, enlarging transmission conductance, directly provoding an electrode on the gate, thereby reducing the gate resistance. CONSTITUTION:An oxide film 102 and an N type channel region 103 are formed in a P type substrate 101. Then, the polysilicon 104 including P type impurities is deposited on the entire surface. With the Si3N4 film 105 as a mask, the polysilicon 104 is etched. With the Si3N4 film 105 and an oxide film 102 as masks, a source region 106 and adrain region 107 are formed by the ion implantation. With the polysilicon 104 as the diffusing source, heat treatment is performed in an oxidizing atmosphere, and a gate region 108 is formed. The Si3N4 film 105 is removed, and contact windows for the source region and the drain region are provided. Then the gate electrode 109, the source electrode 110, and the drain electrode 111 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a junction field effect transistor (hereinafter referred to as J-FET) with high integration and high transfer conductance.
The present invention relates to a manufacturing method.

Since J-FETs have characteristics such as square-law characteristics and low noise characteristics, they have been widely used in various fields including the acoustic field. Recently, it has begun to be used in the video field, and therefore higher frequencies are required. In order to achieve higher frequencies, it is necessary to reduce the occupied area in order to reduce the capacitance. Furthermore, in order to improve the low noise characteristics, it is necessary to increase the transfer coductance.

Next, a conventional method for manufacturing an n-channel type J-FET will be explained based on FIG. An oxide film 2 is formed on a p-type substrate 1, and layer resistors 3 to 5 are formed in desired areas by photo-etching and photo-etching.
An n-type channel region 3 with a diffusion depth of 0.5 to 1.0 μm and a diffusion depth of 0.5 to 1.0 μm is formed (FIG. 1(a)).

Next, an oxide film 4 is formed on the n-type channel region 3, and an n-type source region 5 and drain region 6 are formed by photoetching (FIG. 1(b)).

Further, after forming the oxide film 7, a highly concentrated p-type f-) region 8 (layer resistance 10 to several 100 Ω/hole, diffusion depth 0.05 to 0.3 μm) is formed by photoetching. 1
Figure (C)). In FIG. 1(C), n-channel region 3
When the p-type gate region 8 and the p-type gate region 8 are reverse biased, a depletion layer spreads to the n-type channel region 3, and the current flowing from the drain region 5 to the source region 6 is controlled. This J-F
In ET, a high concentration p shadow region 8 and an n type source region 5
Since the high-density n-shade region and the drain region 6 are not directly connected to each other, low frequency noise and popcorn noise are small.

However, in this J-FET, the r-t width W is limited by the mask size, so the transfer conductance cannot be made very large. First, in order to reduce noise, the dirt region 8, the source region 5, and the drain region 6 are separated from each other due to mask alignment, and therefore, a margin for mask alignment is required, which prevents high integration. Furthermore, if an attempt is made to increase the transfer conductance, the dart width W must be reduced, and as a result, the dart resistance is large, resulting in an increase in low frequency noise.

The present invention has been made in view of the above drawbacks, and its purpose is to form source drains by ion implantation using an oxide film as a mask, and to form source drains by side-etching impurities using the oxide film as a mask. By forming polysilicon as a diffusion source, the source and drain are separated from the dirt, and by making the dirt size smaller than the mask, the transfer conductance is increased, and the electrode is directly connected to the polysilicon to reduce the date resistance. An object of the present invention is to provide a method for manufacturing a junction field effect transistor that can reduce noise.

Next, a method for manufacturing a junction field effect transistor according to the present invention will be explained with reference to FIG. 2, taking an n-type channel J-FET as an example. An oxide film 102 is formed on a p-type substrate 101, and layer resistances 3 to 3 are formed in desired regions by photoetching.
5, an n-type channel region 103 with a resistance of Ω/hole and a diffusion depth of 0.5 to 1.0 μm is formed (FIG. 2(a)). Next, polysilicon 104 containing p-type impurities is deposited on the entire surface, and an S13N4 film 105 is further formed in a desired region above.
(Figure 2(b)). Thereafter, the polysilicon 105 is etched using the Si isN 4 film 105 as a mask, and side etching is performed so as to go around the edges of the Si, N 4 film 105)'5i6N 4 film 105 and oxide film 102
A source region 106 and a drain region 107 are formed by ion implantation using as a mask (FIG. 2(C)). Then, heat treatment is performed in an oxidizing atmosphere using polysilicon 104 as a diffusion source, resulting in a layer resistance of 10 to several 100 Ω/hole and a diffusion depth of 0.
．． A dirt region 108 with a thickness of 0.5 to 0.3 μm is formed (FIG. 2(d)). After removing the +1 and 5i3N4 electrodes 105 and opening contact windows in the source and drain regions, a dirt electrode 109 and a source electrode 110 are formed. and drain electrode ill is formed (Fig. 2(e))
.

This embodiment has the following advantages.

i) r' - length W (Fig. 2 (d)) car r
Since the frame dimension V (Fig. 2 (d)) can also be made smaller,
Large transfer conductance.

11) Source region 106 and drain region 107 and r-
Since the distance from the contact area 108 is separated by side etching, a mask margin between this area is not required and high integration can be achieved. ・Since the 110 gate contact is made by self-line, direct contact can be made even if the dart length is small, so the dart resistance is reduced. can be lowered, resulting in lower noise.

For example, dart length 2 μm (mask dimension), dart width 70
In the case of a J-FET in which 4 μm cells are arranged in parallel, the conventional manufacturing method has a transfer conductance of 13 m, a dart resistance of 1450, and an input equivalent noise of 1.9 nV15. If so, set the side etch amount to 0.
．． If it is 5 μm, the dart length is 1 μm, the transfer conductance is 26 mU, the dart resistance is approximately OΩ, the input conversion noise is 0.8 nV/, and the transfer conductance is doubled and the input conversion noise is 1/2. 4, and an element with very excellent characteristics can be obtained.

Furthermore, 1v) Source region lO6, drain region 1 with the same mask
07 and the dirt region 108, the number of masks can be reduced by one.

(2) Since the dirt electrode is formed through the polysilicon 104, penetration of the electrode does not occur even if the diffusion bed in the dirt region is very shallow as in this embodiment.

Furthermore, in this embodiment, when the n-type channel region 103 is formed by ion implantation, the defect layer formed on the surface of the n-type channel region 103 by ion implantation is removed when side etching the polysilicon. , it is possible to realize an element with less noise.

As described above, the present invention has a structure in which 5
The source and drain regions are formed by ion implantation using the t3N4 film as a mask, and the polysilicon serving as a diffusion source for the date region under the 813N4 film is side-etched to reduce the gate width, increase the transfer conductance, and increase the date region. Place an electrode directly on top of f-
This method has an excellent effect in that a J-FET with lower resistance and lower noise can be manufactured through a simple process, and will greatly contribute to the realization of a high-precision, low-cost J-FET.

[Brief explanation of the drawing]

Figures 1 (,) to (C) are cross-sectional views showing the conventional J-FET manufacturing method in order of process, and Figures 2 (,) to (,) are sectional views of the J-FET manufacturing method according to the present invention. FIG. 3 is a cross-sectional view showing one embodiment in the order of steps. DESCRIPTION OF SYMBOLS 1... P-type substrate, 2... Oxide film, 3... N channel region, 4... Oxide film, 5... Source region, 6...
...Drain region, 7...Oxide film, 8...High concentration p
Shadow region, 101...p-type substrate, 102... oxide film,
103...n channel region, 104...polysilicon containing p-type impurity, 105...Si3N4 film, 1
06...source region, 107...φ drain region, 1
08...Date area, 109...Dart power supply, 11
0... Source electrode, 111... Drain electrode. Figure 2 (0) (d)

Claims (2)

[Claims] (1) Place a first conductivity type on a desired area on a semiconductor substrate.
forming a region; depositing polysilicon containing impurities of the other conductivity type on the surface; forming an oxidation-resistant thin film portion in a region including at least a portion of the first region; masking the thin film portion; In this step, polysilicon containing impurities of the other conductivity type is removed, in which case the polysilicon containing impurities of the other conductivity type is removed, in such a way that it penetrates a little into the edge of the thin film part, and ion implantation is performed using the thin film part as a mask. forming a second region and a third region of a shape so as to be connected through the first region, diffusing the polysilicon in an oxidizing atmosphere using the polysilicon as a diffusion source, and forming a fourth diffusion region shallower than the first region; A method for manufacturing a junction field effect transistor comprising the steps of: forming a polysilicon layer; and removing the thin film portion and forming an electrode on top of the polysilicon. (2) The method for manufacturing a junction field effect transistor according to claim (1), wherein the first region of one conductivity type is formed by ion implantation.