JPS6299849A - Data converting device - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware by providing two registers, a byte position counter and an unpack switch to convert the data of a long bit byte into the data of a short bit byte for each byte. CONSTITUTION:Both registers 101 and 102 contain 9 bits respectively and data to be converted is supplied to the register 101 for each byte. While the data of the register 101 is transferred to the register 102 for each conversion of data. A byte position counter counts from 0 up to 8 obtained by subtracting 1 from the quotient 9 obtained by dividing the least common multiple 72 between 9 and 8 bits by 8 bits. Then the counter 103 is reset to 0. An unpack switch 104 has 9-way selecting functions and selects the data of 8-bit bytes, i.e., the desired result of conversion out of the outputs of both registers 101 and 102 and delivers it. A cable driver 105 sends said 8-bit byte data to a peripheral device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data conversion device used in an input/output channel of a data processing device, and more particularly to a conversion circuit for converting the bit length constituting one byte.

(Prior art) One byte consists of 9 bits (9-bit byte), one word consists of 4 bytes, and a central processing unit processes f''L data, or one byte consists of 8 bits (8-bit byte). There are various types of peripheral devices that perform processing in bytes.When connecting these devices and transferring data, it is necessary to convert 9-bit byte data into 8-bit byte data. Nine data conversion devices are required, each having a conversion circuit.

Conventionally, the following types of conversion devices have been known.

The first data conversion device does not use one bit of each byte of data sent from the central processing unit to the peripheral device, but discards unused bits in the input/output channel and sends the data to the peripheral device as an 8-bit byte. there were. In such a method, before sending data from the central processing unit to the peripheral device,
1) Not only was it necessary to convert the format so that it was not used, but the main storage area was wasted.

The second data conversion device improves the shortcomings of the first data conversion device, for example, in Japanese Patent Publication No. 54-31775 “
"Data mode conversion device". In Japanese Patent Publication No. 54-31775, a ninth, 40-bit register is provided to convert one word of data less than 36 bits (36-bit word data) into 8-bit byte data, and the first word is Register bits 0~
Set bit 35 to fetch four 8-bit bytes, set the second word to bits 36-40 and bits 0-31 of the 40-bit register, and set the conversion bits of the first word. and the remaining 4 bits (bits 32 to 36) of the data to extract five 8-bit bytes. This results in 8 bytes of 9-bit byte data (72 bits)? It can be converted into 9 bytes of 8-bit byte data (72 bits).

Such a data conversion device requires a large register of 40 bits, which requires unnecessary hardware.

(Problems to be Solved by the Invention) The first data conversion device based on the above-described technology requires pre-processing of data conversion by the central processing unit, which leads to a decrease in performance and further occupies the area of the main storage device. The object of the present invention is to convert the bytes of the length to be converted. Input data one byte at a time, temporarily hold the remaining bits of the input data after each conversion, and calculate the quotient obtained by dividing the least common multiple of the number of bits in the long byte and short byte by the number of bits in the short byte. Eliminates the above drawback by counting down to the value subtracted by 1, extracting the necessary bit Z according to the counted value, and generating a short byte, effectively generating short byte data from long byte data. The object of the present invention is to provide a data conversion device ff1 that is configured to be able to perform the following steps.

(Means for Solving the Problems) A data conversion device according to the present invention includes a first register and a second register.
The device is equipped with a register, a byte position counter, and an unpack inch register, and is configured so that long byte data can be input one byte at a time, converted into short byte data, and output.

The first register is for inputting long byte data to be converted one byte at a time.

The second register is for temporarily holding the remaining bits of the input data after conversion.

The byte position counter is 1? from the value of the quotient obtained by dividing the least common multiple of the number of bits of the long byte data and the short byte data by the number of bits of the short byte. : This is to count up to the deductible friend value.

The unback switch extracts the necessary bits from the output of the first register and the output of the second register according to the content value of the byte position counter, and extracts the short byte data χ.
It is for generating.

(Example) Next, what about the drawings of the invention? This will be explained in detail with reference to the following.

FIG. 1 is a block diagram illustrating an embodiment of a 9-bit byte to 8-bit byte data conversion device. In FIG. 1, 101 and 102 are n registers, 103
104 is an unback switch, and 105 is a cable driver.

FIG. 2 is an explanatory diagram showing a detailed bit arrangement of the unback switch 104 in FIG. 1.

In FIG. 1, register 101 is a 9-bit register (WRO), and the data to be converted is stored in register 101.
The 0 register 102 is a 9-bit register (WRI) 102, and the data in the register (WHO) 101 is transferred to the register (WRI) 102 every time data conversion is executed. . Byte position counter (BPO) 103! 72 bits, which is the least common multiple of 19 bits and 8 pits? It is a counter that counts from O and returns to O again, dividing by 8 pits and subtracting 1 from 9, which is the quotient, to 98. Unknown switch (U)
PX) 104 is an 8-bit unbanked switch with a 9-way selection field MEY, and according to the instruction of the byte position counter 103, the required conversion result is obtained from the output of the register (WRo) 101 and the output of the register (WRI) 102. This is a selector that selects and outputs 8-bit byte data. Cable driver 105 is the circuit that sends the 8-bit byte of data 7 resulting from the conversion to the peripheral device.

The unback switch (UPX) 104 is connected to the register (WRo) at byte position O, as shown in FIG.
The first 8 bits χ of the 9-bit byte are extracted from 101, and the remaining 1 bit is transferred from register (WRO) 101 to register (WRl) 102 at the first byte position and input to register (WRO) 101 as companion data. The next 8-bit byte is extracted by combining it with the 9-bit data of the next byte.

Thereafter, in the same way, a register (WRO) 101 that stores input n 9-bit byte data, a register (WB 1) 102 and t that stores the remaining bits χ of conversion, and according to instructions from the byte position counter 103, 8
Create bitbytes of data.

FIG. 3 is a timing chart showing the operation χ of the data conversion device shown in FIG.

Next, the operation of the data conversion apparatus shown in FIG. 1 will be explained using the timing chart Y of FIG. 3.

In FIG. 3, 9-bit byte data is continuously applied to a register (WRO) 101 from byte 0 to byte 7, and n1 byte position counter (BPO) 10
At a value of 3, for example at a timing of 8, data input is inhibited. This is because one additional 8-bit byte is generated in the process of data conversion between a 9-bit byte and an 8-bit byte. Register (WRl) 102
The contents of the register (WFLO) 101 are transferred to the unback switch 104 every time conversion is performed.
The FX data is temporarily held in the register (WRt) 102 and operates accordingly. Byte position counter (
BPO) 103 is reset to O when the Oth byte of 8-byte 9-bit byte data is input.After that, it counts up by +1 for each conversion.
Count up to 8, which is the number of 8-bit bytes to be converted.

FIG. 3 is an explanatory diagram showing how data is converted from a 9-bit byte to an 8-bit byte in the data conversion device shown in FIG.

In FIG. 3, as the byte position counter 103 counts up, the contents of the register (WRO) 101 and the register (WRI) 102 are transferred from the unback switch (UPX) 104 to data WD i (i −0
The output pattern is shown as 7) to 7).

The output W D i (i
= 0 to 7) is the unpunk switch (UPX) in Figure 1.
) 104, and one byte of 8-bit byte data is output for each conversion.

FIG. 4 is a block diagram showing an embodiment of a data processing device to which the present invention is applied. In FIG. 4, 401 is a main storage device, 402 is a system control device, 403 is an arithmetic processing unit, 404 is an input/output processing device, 405 is an input/output channel, 406 is a peripheral control device, and 407 is a peripheral device.

In FIG. 4, the number inside 0 indicates the number of bits that are the unit of processing; 36 bits means one word consisting of 4 bytes of 9 bits, and 8 bits is 1 byte of 8 bits.

In FIG. 4, the data conversion device shown in FIG. 1 is mounted on an input/output channel 405.

The main storage device 401 is for storing programs and processing data. The system control device 402 is a device that controls the access bus Z of the main storage device 401 by the arithmetic processing device 403 and the input/output processing device 404. The arithmetic processing unit 403 executes a program stored in the main storage device 401 and issues an input/output instruction χ at the same time as the input/output processing unit 404 according to instructions from the program. The input/output processing device 404 performs arithmetic processing 1t403
Data is transferred between the main storage device 401 and the peripheral device 406 according to input/output commands issued from the main storage device 401 and the peripheral device 406. It is a device that executes. The input/output channel 405 is connected to the input/output processing device 404
This is the same data transfer port as the peripheral device 406. In the present invention, an interface is provided inside the input/output channel 405, and the internal interface is the main storage 405.
The data of 36 bits 1 word - 9 pit bytes x 4 bytes read from 01 is converted from 9 bit bytes to 8 bit bytes and then sent to the peripheral device 406, which has a width of tth 8 bits.

The peripheral control device 406 is connected to a plurality of peripheral devices 407 and has an input/output channel 40 of the one-person output control device 404.
This is a device that controls data transfer between 8-bit and 8-bit bytes. Peripheral devices 307 include magnetic disks, magnetic tapes, card readers, table printing devices, and the like.

FIG. 5 is an explanatory diagram showing data conversion performed by the data processing apparatus shown in FIG. 4.

The number of bits is converted from a 9-bit byte to an 8-bit byte as shown in FIG.
It converts bit bytes into 9 bytes of 8 bit bytes.

(Effects of the Invention) As explained above and based on the above, the present invention converts long bit byte data into short byte data one byte at a time.
The amount of hardware is small, it is inexpensive, and the number of input/output bits can be reduced, making it easy to implement into LSI.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a 9-bit byte to 8-bit byte data conversion device according to the present invention. FIG. FIG. 2 is an explanatory diagram showing detailed bit allocation of the unback switch shown in FIG. 1. FIG. 3 is an explanatory diagram showing how data is converted from a 9-bit byte to an 8-bit byte in the data conversion device according to the first factor. FIG. 4 is a block diagram showing an embodiment of a nine-data processing device in which the data conversion device configured as shown in FIG. 1 is mounted on an input/output channel. FIG. 5 is an explanatory diagram showing a pattern of data conversion by the data processing device shown in FIG. 4. 101, 102-e・Register 103...Byte position counter 104...Unback switch 105...Cable driver 401...Main storage device 402...System control device 403...Arithmetic processing unit 404... ... Input/output processing device 405 ... Input/output channel 406 ... Peripheral control device 407 ... Peripheral device patent applicant Nippon'Seiki Co., Ltd. Agent Patent attorney Inoro Jusai 1 Figure Twpa-*D7 ) 22 figures 4 figures 5 figures

Claims (1)

[Claims] A first register for inputting long byte data to be converted one byte at a time, and a second register for temporarily holding conversion remaining bits of the input data each time the conversion is performed.
and a byte position counter for counting up to a value obtained by subtracting 1 from the quotient obtained by dividing the least common multiple of the number of bits of the long byte data and the short byte data by the number of bits of the short byte. , an unback switch for generating the short byte data by extracting necessary bits from the output of the first register and the output of the second register according to the content value of the byte position counter. . A data conversion device, characterized in that it is configured to be able to input the long byte data one byte at a time, convert it into the short byte data, and output the short byte data.