JPH02285418A - Data converting device - Google Patents

Abstract

PURPOSE:To convert data without requiring preprocessing nor a large-scale circuit for the data conversion by leading out short-byte data from an OR means while inputting long-byte data to a former-half input register, byte by byte. CONSTITUTION:While the long-byte data is inputted to the input register 101, a byte by byte, the short-byte data is led out from the OR means 108. Namely, the long-bit-byte data is inputted, bit by bit, and the before-conversion remaining bits of the input data are held in a register 104 temporarily before conversion is performed; and the respective bytes of the input data are shifted by the difference in the number of bits between the long and short bytes in order and the shift contents and the bits held in the register 104 are combined to perform conversion to a short bytes. Consequently, the quantity of hardware is small, the cost is reduced, and the number of input/output bits is decreased, so LSI-implementation is facilitated.

Description

TECHNICAL FIELD The present invention relates to a data conversion device used in a human output channel of a data processing device, and more particularly to a data conversion device for converting bits constituting one byte of data.

Conventional technology A central processing unit that processes data in which 1 byte consists of 9 bytes (9-bit byte) and 1 word consists of 4 bytes, or 1 byte consists of 8 bits (8-bit byte), and processing is performed in units of bytes. There are various data formats for peripheral devices that perform . When these devices are connected to each other to transfer data, a data conversion device is required that includes a conversion circuit that converts 9-bit byte data into 8-bit byte data.

Conventionally, the following types of conversion devices are known. The first data conversion device does not use one bit of each byte of data sent from the central processing unit to the peripheral device, but discards unused bits in the input/output channel and sends the data to the peripheral device as an 8-bit byte. be. In such a system, before sending data from the central processing unit to the peripheral device, not only is it necessary to convert the format so that one bit is not used, but also the main storage area is wasted.

The second data conversion device improves on the shortcomings of the first data conversion device.
This is disclosed in Publication No. 5 "Data Mode Conversion Device". In this device, in order to convert one word of data consisting of 36 bits (36-bit word data) into 8-bit byte data, a 40-bit register is provided, and the first word is converted from bits 0 to 8 of the register. Set bit 35 to fetch four 8-bit bytes, set the second word to bits 36 to 40 and bits 0 to 31 of the 40-bit register, and retrieve the remaining conversion bits of the first word draw. 4 bits of
(bits 32-36) to extract five 8-bit bytes. As a result, 8 bytes of 9-bit byte data (72 bits) can be converted into 9 bytes of 8-bit byte data (72 bits).

Such a data conversion device requires a register as large as 40 bits, which requires unnecessary hardware.

The first data conversion device according to the prior art described above requires data conversion pre-processing by the central processing unit, which has the disadvantage of causing a corresponding decrease in performance and wasting the area of the main storage device.

Furthermore, the second data conversion device has the disadvantage that it requires a large-scale circuit and is expensive.

OBJECTS OF THE INVENTION An object of the present invention is to provide a data conversion device that can perform data conversion processing without requiring preprocessing or large-scale circuits for data conversion.

Structure of the Invention According to the present invention, there is provided a data conversion device for converting long byte data into short byte data, the input register storing the inputted long byte data one byte at a time, and the input register storing the long byte data and the short byte data. a counting means whose counting contents change cyclically and sequentially by the number of bits of the short byte data divided by the least common multiple of the number of bits of the short byte data;
Sequentially shifting the contents stored in the input register by the difference between the numbers of both bits and setting an empty bit area to "0";
a selection means for selectively outputting one of these shift data according to the contents of the counting means; and a holding means for holding lower bits equal to the number of bits of the short bit data among the outputs of the selection means. and an OR means for outputting a logical sum of upper bits equal to the number of bits of the short bit data out of the output of the selection means and the holding output of the holding means, There is obtained a data conversion device characterized in that the short byte data is derived from the logical sum means while inputting one byte to a register one byte at a time.

Embodiments Examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a data conversion device from 9-bit bytes to 8-bit bytes. In this embodiment, it is assumed that data conversion as shown in FIG. 4 is performed.

In Fig. 1, iot, 104°1!19 is a register, IO2 is a byte position counter, 103 is an unback switch, and 105 and 106 are exclusive ORs (exclusive OR).
slve-or) circuit, 106 is a flip-flop, 1
08 is a logical sum (OR) circuit.

In FIG. 1, the first register 101 is a 9-bit register (REGI), and data to be converted is input to the first register 101 one byte at a time. The byte position counter 102 counts from 9 to 1, which is the quotient obtained by dividing 72 bits, which is the least common multiple of 9 bits and 8 bits, by 8 bits.
Count from "0" until 8 after subtracting "0" again.
This is a counter that returns to .

The unback switch 103 has a 9-way selection function, has a 10-bit input (9 data bits, 1 parity bit), and a 17-bit output (16 data bits, 1 parity bit). According to the instructions of the counter 102, the unback switch 10
As shown in the detailed bits in the figure of 3, it has a function of right-shifting by 1, which is the difference between 9 bits and 8 bits, and outputting "0" to the output empty area. In addition, the unback switch 103 outputs the parity bit as it is (the parity bit is particularly
It is a selector that does not need to be taken into the
Byte position counter 102
The byte contents at the position decoded by the decoder 110 are alternatively output.

The second register 104 temporarily holds the 9th to 16th bits, which are the lower 8 bits of the selected output of the unback switch 103, every time data conversion is performed.
This is a bit register (REG2). The exclusive OR circuits 105 and 107 are circuits that predict (pre-a-1) the parity bit after data conversion, and the flip-flop 10B temporarily stores information for the next conversion data following the conversion data being executed. It is for holding.

The OR circuit 108 performs the OR operation between bits 1 to 8, which are the upper 8 bits of the selected output of the unback switch 103, and the output (8-bit data) of the second register 104, and uses the data bits of the conversion result. Generate some 8 bits. The exclusive OR circuit 107 is for generating a parity bit of the conversion result. The third register 109 has 9 bits (8 bits of data, 8 bits of data,
This is a 1-bit parity register.

A first register 101 stores input 9-bit byte data, and an unback switch 103 during the conversion process.
A second register 104 temporarily stores a portion of the output of
8 according to the instruction of the byte position counter 102.
It creates bit bytes of data.

FIG. 2 is a timing chart showing the operation of the data conversion device shown in FIG. The operation of the data conversion apparatus shown in FIG. 1 will be explained using the timing chart of FIG. 2.

In FIG. 2, the register (REGI) 101 in FIG.
contains 9-bit bytes of data from byte 0 to byte 7.
When the value of the byte position counter 102 is 8, for example, data input is inhibited. This is because, as shown in Figure 4, in the process of data conversion between a 9-bit byte and an 8-bit byte, the 8-bit byte becomes 1.
This is because an extra byte is generated.

The second register (REG2) 104 operates to temporarily hold a part of the selected output of the unback switch 103 (lower 8 bits, corresponding to the remaining bits shifted to the right) every time a conversion is performed. . Paitbojishi Sun Counter 1
02 is reset when the Oth byte of 8-byte 9-bit byte data is input, and after that, it is counted up by +1 every time it is converted, until it reaches 8, which is the number of 8-bit bytes to be converted. Ru. The third register (REG3) 109 stores 8-bit byte data as a conversion result.

FIG. 2 is an explanatory diagram showing how data is converted from a 9-bit byte to an 8-bit byte in the data converter shown in FIG. In FIG. 2, as the byte position counter 102 counts up, the first register (R
The contents of EGI) 101 are input to the unback switch 103, the output of the unback switch 103 is temporarily held in the second register (REG2) 104, and the 8-bit byte is stored as the conversion result in the third register (REG3) 109. This shows how the data is output.

FIG. 3 is a block diagram showing an embodiment of a data processing device to which the present invention is applied. In FIG. 3, 301 is a main storage device, 302 is a system control device, 303 is an arithmetic processing unit, 304 is an input/output processing device, 305 is an input/output channel, 30B is a peripheral control device, and 307 is a peripheral device.

In FIG. 3, the numbers in parentheses indicate the number of bits that are the unit of processing; 36 bits means 1 word made up of 4 bytes of 9 bits, and 8 bits means 1 byte of 8 bits.

In FIG. 3, the input/output channel 305 is equipped with the data conversion device shown in FIG. Main storage device 30
1 is for storing programs and processing data. The system control device 302 is a device that controls the access bus of the main storage device 301 by the arithmetic processing device 303 and the input/output processing device 304.

The arithmetic processing unit 303 executes a program stored in the main storage device 301 and issues input/output commands to the input/output processing unit 304 according to instructions from the program. The input/output processing device 304 is the arithmetic processing device 303
This is a device that executes data transfer between the main storage device 301 and the peripheral device 30B according to input/output commands issued from the main storage device 301.

The input/output channel 305 is a data transfer port from the input/output processing device 304 to the peripheral device 30B.

In the present invention, an interface is provided inside the human output channel 305, and the internal interface is a 36-bit 1 word read from the main memory 301 - 9 bit bytes x
It has a width of 8 bits for converting 4 bytes of data from a 9 bit byte to an 8 bit byte and then sending it to the peripheral device 306.

The peripheral control device 306 is connected to a plurality of peripheral devices 307 and has a human output channel 305 of the input/output processing device 304.
It is a device that controls data transfer between 8-bit bytes and 8-bit bytes. Peripheral devices 307 include magnetic disks, magnetic tapes, card readers, printing devices, and the like.

FIG. 4 is an explanatory diagram showing data conversion by the data processing device shown in FIG. 3. Bit number conversion from a 9-bit byte to an 8-bit byte is performed as shown in FIG. 4, and is the least common multiple of 9 bits and 8 bits. 7
This converts 2 bits from 8 bytes of 9 bits to 9 bytes of 8 bits.

Effects of the Invention As described above, according to the present invention, long bit byte data is input bit by bit, and the remaining bits of the input data are temporarily held in a register each time conversion is performed. Since each byte is sequentially shifted by the difference in the number of bits between the long and short bytes, and the shifted contents are combined with the bits held in the register to convert it into a short byte, the amount of hardware is small, the cost is low, and the input/output Since the number of bits is reduced, it has the effect of being easier to implement into an LSI.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a timing chart showing the data conversion process from 9-bit bytes to 8-bit bytes, and Fig. 3 is a system block diagram of a data processing device to which the embodiment of the present invention is applied. FIG. 4 is a diagram showing the principle of data conversion from a 9-bit byte to an 8-bit byte. Explanation of symbols of main parts lot...Second register 102...Byte position counter 103...
... Unback switch 104 ... Second register 108 ... OR circuit 109 ... Third register

Claims (1)

[Claims] (1) A data conversion device that converts long byte data into short byte data, including an input register that stores the input long byte data one byte at a time, and both bits of the long byte data and the short byte data. counting means for changing the count contents cyclically and sequentially by a value obtained by dividing the least common multiple of the numbers by the number of bits of the short byte data; and a counting means for sequentially shifting the contents stored in the input register by the difference between the numbers of both bits. selecting means for selectively outputting one of the shifted data according to the contents of the counting means while setting the free bit area to "0"; holding means for holding lower bits equal to the number of bits of the short bit data, and logical sum means for outputting the logical sum of the upper bits of the output of the selection means equal to the number of bits of the short bit data and the holding output of the holding means. A data conversion device comprising: inputting the long byte data one byte at a time to the input register and deriving the short byte data from the logical sum means.