JPS629735Y2 - - Google Patents
Info
- Publication number
- JPS629735Y2 JPS629735Y2 JP1982129219U JP12921982U JPS629735Y2 JP S629735 Y2 JPS629735 Y2 JP S629735Y2 JP 1982129219 U JP1982129219 U JP 1982129219U JP 12921982 U JP12921982 U JP 12921982U JP S629735 Y2 JPS629735 Y2 JP S629735Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- heat dissipation
- common
- dissipation board
- portions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920005989 resin Polymers 0.000 claims description 36
- 239000011347 resin Substances 0.000 claims description 36
- 239000004020 conductor Substances 0.000 claims description 26
- 230000017525 heat dissipation Effects 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005452 bending Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982129219U JPS5936248U (ja) | 1982-08-27 | 1982-08-27 | 樹脂モ−ルド半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982129219U JPS5936248U (ja) | 1982-08-27 | 1982-08-27 | 樹脂モ−ルド半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5936248U JPS5936248U (ja) | 1984-03-07 |
JPS629735Y2 true JPS629735Y2 (enrdf_load_stackoverflow) | 1987-03-06 |
Family
ID=30292857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982129219U Granted JPS5936248U (ja) | 1982-08-27 | 1982-08-27 | 樹脂モ−ルド半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5936248U (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013239659A (ja) * | 2012-05-17 | 2013-11-28 | Sumitomo Electric Ind Ltd | 半導体デバイス |
-
1982
- 1982-08-27 JP JP1982129219U patent/JPS5936248U/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5936248U (ja) | 1984-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5596225A (en) | Leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die | |
US7473584B1 (en) | Method for fabricating a fan-in leadframe semiconductor package | |
US20240096759A1 (en) | Smds integration on qfn by 3d stacked solution | |
JP4390317B2 (ja) | 樹脂封止型半導体パッケージ | |
US5299091A (en) | Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same | |
US3786317A (en) | Microelectronic circuit package | |
US4712127A (en) | High reliability metal and resin container for a semiconductor device | |
JPS629735Y2 (enrdf_load_stackoverflow) | ||
JPS58218149A (ja) | 樹脂封止ダイオ−ド用リ−ドフレ−ム | |
JP2911265B2 (ja) | 表面実装型半導体装置 | |
KR102016019B1 (ko) | 고열전도성 반도체 패키지 | |
JP2902918B2 (ja) | 表面実装型半導体装置 | |
JPS6180842A (ja) | 半導体装置 | |
JPH0637217A (ja) | 半導体装置 | |
US7199455B2 (en) | Molded resin semiconductor device having exposed semiconductor chip electrodes | |
KR0148078B1 (ko) | 연장된 리드를 갖는 리드 온 칩용 리드프레임 | |
JP3688440B2 (ja) | 半導体装置 | |
JPS6329413B2 (enrdf_load_stackoverflow) | ||
KR100421033B1 (ko) | 열전달 효율이 높은 전력용 패키지 | |
JPS62134945A (ja) | モ−ルドトランジスタ | |
JP2003007933A (ja) | 樹脂封止型半導体装置 | |
JP3284604B2 (ja) | 放熱板付樹脂封止半導体装置の製造方法 | |
JPH02283054A (ja) | リードフレーム | |
JPH06101493B2 (ja) | プラスチツクチツプキヤリア | |
JPS6217382B2 (enrdf_load_stackoverflow) |