JPS6290090A - Luminance signal recording and reproducing circuit in vtr - Google Patents

Abstract

PURPOSE:To compact a VTR and to allow one VTR to simultaneously record and reproduce two luminance signals by installing a recording field sequential conversion processing means on a recording system and a field sequential signal decoding means also on a reproducing system. CONSTITUTION:A two-luminance signal synchronization processing means 3 in the recording system X receives the 1st recording luminance signal S1 and the 2nd recording luminance signal S2, both of which are asynchronous. The 1st recording luminance signals S1 and the 2nd recording luminance signals S9 which are synchronous each other and obtained by the two-luminance signal synchronization processing means 3, and a read timing pulse S3 are inputted to the field sequential signal decoding means 4 respectively. In the reproducing system Y, a reproduction amplifier 10 amplifies the reproduced luminance signal and supplies it to a decoding means 11. At the time of recording the decoding means 11 decodes the reproduced luminance signal subjected to frequency modulation so as to supply it to a reproduction signal processing means 12, executes the prescribed signal processing and gives the reproduced luminance signal P1 to the field sequential signal decoding means 13.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a VTR (VTR) for recording and reproducing image information, etc.
The present invention relates to a luminance signal recording/reproducing processing circuit for recording/reproducing luminance signals in a VTR.

(Prior Art) Conventional VTRs are generally configured so that only one luminance signal that has left the station can be recorded and reproduced.

Therefore, when trying to record two programs simultaneously using such a conventional VTR, 1. Alternatively, if you want to play two programs in parallel at the same time, you will need two VTRs; In order to improve the ability to record and play back, it is possible to install two systems such as a recording medium system, a magnetic head, a recording signal processing circuit, and a reproduction signal processing circuit, but in that case, There are disadvantages such as the device becomes larger and the cost becomes extremely high.

(Objectives of the Invention) The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a VTR that can be constructed relatively compactly and inexpensively, and that can simultaneously record and reproduce two luminance signals. An object of the present invention is to provide a recording/reproducing processing circuit for luminance signals.

(Structure of the Invention) In order to achieve the above object, the recording/reproduction processing circuit for a luminance signal in a VTR according to the present invention has a recording system that records a first recording luminance signal and a second recording luminance signal simultaneously. t11, a second synchronization separation circuit separates and outputs a horizontal open one signal point vertical synchronization signal from the second recording luminance signal, and a second recording luminance signal is generated based on the same jtJ] signal obtained thereby. An A/'D conversion processing circuit and a clock signal generation circuit to digitize, a write timing pulse generation circuit to write the digitized data of the second recording luminance signal to the field memory, and an address for the write data are specified. and a write address signal generation circuit for outputting a horizontal synchronization signal and a vertical synchronization signal separately from the first recording luminance signal in order to read the digital data of the second recording luminance signal synchronized with the first recording luminance signal from the field memory. a first synchronization separation circuit for reading out the digital data based on the same amount signal obtained by the first synchronization separation circuit; a readout timing pulse generation circuit for reading out the digital data based on the same amount signal obtained therefrom; a readout address signal generation circuit for specifying a readout address; Two luminance signal synchronization processing means consisting of a D/A conversion processing circuit that converts digital data read from the memory into analog are provided, and mutually synchronized first records obtained by the two luminance signal synchronization processing means are provided. A recording field sequential conversion processing means is provided with a recording switching circuit that alternately selects and outputs the luminance signal and the second recording luminance signal every one field period, and the reproduction system is provided with a recording field sequential conversion processing means that selectively outputs the luminance signal and the second recording luminance signal alternately every field period. a reproduction synchronization separation circuit that separates and outputs a vertical synchronization signal from the reproduced luminance signal, and alternately outputs a first reproduction switching signal and a second reproduction switching signal in response to the vertical synchronization signal obtained thereby; a reproduction switching signal output circuit; a vertical scanning period delay processing circuit that performs predetermined delay processing on the reproduced luminance signal based on the cycle of the vertical synchronization signal and outputs a delayed reproduced luminance signal; and a delayed reproduction obtained thereby. Luminance signal]
1; A field sequential signal comprising a first switching circuit for reproduction and a second switching circuit for reproduction, which alternately select and output the reproduced luminance signal described in 1 according to the first switching signal for reproduction and the second switching signal for reproduction. It has the feature of being equipped with demodulation means.

(Example) Hereinafter, specific embodiments of the present invention will be described based on the drawings.

FIG. 1 is a schematic block circuit diagram showing a luminance signal recording and reproducing processing circuit in a VTR separated into a recording system X and a reproducing system Y, and FIG. 2 is a detailed block circuit diagram of the luminance signal synchronization processing means 3, FIG. 3 is a detailed block circuit diagram of the recording field sequential conversion processing means 4 in FIG. 1, and FIG. 4 is a detailed block circuit diagram of the field sequential conversion processing means 4 in FIG. Detailed block circuit diagrams of the signal demodulating means 13 are shown respectively, and FIG.
A signal waveform diagram for explaining the operation of the luminance signal synchronization processing means 3 and the recording field sequential conversion processing means 4 is shown below.
FIG. 6 shows signal waveform diagrams for explaining the operation of the field sequential signal demodulating means 13.

The two luminance signal synchronization processing means 3 in the recording system
As shown in FIGS. 3 and 5, the first recording luminance signal St and the second recording luminance signal are not synchronized with each other and are generated by a broadcast receiving circuit (not shown) included in the VTR. Signals S2 (shown at (1) and (2) in FIG. 5) are received via input terminals 1.2, respectively. The two luminance signal synchronization processing means 3 includes a second synchronization separation circuit 20 that separates and outputs a horizontal open 1υI signal S5 and a vertical synchronization signal s6 from the second recording luminance signal S2, and a horizontal synchronization signal obtained thereby. Clock signal generation diagram 1s19 that generates the lock signal s9, which is necessary when the second recording luminance signal S2 is digitized by the A/D conversion processing circuit 16 based on S5.
, a field memory 17 capable of storing the digital data of the second recording luminance signal s2 obtained by the A/D conversion processing circuit 16 for one field period, and a timing pulse S7 when writing the digital data to the field memory 17. Write timing pulse generation circuit 2 that generates
2, and a write address signal generation circuit 23 that generates a signal specifying an address for write data, and a second recording brightness signal S9 (shown in ■ in FIG. 5) synchronized with the first recording brightness signal Sl. ), the horizontal synchronization signal S4 and the vertical synchronization signal s are input from the first recording luminance signal S1.
The timing pulse 58 necessary for reading out the digital data written in the field memory 17 based on the first synchronization signal S4 and the vertical synchronization signal S3 obtained thereby, (
Read timing pulse generation circuit 2 that generates S3)
4, and a read address signal generation circuit 25 that specifies generation of a read address signal, and further includes a D/A conversion processing circuit 18 that converts digital data read from the field memory 17 into analog. There is.

The field sequential signal demodulation means 4 receives a first recording luminance signal s1 and a second recording luminance signal S9 synchronized with each other obtained by the two luminance signal synchronization processing means 3 (indicated by ) and the read timing pulse 33 (S8) are input to the input terminals 26, 27, 28.
are respectively input via the .

This field sequential signal demodulation means 4 selectively outputs a first recording luminance signal s1 given to the individual contact point S and a second recording luminance signal s9 given to the individual contact point C via the movable contact a. a recording switching signal that outputs a recording switching signal S10 (shown in ■ in FIG. 5) for switching and operating the recording switching circuit 30 in response to the reading timing pulse 33 (3B); T as output circuit 29
It has flip-flops. Note that the recording switching signal output circuit 2 consisting of the above-mentioned T flip-flop
Reference numeral 9 is a negative edge trigger type, which operates at the falling point of the read timing pulse 53 (S8) to output a recording switching signal SIO.

The field sequential signal demodulation means 4 then converts the luminance signal AI included in the first recording luminance signal Sl.

Az, As... and the luminance signals B+, B:1. included in the second recording luminance signal S9. Bs... are alternately switched every one field period in response to the recording switching signal 310, and a sequentially generated recording field sequential processing signal 5ll (shown in ■ in FIG. 5) is output. .

Note that the output of the recording switching circuit 30 shown in FIG. 3, that is, the recording field sequential processing signal Sll
is supplied via the output terminal 31 to the recording signal processing means 5 shown in FIG. 1, where predetermined signal processing is performed. Further, the FM modulation means 6 frequency-modulates the output from the recording signal processing means 5 and supplies it to the recording amplifier 7 for amplification. A recording luminance signal frequency-modulated is recorded on a magnetic tape serving as a magnetic recording medium 9.

On the other hand, in the reproduction system Y, as shown in FIGS. 1, 4, and 6, a reproduction amplifier 10 amplifies the reproduced luminance signal reproduced by the rotating magnetic head 8,
The demodulating means 11 demodulates the reproduced luminance signal, which has been frequency modulated during recording, and supplies it to the reproduced signal processing means 12, which performs predetermined signal processing and converts it into field sequential signal demodulating means. Reproduction luminance signal P1 to 13
(shown in ■ in Figure 6) is given.

As shown in FIG. 4, the field sequential signal demodulation means 13 converts the reproduced luminance signal P1 to the vertical synchronization signal P5 (
A regeneration synchronization separation circuit 33 separates and outputs the signals (shown in A reproduction switching signal output circuit 34 consisting of a negative edge trigger type T flip-flop outputs a reproducing switching signal output circuit 34 which performs a predetermined delay process on the reproduced luminance signal P1 based on the period of the vertical synchronizing signal P5, that is, the reproduced luminance signal P1 is subjected to one vertical scan. a vertical scanning period delay processing circuit 35 that outputs a delayed reproduced luminance signal P2 after performing a process of delaying the same by a period of time; P6 and second reproduction switching signal P7
It is provided with a first switching circuit for reproduction 36 and a second switching circuit for reproduction 37 which selectively output alternately according to the output.

The movable contact a1 of the first switching circuit for reproduction 36 is connected to the first switching signal output from one output terminal Q1 of the switching signal output circuit for reproduction consisting of a T flip-flop.
When the regeneration switching signal P6 is at High level, it is connected to one individual contact b1, and when the first regeneration switching signal P6 is at Low level, it is connected to the other individual contact c1.
connected to. Therefore, the movable contact a outputs the first reproduced luminance signal P3 as shown in (■) in FIG.

Further, the movable contact a2 of the second regeneration switching circuit 37 is activated when the second regeneration switching signal P7 outputted from the other output terminal Q+ of the regeneration switching signal output circuit 34 consisting of a T flip-flop is at H4gh level. is connected to one individual contact S, and is connected to the other individual contact C2 when the second reproduction switching signal P7 is at a low level. Therefore, the movable contact a2 outputs a second reproduced luminance signal P4 as shown in (■) in FIG.

In this way, the first reproduced luminance signal P3 and the second reproduced luminance signal P4 are reproduced, and when the television monitors are respectively connected to the output terminals 14 and 15 shown in FIG. The reproduced image is displayed.

(Effects of the Invention) As is clear from the detailed description above, according to the luminance signal recording and reproducing processing circuit in a VTR according to the present invention,
The recording system is provided with recording field sequential conversion processing means for field sequential conversion processing of the first recording luminance signal and the second recording luminance signal every vertical scanning period, and the reproduction system is provided with the recording field sequential conversion processing means. It is equipped with a field sequential signal demodulation means for field sequential signal demodulation of the reproduced luminance signal of the signal recorded by the VTR every one vertical scanning period. Since it is possible to record and play back two luminance signals at the same time, it is possible to record and play back two programs such as television broadcast programs at the same time, achieving a significant increase in the functionality of VTRs in an economical manner. This has led to excellent results.

[Brief explanation of drawings]

The drawings show a specific embodiment of the luminance signal recording/reproduction processing circuit in a VTR according to the present invention, and FIG. 1 depicts the luminance signal recording/reproduction processing circuit separated into a recording system X and a reproduction system Y. 2 is a detailed block circuit diagram of the two luminance signal synchronization processing means, and FIG. 3 is a detailed block circuit diagram of the recording field sequential conversion processing means.
FIG. 4 is a detailed block circuit diagram of the field sequential signal demodulation means, FIG. 5 is a signal waveform diagram for explaining the operation of the two luminance signal synchronization processing means and the recording field sequential conversion processing means, and FIG. 6 is a detailed block circuit diagram of the field sequential signal demodulation means. is a signal waveform diagram for explaining the operation of field sequential signal demodulation means. X...Recording system, Y...Reproduction system, 3...2 luminance signal synchronization processing means, 4... Recording field sequential conversion processing means, 9...
magnetic recording medium, 13...field sequential signal demodulation means, 16...A
/D conversion processing circuit, 17... Field memory, 18... D/A conversion processing circuit, 19... Clock signal generation circuit, 20... Second synchronization separation circuit, 21... First synchronization separation circuit, 22... write timing pulse generation circuit, 23.
...Write address signal generation circuit, 24...Read timing pulse generation circuit, 25...Read address signal generation circuit, 30...Switching circuit for recording, 33...Synchronization separation circuit for playback, 34...・Reproduction switching signal output circuit, 35...
- Vertical scanning period delay processing circuit, 36... First switching circuit for reproduction, 37... Second switching circuit for reproduction, Sl... First recording luminance signal, S2... Second recording luminance signal, S3...Vertical synchronization signal of the first recording luminance signal Sl, S4
...Horizontal synchronization signal of the first recording luminance signal S1, S5...
- Horizontal synchronization signal of the second recording luminance signal S2, S6... Vertical synchronization signal of the second recording luminance signal S2, S9... Synchronized second recording luminance signal, Pl... Reproduction luminance signal, Pl. ... Delayed reproduction luminance signal, P5... Vertical synchronization signal, P6... Switching signal for first reproduction, Pl... Switching signal for second reproduction.

Claims (1)

[Claims] The recording system includes a second synchronization separation circuit that separates and outputs a horizontal synchronization signal and a vertical synchronization signal from the second recording luminance signal in order to synchronize the second recording luminance signal with the first recording luminance signal; an A/D conversion processing circuit and a clock signal generation circuit that digitize the second recording luminance signal based on the synchronization signal, and a write timing pulse generation circuit for writing the data of the digitized second recording luminance signal into the field memory. a write address signal generation circuit for specifying an address for write data;
In order to read digital data of a second recording luminance signal synchronized with the first recording luminance signal from the field memory,
a first synchronization separation circuit that separates and outputs a horizontal synchronization signal and a vertical synchronization signal from a first recording luminance signal; a readout timing pulse generation circuit for reading out the digital data based on the synchronization signal obtained thereby; and a readout timing pulse generation circuit for reading the digital data based on the synchronization signal obtained thereby; a read address signal generation circuit for specifying an address;
Two luminance signal synchronization processing means consisting of a D/A conversion processing circuit that converts digital data read from the field memory into analog data are provided, and two luminance signal synchronization processing circuits are provided that are synchronized with each other obtained by the two luminance signal synchronization processing means. Recording field sequential conversion processing means is provided with a recording switching circuit that alternately selects and outputs the first recording luminance signal and the second recording luminance signal every one field period, and the reproduction system is provided with a recording field sequential conversion processing means that selectively outputs the first recording luminance signal and the second recording luminance signal alternately every one field period. a reproduction synchronization separation circuit that separates and outputs a vertical synchronization signal from the reproduced luminance signal obtained by the reproduction synchronization signal, and alternately outputs a first reproduction switching signal and a second reproduction switching signal in response to the vertical synchronization signal obtained thereby. a reproduction switching signal output circuit; a vertical scanning period delay processing circuit that performs predetermined delay processing on the reproduced luminance signal based on the cycle of the vertical synchronization signal and outputs a delayed reproduced luminance signal; and a delayed reproduction obtained thereby. A field sequential signal comprising a first switching circuit for reproduction and a second switching circuit for reproduction, which alternately select and output a luminance signal and the reproduced luminance signal according to the first switching signal for reproduction and the second switching signal for reproduction. 1. A recording and reproducing processing circuit for a luminance signal in a VTR, characterized in that it is provided with demodulation means.