JPS628947B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor capacitive element, and more particularly to a semiconductor capacitive element that reduces errors in capacitance ratio between a plurality of capacitive elements formed on a semiconductor substrate.

In recent years, metal/oxide film/semiconductor (MOS)
With the continuous progress in manufacturing technology and circuit design technology, the field of application is rapidly expanding. As an example, in the field of conventional digital-to-analog converters using resistive elements, a digital-to-analog converter using capacitance has been announced. For example, IEEE J.of SSC Vol.SC−10 No.6
JL disclosed in pp371-379 (Dec.1979)
“All-MOS” by McCREARY and PRGRAY
Charge RedistributionAnalog−to−Digital
Conversion Techniques-Part I”.

As disclosed in the above paper, capacitive elements are used to convert digital to analog converters or analog to analog converters.
A digital converter can be configured. At this time, the cause of deterioration in the accuracy of the converter is the accuracy of the capacitance ratio between the capacitive elements.

Conventionally, it has been well known to connect unit capacitive elements in parallel as a method of ensuring the accuracy of the capacitance ratio between capacitive elements.

A point to consider when manufacturing unit capacitance elements using MOS technology is to reduce errors between unit capacitance elements due to variations in the manufacturing process. For this reason, as a conventional means, a circular structure as shown in FIG. 1 was used for the unit capacitance element.

FIG. 1a is a plan view of a unit capacitance element 5 having a MOS structure, and FIG. 1b is a sectional view taken along cutting line XX'. FIG. 1 shows a diffusion region 2 of an opposite conductivity type formed in the form of an island on the main surface of a semiconductor substrate 4 of one conductivity type.
An insulating oxide film 3 is formed on the semiconductor substrate 5, and the thickness of the unit capacitor element portion is reduced. This film thickness can be controlled by forming the oxide film on the entire surface and then
After selectively etching the upper MOS unit capacitor element portion, a uniform insulating oxide film can be formed again. After depositing a thin layer of metal on the insulating oxide film 3, the metal electrode 1 is selectively etched and left in correspondence with the diffusion region 2, thereby forming the MOS capacitor element 5 between the regions 1, 3, and 2. Form.

The unit capacitive element 5 described above with reference to the drawings has the following advantages.

Since errors in selective etching (for example, overetching, underetching, etc.) are considered to occur evenly between each unit capacitance element, there is little deterioration in relative accuracy.

Even when selective etching has directionality, there is little deterioration in relative accuracy because the geometrical shape is point symmetric.

However, in the prior art as shown in FIG. 1, there are four acute angle points in the lead-out portion of the metal electrode. At this acute angle, manufacturing errors are likely to occur during selective etching, which often causes deterioration in relative precision between unit capacitance elements.
In order to avoid this influence, it is necessary to increase the shape of the unit capacitive element 5. Furthermore, the capacitance value of a circular shape is only 3/4 that of a square unit capacitance element with one side of the same length, so the geometric shape becomes larger and it is difficult to provide an inexpensive MOS integrated circuit. Can not.

The present invention ameliorates most of these drawbacks and provides an inexpensive
The present invention provides an effective semiconductor capacitive element for realizing a MOS integrated circuit using a unit capacitive element.

That is, the present invention provides semiconductor capacitive elements formed on the same semiconductor substrate, in which the take-out portion of the unit capacitive element and the angle of the unit capacitive element are approximately 45 degrees, and a plurality of unit capacitive elements are interconnected by an electrically conductive means. The semiconductor capacitive element is characterized in that a single capacitive element is formed by a plurality of capacitive elements, and a ratio of a capacitance of the single capacitive element to a capacitance of the unit capacitive element is set to a predetermined value.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a plan view of the first embodiment of the present invention, and the sectional view taken along the XX' section has the same configuration as FIG. 1b.

FIG. 2 has a cross-sectional structure similar to that of FIG. 1, and has a semiconductor substrate 4 of one conductivity type formed in the form of an island and a diffusion region 22 of the opposite conductivity type, with a thin layer formed above the diffusion region 22. metal electrode 2 through insulating oxide film 3
FIG. 1 is an explanatory diagram of a first example of a unit capacitance element formed by forming a unit capacitor 1;

If this first embodiment of the present invention is used, the extraction portions of the metal electrodes 21 are taken out using an inclination of 45 degrees, and each corner is inclined at an angle of 45 degrees, so that during selective etching. Since the manufacturing errors are canceled out at each corner and the lead-out portion of the metal electrode 21, it is very rare that the relative accuracy between the unit capacitance elements 25 becomes a cause of deterioration. Therefore, it is possible to realize a unit capacitive element with small relative accuracy between capacitive elements. Furthermore, if the area of the 45-degree inclination of the metal electrode 21 and the area of each corner are the same, the capacitance value of the unit capacitive element can be considered to be, for example, the area of a square, so the geometric shape can be made smaller. It is possible to provide an inexpensive MOS integrated circuit.

An explanatory diagram of a second embodiment of the present invention is shown in FIG. FIG. 3 shows an example in which a film conductor 32 and an insulating oxide film 36 are used as the diffusion region 2 of the opposite conductivity type in FIG. It is. FIG. 3 is an example of a unit capacitance element 35 formed between a film conductor 32, an insulating oxide film 33, and a metal electrode 31, and its effectiveness differs from the first embodiment of the present invention in the structure of the cross-sectional view. It is obvious.

As described above in detail with reference to the figures, if the present invention is implemented, a capacitive element with excellent relative accuracy can be realized in a small area using a unit capacitive element, and an inexpensive MOS integrated circuit can be realized. It is very effective in expanding the field of application.

[Brief explanation of the drawing]

FIG. 1 is a plan view and b sectional view of a unit capacitance element with a conventional metal/oxide film/semiconductor structure, FIG. 2 is a plan view of the first embodiment of the present invention, and FIGS. FIG. 6 shows a plan view and a cross-sectional view of a second embodiment of the invention, respectively. In the figure, 1, 21, 31...metal electrode, 2, 22... island-shaped diffusion region, 3, 33, 3
6... Insulating oxide film, 4, 34... Semiconductor substrate,
5, 25, 35...unit capacitance element, 32...membrane conductor.

Claims (1)

[Claims] 1. In a semiconductor capacitive element formed by interconnecting a plurality of unit capacitive elements formed on the same semiconductor substrate, the electrode lead-out portions and corners of the unit capacitive element have a taper of approximately 45° in plan view. A semiconductor capacitive element characterized by being provided with.