JPH02133952A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02133952A JPH02133952A JP28793388A JP28793388A JPH02133952A JP H02133952 A JPH02133952 A JP H02133952A JP 28793388 A JP28793388 A JP 28793388A JP 28793388 A JP28793388 A JP 28793388A JP H02133952 A JPH02133952 A JP H02133952A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- dielectric film
- capacitor
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 230000002411 adverse Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野コ 本発明は半導体装置におけるキャパシタ構造に関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to a capacitor structure in a semiconductor device.
［従来の技術］
従来、半導体装置に形成されるキャパシタの構造は、半
導体表面に形成された第１の電極となる拡散層の表面に
ＳｉＯ□膜等の誘電体膜を形成し、該誘゛電体膜表面に
第２の電極を形成し、第１と第２の電極間の電気容量を
用いるホリゾンタル（水平型）キャパシタが最も一般的
に用いられていた更に、最近はスタックド（積層型）キ
ャパシタとして、半導体基板表面に形成された絶縁膜表
面に第１の電極を形成し、該第１の電極表面に誘電体膜
を介して第２の電極を形成する。これも一種のホリゾン
タル・キャパシタ構造もある。[Prior Art] Conventionally, the structure of a capacitor formed in a semiconductor device is to form a dielectric film such as a SiO Horizontal capacitors, in which a second electrode is formed on the surface of the electric film and the capacitance between the first and second electrodes is used, are most commonly used.Moreover, stacked capacitors have recently been used. As a capacitor, a first electrode is formed on the surface of an insulating film formed on the surface of a semiconductor substrate, and a second electrode is formed on the surface of the first electrode with a dielectric film interposed therebetween. This also has a kind of horizontal capacitor structure.
更に、開発段階ではトレンチ（埋め込み型）キャパシタ
として、半導体基板表面からトレンチ（溝）を形成し、
該トレンチ内にキャパシタを形成する方法も取られては
いる。Furthermore, at the development stage, a trench (groove) is formed from the surface of the semiconductor substrate as a trench (embedded) capacitor.
A method of forming a capacitor within the trench has also been adopted.
［発明が解決しようとする課題］
しかし、上記従来技術によると、ホリゾンタル・キャパ
シタにしても、スタックド・キャパシタにしても、大容
量を得るには大面積を要すると云う課題がある。[Problems to be Solved by the Invention] However, according to the above-mentioned prior art, there is a problem that a large area is required to obtain a large capacity, whether it is a horizontal capacitor or a stacked capacitor.
又、トレンチ・キャパシタは、半導体基板のドライ・エ
ツチング加工を要し、素子特性にドライ・エツチング加
工が損傷を与えると云う課題もあった。Further, trench capacitors require dry etching of the semiconductor substrate, and there is also the problem that dry etching damages the device characteristics.
本発明は、かかる従来技術の課題を解決し、小面積で且
つ大容量を半導体基板表面上に形成し、素子特性への影
響も少な（するような新しいキャパシタ構造を提供する
事を目的とする。The present invention aims to solve the problems of the prior art and provide a new capacitor structure that has a small area and a large capacitance on the surface of a semiconductor substrate, and has less influence on device characteristics. .
［課題を解決するための手段］
上記課題を解決するために、本発明は半導体装置に関し
、半導体表面にほぼ垂直に形成した２つの電極間に誘電
体膜を形成したいわゆるラテラル・キャパシタを形成す
る手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a semiconductor device, and forms a so-called lateral capacitor in which a dielectric film is formed between two electrodes formed substantially perpendicular to the semiconductor surface. take measures.
［実施例］ 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図及び第２図は本発明の実施例を示す半導体装置に
おけるキャパシタ構造の要部の断面図である。1 and 2 are cross-sectional views of essential parts of a capacitor structure in a semiconductor device showing an embodiment of the present invention.
第１図では、８１基板１の表面に、Ｓ ｉ Ｏ，膜等か
ら成る絶縁膜２が形成され、該絶縁膜２の表面に、第１
の電極３と第２の電極４とが相対向して形成され、該第
１の電極３と第２の電極４との間に誘電体膜５が形成さ
れて成る。この場合、例えば第１の電極３は多結晶Ｓ１
膜等を絶縁膜２の表面に形成し、ホト・エツチングによ
り第１電極６となし、該第１の電極３０表面を酸化して
ＳｉＯ□腹となし、該Ｓｉｎ、膜を誘電体膜５となし、
該誘電体膜は第１電極３の全表面に形成される訳である
が、該誘電体膜等の表面に多結晶Ｓ１膜等を再度形成し
、エッチ・バックすることにより第２電極４となすこと
ができる。又、最近のｆｆ＆細加工技術により、絶縁膜
２上に電極膜を形成し、ホト・エッチにより、第１電極
５と第２電極４とを形成し、該第１電極３と第２電極４
との間隙を誘電体膜５で埋めると云う方法で形成するこ
ともできる。In FIG. 1, an insulating film 2 made of SiO, a film, etc. is formed on the surface of a substrate 1 81, and a first insulating film 2 is formed on the surface of the insulating film 2.
An electrode 3 and a second electrode 4 are formed to face each other, and a dielectric film 5 is formed between the first electrode 3 and the second electrode 4. In this case, for example, the first electrode 3 is made of polycrystalline S1
A film or the like is formed on the surface of the insulating film 2 and formed into a first electrode 6 by photo-etching, the surface of the first electrode 30 is oxidized to form a SiO□ anode, and the Si film is formed into a dielectric film 5. none,
The dielectric film is formed on the entire surface of the first electrode 3, but by forming a polycrystalline S1 film or the like again on the surface of the dielectric film and etching back, the second electrode 4 and the like are formed. It can be done. In addition, an electrode film is formed on the insulating film 2 using recent FF & fine processing technology, and a first electrode 5 and a second electrode 4 are formed by photo-etching.
It can also be formed by filling the gap with the dielectric film 5.
第２図では、Ｓｉ基板１１０表面に拡散層１６と絶縁膜
１２とを形成し、該絶縁膜１２の表面には第１の電極１
３を形成し、前記絶縁膜１２の前記拡散層１６上に開け
られたコンタクト穴を埋める形で前記第１電極１３の少
くとも側面に形成された誘電体膜１５を挾んで第２電極
１４が形成されて成る。尚、第１電極１３は、共通電極
として、他の側面にも第２電極１４と同様の電極を形成
し、キャパシタとなすことができる事は云うまでもない
。In FIG. 2, a diffusion layer 16 and an insulating film 12 are formed on the surface of a Si substrate 110, and a first electrode 1 is formed on the surface of the insulating film 12.
3, and a second electrode 14 is sandwiched between a dielectric film 15 formed on at least a side surface of the first electrode 13 to fill a contact hole formed on the diffusion layer 16 of the insulating film 12. formed. It goes without saying that the first electrode 13 can be used as a common electrode by forming an electrode similar to the second electrode 14 on the other side thereof to form a capacitor.
［発明の効果コ
本発明により小面積で且つ大容量のキャパシタを半導体
表面上に形成することができ、半導体素子へのキャパシ
タ形成時のラジェーシ曹ン・ダメージ等による素子特性
の劣化を極力押える事ができる等の効果がある。[Effects of the Invention] According to the present invention, a small-area, large-capacity capacitor can be formed on the surface of a semiconductor, and deterioration of device characteristics due to radiation damage, etc. when forming a capacitor on a semiconductor device can be minimized. There are effects such as being able to.
２ 。2.
３ 。3.
４ 。4.
５ 。5.
１２・・・・・・・・・絶縁膜 １３・・・・・・・・・第１電極 １４・・・・・・・・・第２電極 １５・・・・−・・・・誘電体膜 ・・・・・・・・・・・・・・・拡散層以上12・・・・・・Insulating film 13......First electrode 14... Second electrode 15・・・・・・・・・Dielectric film ・・・・・・・・・・・・・・・ Above the diffusion layer
Claims (1)
は誘電体膜が形成されて成るいわゆるラテラル・キャパ
シタが形成されて成る事を特徴とする半導体装置。A semiconductor device characterized in that a so-called lateral capacitor is formed in which a dielectric film is formed between two electrodes formed substantially perpendicular to the surface of a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28793388A JPH02133952A (en) | 1988-11-15 | 1988-11-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28793388A JPH02133952A (en) | 1988-11-15 | 1988-11-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02133952A true JPH02133952A (en) | 1990-05-23 |
Family
ID=17723611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28793388A Pending JPH02133952A (en) | 1988-11-15 | 1988-11-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02133952A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434742A (en) * | 1991-12-25 | 1995-07-18 | Hitachi, Ltd. | Capacitor for semiconductor integrated circuit and method of manufacturing the same |
| US6525427B2 (en) | 1999-01-04 | 2003-02-25 | International Business Machines Corporation | BEOL decoupling capacitor |
| JP2018515929A (en) * | 2015-05-08 | 2018-06-14 | シーラス ロジック インターナショナル セミコンダクター リミテッド | High density capacitors formed from thin vertical semiconductor structures such as FINFETs |
-
1988
- 1988-11-15 JP JP28793388A patent/JPH02133952A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434742A (en) * | 1991-12-25 | 1995-07-18 | Hitachi, Ltd. | Capacitor for semiconductor integrated circuit and method of manufacturing the same |
| US5745336A (en) * | 1991-12-25 | 1998-04-28 | Hitachi, Ltd. | Capacitor for semiconductor integrated circuit |
| US6525427B2 (en) | 1999-01-04 | 2003-02-25 | International Business Machines Corporation | BEOL decoupling capacitor |
| JP2018515929A (en) * | 2015-05-08 | 2018-06-14 | シーラス ロジック インターナショナル セミコンダクター リミテッド | High density capacitors formed from thin vertical semiconductor structures such as FINFETs |
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