JPS61279166A - Substrate for hybrid integrated circuit - Google Patents
Substrate for hybrid integrated circuitInfo
- Publication number
- JPS61279166A JPS61279166A JP12101285A JP12101285A JPS61279166A JP S61279166 A JPS61279166 A JP S61279166A JP 12101285 A JP12101285 A JP 12101285A JP 12101285 A JP12101285 A JP 12101285A JP S61279166 A JPS61279166 A JP S61279166A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film capacitor
- integrated circuit
- substrate
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、絶縁基板の上に膜技術によシ、コンデンサや
抵抗などの受動素子を形成し、さらに集積回路チップな
どの能動素子を搭載して混成集積回路を形成するための
基板に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to forming passive elements such as capacitors and resistors on an insulating substrate using film technology, and further mounting active elements such as integrated circuit chips. The present invention relates to a substrate for forming a hybrid integrated circuit.
$2[1(a)〜(d)は、従来の混成集積回路におけ
る薄膜コンデンサの製造方法を説明するための断面図で
ある。まず、第2図(a)のよつに、アルミナセラミッ
クなどの絶縁基板1の上のコンデンサ形成部に、できる
だけの平滑面とするためにガラス層12を被着し、つぎ
に同図(b)のように、陽極化成などの方法で誘電体と
することができる金属、例えばタンタルをスパッタリン
グなどの方法で全面に被着したのち、ガラス層2の上に
タンタル3が所定の形状で残るように、化学的エツチン
グなどでパターン化する。つぎに同図(C)のよりに、
タンタル層3の一部を陽極化成などの方法で誘電体層4
に変える。つぎに同図(d)のように、タンタル3の未
化成部分5から下部引出し電極7を引出し、また、誘電
体層4の上に上部電極6を設け、誘電体層4を下面の未
化成タンタルと上面の電極6ではさんだ薄膜コンデンサ
が絶縁性基板1の上面に形成される。$2[1(a) to (d) are cross-sectional views for explaining a method of manufacturing a thin film capacitor in a conventional hybrid integrated circuit. First, as shown in FIG. 2(a), a glass layer 12 is applied to the capacitor formation portion on an insulating substrate 1 made of alumina ceramic or the like to make the surface as smooth as possible, and then ), a metal that can be made into a dielectric by a method such as anodization, such as tantalum, is deposited on the entire surface by a method such as sputtering, and then tantalum 3 is left in a predetermined shape on the glass layer 2. Then, it is patterned by chemical etching. Next, from the same figure (C),
A part of the tantalum layer 3 is formed into a dielectric layer 4 by a method such as anodization.
Change to Next, as shown in FIG. 4(d), the lower extraction electrode 7 is drawn out from the unformed portion 5 of the tantalum 3, and the upper electrode 6 is provided on the dielectric layer 4, and the dielectric layer 4 is connected to the unformed portion 5 on the lower surface. A thin film capacitor sandwiched between tantalum and an electrode 6 on the top surface is formed on the top surface of the insulating substrate 1.
上記のような薄膜コンデンサの容量値は、その面積およ
び誘電体層の厚さで決まることは周知である。よって、
できるだけ大きな容量を得ようとすれば、当然面積を大
きくするか、誘電体層の厚さを薄くすればよい。しかし
、誘電体層の厚さを薄くするには耐圧の点で限界があシ
、また、面積を広げることは、当然コンデンサの占有面
積が増大し、ひいては基板の大形化によシ、実装面積が
増大するとか、コスト増の問題が生じる。It is well known that the capacitance value of a thin film capacitor as described above is determined by its area and the thickness of the dielectric layer. Therefore,
In order to obtain as large a capacity as possible, it is natural to increase the area or reduce the thickness of the dielectric layer. However, reducing the thickness of the dielectric layer has a limit in terms of withstand voltage, and increasing the area naturally increases the area occupied by the capacitor, which in turn leads to an increase in the size of the board. Problems such as increased area and increased costs arise.
上記問題点に対し、本溌咽では、混成集積回路を形成す
る絶縁基板上の少lくとも薄膜コンデンサを形成する部
分を凹凸面とし、この凹凸によシ、この部分に形成され
た薄膜コンデンサの容量を、従来の平坦面上に形成した
薄膜コンデンサに比べ、大幅に増大させるのである。In order to solve the above problem, in the present invention, at least the part where the thin film capacitor is formed on the insulating substrate forming the hybrid integrated circuit is made into an uneven surface, and the uneven surface allows the thin film capacitor formed on this part to be formed on the uneven surface. This significantly increases the capacitance of the capacitor compared to conventional thin film capacitors formed on flat surfaces.
つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.
第1図は本発明の一実施例の部分断面図である。FIG. 1 is a partial cross-sectional view of one embodiment of the present invention.
図において、アルミナセラミックなどの絶縁基板1の薄
膜コンデンサの形成部に、表面に凹凸のあるガラス層2
が形成されている。ガラス層2の表面は、この上に形成
される薄膜コンデンサが不良とならない程度の平滑さを
有し、かつ、その凹凸は、ガラス層2の上の薄膜コンデ
ンサの誘電体層の厚さの約100倍以上の一定の距離で
くシ返しをもつものである。In the figure, a glass layer 2 with an uneven surface is placed on an insulating substrate 1 made of alumina ceramic, etc., where a thin film capacitor is formed.
is formed. The surface of the glass layer 2 is smooth enough not to cause defects in the thin film capacitor formed thereon, and its unevenness is approximately the thickness of the dielectric layer of the thin film capacitor on the glass layer 2. It has barbs at a constant distance of 100 times or more.
なお、上記実施例は、コンデンサ形成部が基板本体と別
個のガラスでもって凹凸面とされているが、これはガラ
スに限定されず他の材料でもよく、また、直接基板自身
に所望の凹凸をつけることでもよいのはいうまでもない
。In the above embodiment, the capacitor forming part is made of glass separate from the substrate body to form an uneven surface, but this is not limited to glass and may be made of other materials, or the desired unevenness may be directly formed on the substrate itself. Needless to say, you can also attach it.
本発明の混成集積回路用基板を用いて、凹凸面のガラス
層2の上に陽極化成によシ誘電体とすることのできる金
属を被着し、第2図(b) 、 (C) 、 (d)に
示す従来例と同様の工程を加えることによシ、ガラス層
2の凹凸面に沿った誘電体層を有する薄膜コンデンサが
答易に製造できる。そして、このコンデンサは、凹凸面
に沿った誘電体層の実効面積を、その面を垂直に投射し
た見かけの平面面積より大きな面積となplよって従来
の平坦面に形成したコンデンサに比べ、同じ基板占有面
積に拘わらず、遥かに大きな容量をもつ薄膜コンデンサ
を作ることができる効果がある。Using the substrate for a hybrid integrated circuit of the present invention, a metal that can be made into a dielectric material is deposited on the uneven glass layer 2 by anodization, as shown in FIGS. 2(b), (C), By adding the same steps as in the conventional example shown in (d), a thin film capacitor having a dielectric layer along the uneven surface of the glass layer 2 can be easily manufactured. The effective area of the dielectric layer along the uneven surface of this capacitor is larger than the apparent planar area of the surface projected perpendicularly. This has the effect of making it possible to create thin film capacitors with much larger capacitance regardless of the occupied area.
第1図は本発明の一実施例の部分断面図、第2図(a)
〜(d)は従来の混成集積回路用基板を用いた薄膜コン
デンサの製造方法を説明するだめの工程順の断面図であ
る。
1・・・絶縁基板、2・・・凹凸面ガラス層、3・・・
タンタル層、4・・・誘電体層、6・・・上部電極、7
・・・下部引出し電極、12・・・平坦面ガラス層。
華 1 図
$ 2 図FIG. 1 is a partial sectional view of an embodiment of the present invention, and FIG. 2(a)
-(d) are cross-sectional views showing the sequence of steps for explaining a method of manufacturing a thin film capacitor using a conventional substrate for a hybrid integrated circuit. 1... Insulating substrate, 2... Uneven surface glass layer, 3...
Tantalum layer, 4... Dielectric layer, 6... Upper electrode, 7
. . . lower extraction electrode, 12 . . . flat surface glass layer. Flower 1 Figure $ 2 Figure
Claims (1)
板において、少なくとも前記薄膜コンデンサ形成部分が
凹凸面とされていることを特徴とする混成集積回路用基
板。1. A hybrid integrated circuit substrate having a thin film capacitor formed on an upper surface thereof, wherein at least the thin film capacitor forming portion has an uneven surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12101285A JPS61279166A (en) | 1985-06-04 | 1985-06-04 | Substrate for hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12101285A JPS61279166A (en) | 1985-06-04 | 1985-06-04 | Substrate for hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61279166A true JPS61279166A (en) | 1986-12-09 |
Family
ID=14800615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12101285A Pending JPS61279166A (en) | 1985-06-04 | 1985-06-04 | Substrate for hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61279166A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068199A (en) * | 1991-05-06 | 1991-11-26 | Micron Technology, Inc. | Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance |
US5290729A (en) * | 1990-02-16 | 1994-03-01 | Mitsubishi Denki Kabushiki Kaisha | Stacked type capacitor having a dielectric film formed on a rough surface of an electrode and method of manufacturing thereof |
-
1985
- 1985-06-04 JP JP12101285A patent/JPS61279166A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5290729A (en) * | 1990-02-16 | 1994-03-01 | Mitsubishi Denki Kabushiki Kaisha | Stacked type capacitor having a dielectric film formed on a rough surface of an electrode and method of manufacturing thereof |
US5068199A (en) * | 1991-05-06 | 1991-11-26 | Micron Technology, Inc. | Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance |
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