JPH05251259A - Manufacture of thin film multilayer capacitor - Google Patents

Manufacture of thin film multilayer capacitor

Info

Publication number
JPH05251259A
JPH05251259A JP4049255A JP4925592A JPH05251259A JP H05251259 A JPH05251259 A JP H05251259A JP 4049255 A JP4049255 A JP 4049255A JP 4925592 A JP4925592 A JP 4925592A JP H05251259 A JPH05251259 A JP H05251259A
Authority
JP
Japan
Prior art keywords
thin film
mask
dielectric
pattern
evaporation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4049255A
Other languages
Japanese (ja)
Inventor
Masashi Shimamoto
昌司 嶋本
Shigeru Ryuzaki
繁 粒崎
Yusuke Takada
祐助 高田
Yoshiyuki Ukishima
禎之 浮島
Shinichi Ono
信一 小野
Yukio Masuda
行男 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ulvac Inc
Panasonic Holdings Corp
Original Assignee
Ulvac Inc
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac Inc, Matsushita Electric Industrial Co Ltd filed Critical Ulvac Inc
Priority to JP4049255A priority Critical patent/JPH05251259A/en
Publication of JPH05251259A publication Critical patent/JPH05251259A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a small thin film multilayer capacitor of high capacity to be manufactured high in productivity at a low cost by a method wherein different evaporation masks are used for the formation of a dielectric body and an electrode, and the side of the evaporation mask coming into contact with an evaporation source is set smaller than the other side in dimensions. CONSTITUTION:Al is evaporated on a substrate by sputtering using a stainless steel evaporation mask 4a whose side in contact with an evaporation mask source is set smaller than other side in dimensions for the formation of a lower electrode 2a. An SiO2 thin film dielectric 3a is evaporated thereon using a different mask 4b, and furthermore an Al electrode is evaporated thereon using a different mask 4c by sputtering. At this point, the evaporation mask 4b and 4c of stainless steel are 0.05mm-1mm in the same thickness as that of the mask 4a, and the sides of them in contact with an evaporation source are set smaller than the other sides in dimension by a length of 20-50mum.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電気回路部品として用
いられる薄膜積層コンデンサの製造方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer capacitor used as an electric circuit component.

【0002】[0002]

【従来の技術】近年、表面実装技術の発達に伴い、電子
部品の小型化、チップ化の進歩はめざましいものがあ
る。そのため、コンデンサ業界でも、(1)小型、大容
量化、(2)回路の高周波化への対応、(3)耐環境性
の強化等のニーズが高まっている。
2. Description of the Related Art In recent years, with the development of surface mounting technology, there have been remarkable advances in miniaturization of electronic parts and chip formation. Therefore, in the capacitor industry as well, there is an increasing need for (1) miniaturization, large capacity, (2) response to high frequency circuits, and (3) enhancement of environmental resistance.

【0003】従来のコンデンサとしては、大容量のもの
として電解コンデンサ、小型のものとしてセラミックコ
ンデンサがあり、電気特性に優れているものとしてはフ
ィルムコンデンサ、マイカコンデンサが一般的である。
しかし、これらのコンデンサについては上述のように優
れた特性を有している反面、大容量の電解コンデンサ、
小型のセラミックコンデンサは電気特性が十分でなく、
逆に、電気特性が優れているフィルムコンデンサは小
型、大容量化が困難であるという相反した特徴を持って
いる。
Conventional capacitors include electrolytic capacitors having a large capacity and ceramic capacitors having a small size, and film capacitors and mica capacitors are generally used as capacitors having excellent electric characteristics.
However, while these capacitors have excellent characteristics as described above, large-capacity electrolytic capacitors,
Small ceramic capacitors have insufficient electrical characteristics,
On the other hand, film capacitors with excellent electrical characteristics have the contradictory characteristics that it is difficult to make them small and have a large capacity.

【0004】一般に、大容量化の方法としては、(イ)
誘電率を大きくする、(ロ)容量面積を大きくする、
(ハ)誘電体の膜厚を薄くする、の3つが考えられる。
Generally, as a method for increasing the capacity, (a)
Increase the dielectric constant, (b) increase the capacitance area,
(3) There are three possible ways to reduce the film thickness of the dielectric.

【0005】(イ)については、誘電体に、BaTiO
3、PbTiO3等の強誘電体を使用することが以前から
試みられていた。しかしながら、強誘電体を使用する方
法については、(1)薄膜形成過程で酸素を十分に供給
しないと半導体化しやすい。(2)膜厚が約1μm以下
では、誘電率が大きくならない。(3)誘電率の温度依
存性、電界依存性が大きい等の課題を有しており、さら
に、大容量化を図るために他の高い誘電率をもつ物質を
利用する方法も、技術的解決がなされていないのが現状
である。
As for (a), BaTiO 3 is used as the dielectric.
It has been attempted for a long time to use a ferroelectric substance such as 3 , PbTiO 3 . However, regarding the method of using a ferroelectric substance, (1) if oxygen is not sufficiently supplied in the thin film formation process, it is likely to become a semiconductor. (2) If the film thickness is about 1 μm or less, the dielectric constant does not increase. (3) There is a problem that the dielectric constant has a large temperature dependency and a large electric field dependency, and further, a method of utilizing another substance having a high dielectric constant in order to increase the capacity is a technical solution. The current situation is that this has not been done.

【0006】一方、コンデンサの大容量化を図るため
に、(ロ)の容量面積を大きくするという方法も有力な
手段であって、積層構造を利用するといった公知の方法
がセラミックコンデンサ、フィルムコンデンサ等で実用
化されている。
On the other hand, in order to increase the capacity of the capacitor, the method of enlarging the capacity area of (b) is also an effective means. Known methods such as utilizing a laminated structure are ceramic capacitors, film capacitors, etc. Has been put into practical use in.

【0007】また、(ハ)の誘電体の膜厚を薄くする方
法については、薄膜コンデンサに応用されている。従来
の薄膜コンデンサとしては、混成集積回路用素子として
Ta25膜を誘電体としたTMMコンデンサがよく知ら
れている。これはTa−Ta25−MnO2−Meta
lの積層構造でありTa25層と金属層との間に半導体
層としてMnO2膜をはさむことによって自己回復作用
を利用し、従来のTMコンデンサに比べコンデンサの耐
電圧を向上し、そのことで信頼性を高めている。
The method (c) of reducing the film thickness of the dielectric is applied to a thin film capacitor. As a conventional thin film capacitor, a TMM capacitor having a Ta 2 O 5 film as a dielectric is well known as a hybrid integrated circuit element. This is Ta-Ta 2 O 5 -MnO 2 -Meta
The self-healing action is utilized by sandwiching the MnO 2 film as a semiconductor layer between the Ta 2 O 5 layer and the metal layer in the laminated structure of 1 to improve the withstand voltage of the capacitor as compared with the conventional TM capacitor. That enhances reliability.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、この薄
膜コンデンサはフィルムコンデンサと同様に電気特性に
優れている反面、小型大容量化についてはまだ十分でな
く、したがって、市場ニーズに応えるためには、更に小
型大容量化が得られる(ロ)と(ハ)を組み合わせた、
すなわち、積層構造の薄膜コンデンサの実用化が必要不
可欠になっている。しかし、技術的にもコスト的にも課
題が多く、実用化までは今一歩なのが現状である。
However, while this thin film capacitor has excellent electrical characteristics like the film capacitor, it is still insufficient for miniaturization and large capacity. Therefore, in order to meet market needs, further Combining (b) and (c), which can achieve small size and large capacity,
That is, it is essential to put a thin film capacitor having a laminated structure into practical use. However, there are many problems in terms of technology and cost, and it is the current situation that it is not yet ready for practical use.

【0009】例えば、Ta25薄膜コンデンサは、誘電
体を形成するために陽極酸化法という湿式の化学処理を
行っているため、連続的なドライプロセスを生産工程に
敷くことができず、積層構造によって容量面積を大きく
するということは、技術的に実現が困難である。
For example, in a Ta 2 O 5 thin film capacitor, since a wet chemical treatment called an anodic oxidation method is performed to form a dielectric, a continuous dry process cannot be applied to a production process, and a laminated It is technically difficult to increase the capacitance area by the structure.

【0010】また、積層構造の薄膜コンデンサでは薄膜
形成手段を用いる場合、薄膜のパターン形成が必要であ
る。一般に、パターン形成法は、(A)リバースエッチ
ング法、(B)フォトエッチング法、(C)マスク法の
3つに大別される。現在、半導体素子等では微細加工に
優れた(A)や(B)の方法がさかんに利用されている
が、半導体素子に比べ一個あたりが一桁以上安価なコン
デンサ素子の作製にはこれらの二つの方法では、微細加
工が可能な反面、工程が複雑になり、コスト、生産性の
面で実用的なパターン形成方法とは言えない。
Also, in the case of a thin film capacitor having a laminated structure, when a thin film forming means is used, it is necessary to form a thin film pattern. Generally, pattern forming methods are roughly classified into three types: (A) reverse etching method, (B) photo etching method, and (C) mask method. At present, the methods (A) and (B), which are excellent in fine processing, are widely used for semiconductor elements, but these two methods are used for the production of a capacitor element which is cheaper than a semiconductor element by one digit or more. Although one of the two methods enables fine processing, it is not a practical pattern forming method in terms of cost and productivity because the process becomes complicated.

【0011】更に、フォトエッチング法等では、パター
ンエッジ部分が鋭く切れ込むため、積層数が増えるに従
い、パターンエッジ部分上に膜を形成した場合、ステッ
プカバレッジの問題が生じてしまい、その結果、コンデ
ンサ素子の電気特性に悪影響を与えてしまう。
Further, in the photo-etching method or the like, since the pattern edge portion is sharply cut, when the film is formed on the pattern edge portion as the number of laminated layers increases, a problem of step coverage occurs, and as a result, the capacitor element is formed. Adversely affect the electrical characteristics of.

【0012】[0012]

【課題を解決するための手段】上記問題点に鑑み、本発
明の薄膜積層コンデンサの製造方法は、下部電極が形成
された基板上に、ドライプロセスを利用した薄膜形成手
段を用い、誘電体と電極とを交互に少なくとも一層ずつ
積み重ねる際に、誘電体と電極のパターン形成にマスク
法を用いると共に、誘電体と電極で異なる蒸着マスクを
用い、それぞれの蒸着マスクは基体に接する側よりも蒸
発源側のパターン寸法を小さくしたことを特徴としてい
る。
In view of the above problems, a method of manufacturing a thin film multilayer capacitor according to the present invention uses a thin film forming means utilizing a dry process on a substrate having a lower electrode formed thereon, and a dielectric material. When alternately stacking at least one layer of electrodes, a mask method is used to form the pattern of the dielectric and the electrodes, and different vapor deposition masks are used for the dielectric and the electrodes. The feature is that the pattern size on the side is reduced.

【0013】[0013]

【作用】本発明は上記方法によって、薄膜コンデンサで
は実用されなかった積層構造型の薄膜コンデンサを従来
から現存するマスク法を利用することにより、可能とし
たものである。
According to the above method, the present invention enables a laminated structure type thin film capacitor, which has not been practically used in a thin film capacitor, by using the existing mask method.

【0014】マスク法を利用することにより、半導体素
子に使用されるような微細加工は困難になる反面、単純
なパターンを繰り返し積層することがきわめて簡単にな
り、同一のマスクを再利用することもできる。
The use of the mask method makes it difficult to perform microfabrication as used in semiconductor devices, but makes it easy to repeatedly stack simple patterns, and the same mask can be reused. it can.

【0015】さらに、マスク法の最大の利点は、遮蔽体
(マスク)を基体に接する側よりも蒸発源側のパターン
寸法を小さくすることができ、基体と遮蔽体(マスク)
エッジとの間に間隙を設けることができるという点にあ
る。フォトエッチング法やリバースエッチング法では基
体と遮蔽体(レジスト膜)エッジとの間に間隙がなく、
パターンエッジ部分に鋭い切れ込みが生じ、パターンが
鮮明になる。しかし、エッジ部分が鋭く切れ込んでいる
ため、その上に膜を付着させる場合には、半導体素子等
でよく言われているステップカバレッジの問題が生じて
しまう。また、マスク法でも密着させた基体と遮蔽体
(レジスト膜)エッジとの間に若干の間隙が存在するも
のの、積層するにしたがい、エッジ部分でのステップカ
バレッジの問題が無視できないようになる。そこで、パ
ターン形成にマスク法を使用し、さらに、前述のよう
に、遮蔽体(マスク)の基体に接する側よりも蒸発源側
のパターン寸法差を小さくし、基体と遮蔽体(マスク)
エッジとの間に間隙を設けることにより、付着した膜の
エッジ部分をなだらかにすると同時に、切れ込みをなく
すことができる。その結果、エッジ部分での電極の接続
問題、誘電体の絶縁破壊の問題をほとんどなくすことが
できる。
Further, the greatest advantage of the mask method is that the pattern size on the evaporation source side can be made smaller than that on the side where the shield (mask) is in contact with the substrate, and the substrate and the shield (mask).
The point is that a gap can be provided between the edge. In the photo etching method and the reverse etching method, there is no gap between the substrate and the edge of the shield (resist film),
Sharp cuts occur at the edge of the pattern and the pattern becomes clear. However, since the edge portion is sharply cut, when a film is attached thereon, the problem of step coverage, which is often said in semiconductor elements and the like, occurs. Further, even with the mask method, although there is a slight gap between the adhered substrate and the edge of the shield (resist film), the problem of step coverage at the edge cannot be ignored due to the stacking. Therefore, the mask method is used for the pattern formation, and as described above, the pattern size difference on the evaporation source side is made smaller than that on the side of the shield (mask) in contact with the base, so that the base and the shield (mask).
By providing a gap between the edge and the edge, it is possible to smooth the edge portion of the attached film and at the same time to eliminate the cut. As a result, the problem of electrode connection at the edge and the problem of dielectric breakdown of the dielectric can be almost eliminated.

【0016】[0016]

【実施例】以下本発明の一実施例に付いて、図面を参照
しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0017】図1は本実施例の薄膜積層コンデンサの基
本構成を示す素子断面図である。図1において、1は基
体となるグレイズドセラミック基板、2a,2b,2
c,2dはAl電極、3a,3b,3cは、SiO2
膜誘電体である。
FIG. 1 is an element cross-sectional view showing the basic structure of the thin film multilayer capacitor of this embodiment. In FIG. 1, reference numeral 1 is a glaze ceramic substrate 2a, 2b, 2 serving as a base.
c and 2d are Al electrodes, and 3a, 3b and 3c are SiO 2 thin film dielectrics.

【0018】次に、具体的な製造方法を図2を用いて説
明すると、あらかじめ洗浄した厚さ0.7mmのグレイズ
ドセラミック基板1の上に、まず、厚みが0.2mmであ
り、基板に接する側よりも蒸発源側のパターンの寸法が
50μm小さいステンレス製蒸着マスク4aを使用し、
Alを0.1μmの膜厚になるまでスパッタ蒸着し、下
部電極2aとした(図2(a))。次にその上部に、パ
ターンの異なるマスク4bを使用し、同様に、SiO2
薄膜誘電体3aを0.2μm、さらに、その上部に、蒸
着マスク4cを使用し、Al電極を0.1μm、いずれ
もスパッタ蒸着により形成した(図2(b),
(c))。この時、蒸着マスク4b,4cは、上記蒸着
マスク4aと同様に厚みが0.2mmであり、基板に接す
る側よりも蒸発源側のパターンの寸法が50μm小さい
ステンレス製蒸着マスクを用いた。また、基板に接する
側と蒸発源側のパターンの寸法差は湿式のテーパーエッ
チングにより設けた。以後このようにして、Al電極と
SiO2薄膜誘電体を交互に積層し、100層の薄膜積
層コンデンサAを作成した。
Next, a specific manufacturing method will be described with reference to FIG. 2. First, on the previously washed 0.7 mm-thick glaze ceramic substrate 1, the thickness is 0.2 mm. Using a stainless steel vapor deposition mask 4a in which the pattern size on the evaporation source side is 50 μm smaller than the contact side,
Al was sputter-deposited to a film thickness of 0.1 μm to form a lower electrode 2a (FIG. 2A). Next, a mask 4b having a different pattern is used on the upper portion thereof, and similarly, SiO 2 is used.
The thin film dielectric 3a was 0.2 μm, and the vapor deposition mask 4c was used on the top of the thin film dielectric 3a, and the Al electrode was 0.1 μm, both of which were formed by sputter deposition (FIG. 2 (b),
(C)). At this time, as the vapor deposition masks 4b and 4c, stainless steel vapor deposition masks having a thickness of 0.2 mm as in the vapor deposition mask 4a and having a pattern dimension of 50 μm smaller on the evaporation source side than on the side in contact with the substrate were used. The dimensional difference between the pattern in contact with the substrate and the pattern on the evaporation source side was provided by wet taper etching. Thereafter, in this manner, Al electrodes and SiO 2 thin film dielectrics were alternately laminated to form a 100-layer thin film multilayer capacitor A.

【0019】(比較例1)比較例1として蒸着マスクの
基体に接する側と蒸発源側のパターンに寸法差を設けな
い蒸着マスクを用いた以外は上記実施例と同様にして薄
膜積層コンデンサBを作成した。
(Comparative Example 1) As Comparative Example 1, a thin film multilayer capacitor B was prepared in the same manner as in the above Example except that a vapor deposition mask was used in which the pattern on the side of the vapor deposition mask in contact with the substrate and the pattern on the side of the evaporation source were not provided with a dimensional difference. Created.

【0020】(比較例2)比較例2としてフォトエッチ
ング法を用いた以外は上記実施例と同様にして薄膜積層
コンデンサCを作成した。図3はこのフォトエッチング
法を用いた薄膜積層コンデンサの基本構成を示す素子断
面図である。薄膜積層コンデンサAと同様に、1はグレ
イズドセラミック基板、2a,2b,2c,2dはAl
電極、3a,3b,3cはSiO2薄膜誘電体である。
また、フォトエッチング法に使用したレジスト膜はポジ
型のレジスト材料(東京応化(株)製OFPR−80
0)、エッチングには、ドライエッチング法を使用し
た。
Comparative Example 2 A thin film multilayer capacitor C was prepared in the same manner as in the above example except that the photo etching method was used as Comparative Example 2. FIG. 3 is an element cross-sectional view showing the basic structure of a thin film multilayer capacitor using this photoetching method. Similar to the thin film multilayer capacitor A, 1 is a glaze ceramic substrate, 2a, 2b, 2c and 2d are Al.
The electrodes 3a, 3b, 3c are SiO 2 thin film dielectrics.
The resist film used in the photoetching method is a positive resist material (OFPR-80 manufactured by Tokyo Ohka Co., Ltd.).
0), the dry etching method was used for etching.

【0021】これらの積層薄膜コンデンサを各々100
個ずつ作成したところ、電気検査の歩留りは(表1)に
示す値となった。
Each of these multilayer thin film capacitors is 100
When they were created one by one, the yield of electrical inspection was the value shown in (Table 1).

【0022】[0022]

【表1】 [Table 1]

【0023】次に、耐電圧(昇圧破壊)、誘電正接の測
定、充放電試験に上記薄膜積層コンデンサA,B,Cの
おのおの良品10個ずつ、投入した。その結果を(表
2)に示す。
Next, 10 good products of each of the thin film multilayer capacitors A, B and C were put into a withstand voltage (voltage breakdown) measurement, a dielectric loss tangent measurement and a charge / discharge test. The results are shown in (Table 2).

【0024】[0024]

【表2】 [Table 2]

【0025】以上の結果より、蒸着マスクの基体に接す
る側と蒸発源側のパターンに寸法差を設けた蒸着マスク
を用いて作成した薄膜積層コンデンサが最も優れた特性
を有しており、生産歩留り、電気特性の両面で優位であ
ることは明らかである。
From the above results, the thin film multilayer capacitor produced by using the vapor deposition mask in which the pattern on the side of the vapor deposition mask in contact with the substrate and the pattern on the side of the evaporation source are provided with the dimensional difference has the most excellent characteristics, and the production yield is improved. However, it is clear that it is superior in terms of both electrical characteristics.

【0026】本実施例では、厚みが0.2mmであり、基
板に接する側よりも蒸発源側のパターンの寸法が50μ
m小さいステンレス製蒸着マスクを用いたが、厚みが
0.05mmに満たない場合、あるいは基体に接する側と
蒸発源側のパターンの寸法差が20μmに満たない場合
には基体と遮蔽体(マスク)エッジとの間に間隙を設け
た効果がなくなり、逆に、厚みが1mmを越える場合、あ
るいは基体に接する側と蒸発源側のパターンの寸法差が
500μmを越える場合には目的に沿った微細加工がで
きず、市場ニーズにあった薄膜積層コンデンサを提供す
ることができないため、蒸着マスクの厚みは0.05mm
以上1mm以下であり、基体に接する側よりも蒸発源側の
パターンの寸法を20μm以上500μm以下の範囲で
小さくすることが必要である。
In this embodiment, the thickness is 0.2 mm, and the dimension of the pattern on the evaporation source side is 50 μm from the side in contact with the substrate.
A stainless steel vapor deposition mask with a small size was used, but if the thickness is less than 0.05 mm, or if the dimensional difference between the pattern in contact with the substrate and the evaporation source side is less than 20 μm, the substrate and the shield (mask) The effect of providing a gap between the edges disappears, and conversely, when the thickness exceeds 1 mm, or when the dimension difference between the pattern in contact with the substrate and the evaporation source side exceeds 500 μm, fine processing according to the purpose Since it is not possible to provide thin film multilayer capacitors that meet market needs, the thickness of the evaporation mask is 0.05 mm.
It is 1 mm or less, and it is necessary to reduce the dimension of the pattern on the evaporation source side from the side in contact with the substrate within the range of 20 μm to 500 μm.

【0027】なお、本発明を説明するにあたって、誘電
体薄膜にSiO2を使用したが、他の無機薄膜誘電体材
料、あるいは、有機薄膜誘電体材料を用いても同様の結
果が得られるのは言うまでもない。
Although SiO 2 is used for the dielectric thin film in the explanation of the present invention, similar results can be obtained even if another inorganic thin film dielectric material or organic thin film dielectric material is used. Needless to say.

【0028】また、電極材料はAlに限るものではな
い。また、上記実施例では、スパッタリング法により薄
膜形成を行ったが、他の薄膜形成法でも同様の結果が得
られることは言うまでもない。
The electrode material is not limited to Al. Further, in the above-mentioned embodiment, the thin film was formed by the sputtering method, but it goes without saying that similar results can be obtained by other thin film forming methods.

【0029】[0029]

【発明の効果】本発明は上記実施例より明らかなよう
に、基体上にドライプロセスを利用した薄膜形成手段を
用いて誘電体と電極とを交互に少なくとも一層ずつ積み
重ねる際に、誘電体と電極のパターン形成にマスク法を
用いると共に、誘電体と電極で異なる蒸着マスクを用
い、それぞれの蒸着マスクの厚みが0.05mm以上1mm
以下であり、基体に接する側よりも蒸発源側のパターン
の寸法差が20μm以上500μm以下の範囲で小さく
することにより、付着した膜のエッジ部分をなだらかに
すると同時に、切れ込みをなくすことができる。その結
果、エッジ部分での電極の接続問題、誘電体の絶縁破壊
の問題をほとんどなくすことができ、小型で大容量の薄
膜積層コンデンサを低コストで生産性よく提供すること
が可能となる。
As is apparent from the above-described embodiments, the present invention provides a method of forming a dielectric and an electrode on a substrate by alternately stacking at least one layer of the dielectric and the electrode by using a thin film forming means utilizing a dry process. The mask method is used to form the pattern, and different vapor deposition masks are used for the dielectric and the electrodes, and the thickness of each vapor deposition mask is 0.05 mm or more and 1 mm.
It is as follows, and by making the dimensional difference of the pattern on the evaporation source side smaller than that on the side in contact with the substrate within the range of 20 μm or more and 500 μm or less, the edge portion of the attached film can be smoothed and the cut can be eliminated. As a result, the problem of electrode connection at the edge portion and the problem of dielectric breakdown of the dielectric can be almost eliminated, and a small-sized and large-capacity thin film multilayer capacitor can be provided at low cost with high productivity.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における薄膜積層コンデンサ
の基本構成を示す素子断面図
FIG. 1 is an element cross-sectional view showing the basic structure of a thin film multilayer capacitor in one embodiment of the present invention.

【図2】本実施例の製造工程を示した図であって、 (a)は下部電極を形成する工程図 (b)は下部電極の上に薄膜誘電体を形成する工程図 (c)は薄膜誘電体の上にAl電極を形成する工程図FIG. 2 is a diagram showing a manufacturing process of the present embodiment, in which (a) is a process diagram for forming a lower electrode, (b) is a process diagram for forming a thin film dielectric on the lower electrode, and (c) is a process diagram. Process drawing of forming Al electrode on thin film dielectric

【図3】本比較例のフォトエッチング法を用いた薄膜積
層コンデンサの基本構成を示す素子断面図
FIG. 3 is an element cross-sectional view showing the basic structure of a thin film multilayer capacitor using a photo-etching method of this comparative example.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2a〜2d Al電極 3a〜3c SiO2薄膜誘電体 4a〜4c 蒸着マスク1 ceramic substrate 2 a to 2 d Al electrodes 3 a to 3 c SiO 2 thin film dielectric 4a~4c deposition mask

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高田 祐助 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 浮島 禎之 神奈川県茅ケ崎市萩園2500番地 日本真空 技術株式会社内 (72)発明者 小野 信一 神奈川県茅ケ崎市萩園2500番地 日本真空 技術株式会社内 (72)発明者 増田 行男 神奈川県茅ケ崎市萩園2500番地 日本真空 技術株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yusuke Takada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. ) Inventor Shinichi Ono 2500 Hagizono, Chigasaki City, Kanagawa Japan Vacuum Technology Co., Ltd. (72) Inventor Yukio Masuda 2500 Hagien, Chigasaki City, Kanagawa Japan Vacuum Technology Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基体上にドライプロセスを利用した薄膜形
成手段を用いて誘電体と電極とを交互に少なくとも一層
ずつ積み重ねる際に、前記誘電体と電極のパターン形成
にマスク法を用いると共に、前記誘電体と電極で異なる
蒸着マスクを用い、それぞれの蒸着マスクは前記基体に
接する側よりも蒸発源側のパターン寸法を小さくしたこ
とを特徴とする薄膜積層コンデンサの製造方法。
1. A mask method is used to form a pattern of the dielectric and the electrode when alternately stacking at least one layer of the dielectric and the electrode by using a thin film forming means utilizing a dry process on the substrate, and A method of manufacturing a thin film multilayer capacitor, wherein different vapor deposition masks are used for a dielectric and an electrode, and each vapor deposition mask has a smaller pattern size on the evaporation source side than on the side in contact with the substrate.
【請求項2】前記蒸着マスクの厚みが0.05mm以上1
mm以下であり、基体に接する側と蒸発源側のパターンの
寸法差が20μm以上500μm以下であることを特徴
とする請求項1記載の薄膜積層コンデンサの製造方法。
2. The thickness of the vapor deposition mask is 0.05 mm or more 1
2. The method for manufacturing a thin film multilayer capacitor according to claim 1, wherein the dimension difference between the pattern in contact with the substrate and the pattern on the evaporation source side is 20 μm or more and 500 μm or less.
JP4049255A 1992-03-06 1992-03-06 Manufacture of thin film multilayer capacitor Pending JPH05251259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4049255A JPH05251259A (en) 1992-03-06 1992-03-06 Manufacture of thin film multilayer capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4049255A JPH05251259A (en) 1992-03-06 1992-03-06 Manufacture of thin film multilayer capacitor

Publications (1)

Publication Number Publication Date
JPH05251259A true JPH05251259A (en) 1993-09-28

Family

ID=12825732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4049255A Pending JPH05251259A (en) 1992-03-06 1992-03-06 Manufacture of thin film multilayer capacitor

Country Status (1)

Country Link
JP (1) JPH05251259A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005517810A (en) * 2002-02-14 2005-06-16 スリーエム イノベイティブ プロパティズ カンパニー In-line deposition for circuit manufacturing
JP2013028835A (en) * 2011-07-28 2013-02-07 Kyocera Crystal Device Corp Film formation method
JP2014067850A (en) * 2012-09-26 2014-04-17 Institute Of National Colleges Of Technology Japan Manufacturing apparatus for capacitor and manufacturing method for multilayer capacitor
RU2669259C2 (en) * 2016-12-09 2018-10-09 Федеральное государственное автономное образовательное учреждение высшего образования "Уральский федеральный университет имени первого Президента России Б.Н. Ельцина" Device for producing films

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005517810A (en) * 2002-02-14 2005-06-16 スリーエム イノベイティブ プロパティズ カンパニー In-line deposition for circuit manufacturing
JP2013028835A (en) * 2011-07-28 2013-02-07 Kyocera Crystal Device Corp Film formation method
JP2014067850A (en) * 2012-09-26 2014-04-17 Institute Of National Colleges Of Technology Japan Manufacturing apparatus for capacitor and manufacturing method for multilayer capacitor
RU2669259C2 (en) * 2016-12-09 2018-10-09 Федеральное государственное автономное образовательное учреждение высшего образования "Уральский федеральный университет имени первого Президента России Б.Н. Ельцина" Device for producing films

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