JP2736362B2 - Method for manufacturing capacitor of microwave integrated circuit - Google Patents

Method for manufacturing capacitor of microwave integrated circuit

Info

Publication number
JP2736362B2
JP2736362B2 JP9405989A JP9405989A JP2736362B2 JP 2736362 B2 JP2736362 B2 JP 2736362B2 JP 9405989 A JP9405989 A JP 9405989A JP 9405989 A JP9405989 A JP 9405989A JP 2736362 B2 JP2736362 B2 JP 2736362B2
Authority
JP
Japan
Prior art keywords
metal wiring
insulating film
metal
capacitor
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9405989A
Other languages
Japanese (ja)
Other versions
JPH02271563A (en
Inventor
祐記 今井
孝之 菅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9405989A priority Critical patent/JP2736362B2/en
Publication of JPH02271563A publication Critical patent/JPH02271563A/en
Application granted granted Critical
Publication of JP2736362B2 publication Critical patent/JP2736362B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明はマイクロ波集積回路に於けるキャパシタの
製造方法に関するものである。
The present invention relates to a method for manufacturing a capacitor in a microwave integrated circuit.

「従来の技術」 従来の代表的なマイクロ波集積回路のキャパシタ製造
方法を第3図に示す。以下、第3図に従ってその製造方
法を説明する。まずガリウムひ素(GaAs)などの半絶縁
性基板やSiO2などの絶縁性基板1の上にリフトオフ法な
どによりAuなどの第1の金属配線2を形成する(第3図
(a))。次にSiO2やSi3N4などの第1の絶縁膜3をた
とえばプラズマCVD法などにより全面に形成した後、第
1の金属配線2上の第1の絶縁膜3の一部を選択的に除
去し、除去した部分にリフトオフ法などによりAuなどか
らなる第1の金属接続柱4を形成する(第3図
(b))。
[Prior Art] FIG. 3 shows a conventional typical method for manufacturing a capacitor of a microwave integrated circuit. Hereinafter, the manufacturing method will be described with reference to FIG. First, a first metal wiring 2 such as Au is formed on a semi-insulating substrate such as gallium arsenide (GaAs) or an insulating substrate 1 such as SiO 2 by a lift-off method or the like (FIG. 3A). Next, after a first insulating film 3 such as SiO 2 or Si 3 N 4 is formed on the entire surface by, eg, plasma CVD, a part of the first insulating film 3 on the first metal wiring 2 is selectively formed. The first metal connection pillar 4 made of Au or the like is formed on the removed portion by a lift-off method or the like (FIG. 3B).

次にAuなどから構成される第2の金属配線5をスパッ
タ法などにより形成し、その上に一部が開孔したフォト
レジスタ6を通常のフォトリソグラフィー工程により形
成する(第3図(c))。次にフォトレジスタ6をマス
クとしてArイオンなどを用いたイオンビームマッチング
などにより第2の金属配線5を選択的に除去して第1の
金属接続柱4に接続された部分を分離した後、フォトレ
ジスト6を溶剤により除去し、次にSiO2やSi3N4などの
第2の絶縁膜7をプラズマCVD法などにより形成する第
3図(d))。
Next, a second metal wiring 5 made of Au or the like is formed by a sputtering method or the like, and a photoresist 6 partially opened is formed thereon by a normal photolithography process (FIG. 3C). ). Next, the second metal wiring 5 is selectively removed by ion beam matching or the like using Ar ions or the like with the photoresist 6 as a mask to separate the portion connected to the first metal connection column 4. The resist 6 is removed by a solvent, and then a second insulating film 7 such as SiO 2 or Si 3 N 4 is formed by a plasma CVD method or the like (FIG. 3D).

次に第2の金属配線5の第1の金属接続柱4と接続さ
れた部分と接続する第2の金属接続柱8を第2の絶縁膜
7中に第1の金属接続柱4と同様な方法により形成し、
その後第3の金属配線9を第2の金属配線5と同様な方
法により形成する(第3図(e))。
Next, a second metal connecting column 8 connected to a portion of the second metal wiring 5 connected to the first metal connecting column 4 is formed in the second insulating film 7 in the same manner as the first metal connecting column 4. Formed by the method,
Thereafter, a third metal wiring 9 is formed by the same method as that for the second metal wiring 5 (FIG. 3E).

第3図(e)の構造に於いて第1の金属配線2は第1
の金属接続柱4、第2の金属配線5の一部、第2の金属
接続柱8を介して第3の金属配線9と接続されている。
第1の金属配線2あるいは第3の金属配線9を第1の電
極とし、第2の金属配線5を第2の電極とし、第1の金
属配線2と第2の金属配線5との交叉部分の第1の絶縁
膜10と、第2の金属配線5と第3の金属配線9との交叉
部分の第2の絶縁膜11とを誘電体とすることにより金属
電極/誘電体/金属電極からなるキャパシタが構成され
る。
In the structure of FIG. 3E, the first metal wiring 2 is
And a part of the second metal wiring 5, and the third metal wiring 9 via the second metal connection pillar 8.
The first metal wiring 2 or the third metal wiring 9 is used as a first electrode, the second metal wiring 5 is used as a second electrode, and the intersection of the first metal wiring 2 and the second metal wiring 5 The first insulating film 10 and the second insulating film 11 at the intersection of the second metal wiring 5 and the third metal wiring 9 are made of a dielectric material so that the metal electrode / dielectric / metal electrode Is formed.

「発明が解決しようとする課題」 以上、説明した従来のキャパシタ製造方法では、第2
の金属配線5をマイクロ波集積回路を構成する各素子を
結合する配線としても利用するため、その配線抵抗を下
げるため配線厚さを1μm以上に厚くし、一方、第2の
絶縁膜7はキャパシタの容量を大きくとるため0.3〜0.5
μm程度に薄くする必要がある。このため第2の絶縁膜
7をプラズマCVD法やスパッタ法などの通常の方法で形
成した場合、形成する絶縁膜の厚みに対して第2の金属
配線5の側壁部の高さが大きいので第2の金属配線5の
側壁部に付着する絶縁膜の堆積速度が遅く、この部分の
絶縁膜12の厚みが薄くなり、更に側壁部の膜の密度が下
がる等の膜質の劣化が生ずる場合(第1図(e))やあ
るいは第4図に示すように第2の金属配線5の側壁部に
第2の絶縁膜7が付着せず第2の金属配線5と第3の金
属配線9とが接触する部分13が発生する場合がある。こ
のため前者の場合ではキャパシタの電気的耐圧が低下
し、又、後者の場合では電気的に短絡し、容量として働
かないという問題があった。
[Problem to be Solved by the Invention] In the conventional capacitor manufacturing method described above,
In order to reduce the wiring resistance, the wiring thickness is increased to 1 μm or more in order to use the metal wiring 5 as a wiring connecting the elements constituting the microwave integrated circuit. 0.3 to 0.5 to increase the capacity of
It is necessary to reduce the thickness to about μm. Therefore, when the second insulating film 7 is formed by a normal method such as a plasma CVD method or a sputtering method, the height of the side wall of the second metal wiring 5 is larger than the thickness of the formed insulating film. In the case where the deposition rate of the insulating film attached to the side wall of the second metal wiring 5 is low, the thickness of the insulating film 12 in this portion is reduced, and the film quality is deteriorated such that the density of the film in the side wall is further reduced (No. As shown in FIG. 1 (e) or FIG. 4, the second insulating film 7 does not adhere to the side wall of the second metal wiring 5, and the second metal wiring 5 and the third metal wiring 9 are separated. A contact portion 13 may occur. Therefore, in the former case, the electric breakdown voltage of the capacitor is reduced, and in the latter case, there is a problem that the capacitor is electrically short-circuited and does not work as a capacitor.

この発明の目的は電気的耐圧力が大きく、電気的短絡
によるキャパシタの歩留り低下のないマイクロ波集積回
路のキャパシタ製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor for a microwave integrated circuit, which has a high electric withstand pressure and does not lower the yield of the capacitor due to an electric short circuit.

「課題を解決するための手段」 この発明によれば第2の絶縁膜に第2の金属接続柱を
形成した後に、第2の金属配線の縁の部分でかつ第3の
金属配線と交叉すべき部分に第3の絶縁膜を形成し、そ
の後に第3の金属配線を形成し、次にこの第3の絶縁膜
を除去する。
[Means for Solving the Problems] According to the present invention, after forming the second metal connection pillar on the second insulating film, the second metal connection pillar intersects with the third metal wiring at the edge of the second metal wiring. A third insulating film is formed on a portion to be formed, then a third metal wiring is formed, and then the third insulating film is removed.

「実施例」 この発明によるマイクロ波集積回路のキャパシタ製造
方法の実施例を第1図に示し、第3図と対応する部分に
は同一符号を付けてある。まず従来の工程(第3図
(a)〜(d))と同様な工程により半絶縁性あるいは
絶縁性基板1上に第1の金属配線2、第1の絶縁膜3、
第1の金属接続柱4、第2の金属配線5、第2の絶縁膜
7、第2の金属接続柱8を形成する。
"Embodiment" An embodiment of a method for manufacturing a capacitor of a microwave integrated circuit according to the present invention is shown in FIG. 1, and portions corresponding to those in FIG. 3 are denoted by the same reference numerals. First, a first metal wiring 2, a first insulating film 3, a first insulating film 3, and a semi-insulating or insulating substrate 1 are formed on a semi-insulating or insulating substrate 1 by the same steps as the conventional steps (FIGS.
The first metal connection pillar 4, the second metal wiring 5, the second insulating film 7, and the second metal connection pillar 8 are formed.

次にこの発明ではフォトレジストなどの第3の絶縁膜
14を通常のフォトリソグラフィー工程により第2の金属
配線5の縁の部分に形成する(第1図(a))。次に必
要に応じてAuなどからなる金属膜15をスパッタ法などに
より全面に0.1μm程度形成した後、この金属膜15を導
電層としてたとえば電解メッキ法などによりAuなどから
なる第3の金属配線9を2〜3μm程度全面に形成する
(第1図(b))。次に通常のフォトリソグラフィー工
程などによりフォトレジスト16を形成する(第1図
(c))。次にこのフォトレジスト16をマスクとしてた
とえばArイオンを用いたイオンビームエッチングなどに
より第3の金属配線9及び金属膜15をエッチングして第
2の絶縁膜7の一部及び第3の絶縁膜14の一部を露出
し、フォトレジスト16を溶剤により除去した後、第3の
絶縁膜14をたとえば酸素ガスを用いたプラズマエッチン
グにより除去する(第1図(d))。
Next, in the present invention, a third insulating film such as a photoresist
14 is formed at the edge of the second metal wiring 5 by a normal photolithography process (FIG. 1A). Next, if necessary, a metal film 15 made of Au or the like is formed on the entire surface to a thickness of about 0.1 μm by a sputtering method or the like, and then the third metal wiring made of Au or the like is used as a conductive layer by, for example, an electrolytic plating method. 9 is formed on the entire surface of about 2 to 3 μm (FIG. 1B). Next, a photoresist 16 is formed by a normal photolithography process or the like (FIG. 1C). Next, using the photoresist 16 as a mask, the third metal wiring 9 and the metal film 15 are etched by ion beam etching using, for example, Ar ions, so that a part of the second insulating film 7 and the third insulating film 14 are formed. Is exposed and the photoresist 16 is removed by a solvent, and then the third insulating film 14 is removed by, for example, plasma etching using oxygen gas (FIG. 1 (d)).

以上説明した工程により、第2の金属配線5と第3の
金属配線9とは、第2の金属配線5の縁の部分で空間17
により電気的に分離される。このため側壁部の絶縁膜12
の厚みや膜質に依存せずキャパシタの電気的耐圧が高い
という特徴を有する。又、第2図に示す様に第2の金属
配線5が第2の絶縁膜7により完全に被覆されず露出部
18が生じた場合でもキャパシタの電気的短絡を防ぐこと
が出来るという特徴を有する。従ってキャパシタの電気
的や耐圧や歩留りを従来に比べ極めて向上できるという
利点をもつ。
By the above-described steps, the second metal wiring 5 and the third metal wiring 9 are separated from each other by the space 17 at the edge of the second metal wiring 5.
Is electrically separated by Therefore, the insulating film 12 on the side wall
Has the characteristic that the electric breakdown voltage of the capacitor is high irrespective of the thickness and film quality of the capacitor. Further, as shown in FIG. 2, the second metal wiring 5 is not completely covered with the second insulating
The feature is that even if 18 occurs, electrical short-circuiting of the capacitor can be prevented. Therefore, there is an advantage that the electrical, withstand voltage and yield of the capacitor can be significantly improved as compared with the conventional case.

「発明の効果」 以上説明したようにこの発明によるマイクロ波集積回
路のキャパシタ製造方法によれば、キャパシタの電気的
耐圧が増加し、電気的短絡も生じず電気的歩留りも増加
するため、特に1GHz帯などの比較的低周波の回路で大き
な容量値のキャパシタを多数必要とする場合に、その電
気的性能が向上するという利点をもつ。また第3の絶縁
膜14を除去しているため、この部分の寄生容量がなく、
容量が電極間の対向面積で決る設計通りのものを容易に
得ることができる。前述の例のように薄い金属膜15を形
成した後に、電解メッキ法により第3の金属配線9を形
成する場合は第3の絶縁膜14により大きな凹凸となって
いても第3の金属配線9を各部正確に厚く付けることが
できる。
[Effects of the Invention] As described above, according to the method for manufacturing a capacitor of a microwave integrated circuit according to the present invention, the electrical breakdown voltage of the capacitor increases, the electrical short-circuit does not occur, and the electrical yield increases. When a relatively low frequency circuit such as a band requires a large number of capacitors having a large capacitance value, there is an advantage that the electrical performance is improved. Also, since the third insulating film 14 has been removed, there is no parasitic capacitance at this portion.
It is possible to easily obtain a capacitor whose design is determined by the facing area between the electrodes. When the third metal wiring 9 is formed by the electrolytic plating method after forming the thin metal film 15 as in the above-described example, the third metal wiring 9 is formed even if the third insulating film 14 has large irregularities. Can be accurately and thickly applied to each part.

【図面の簡単な説明】[Brief description of the drawings]

第1図はこの発明のキャパシタ製造方法の工程の要部を
示す断面図、第2図はこの発明の効果を説明するための
断面図、第3図は従来のキャパシタ製造方法の工程を示
す断面図、第4図は従来の問題点を説明するための断面
図である。
FIG. 1 is a cross-sectional view showing a main part of a process of the capacitor manufacturing method of the present invention, FIG. 2 is a cross-sectional view for explaining the effect of the present invention, and FIG. FIG. 4 is a cross-sectional view for explaining a conventional problem.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁性あるいは半絶縁性基板上に第1の金
属配線、第1の絶縁膜、第2の金属配線、第2の絶縁
膜、第3の金属配線を順次多層に形成し、上記第1の絶
縁膜及び上記第2の絶縁膜中に、上記第1の金属配線と
上記第3の金属配線を上記第2の金属配線の一部を介し
て接続する第1,第2の金属接続柱をそれぞ形成し、上記
第1の金属配線あるいは上記第3の金属配線を第1の電
極とし、上記第2の金属配線を第2の電極とし、上記第
1の金属配線と上記第2の金属配線との交叉部分にはさ
まれた上記第1の絶縁膜と、上記第2の金属配線と上記
第3の金属配線との交叉部分にはさまれた上記第2の絶
縁膜とを誘電体とする金属電極/誘導体/金属電極から
なるキャパシタを含むマイクロ波集積回路のキャパシタ
製造方法に於いて、 上記第1の金属配線、上記第1の絶縁膜、上記第2の金
属配線、上記第2の絶縁膜、上記第1,第2の金属絶縁柱
を形成した工程の後に、上記第2の金属配線の縁の部分
で上記第3の金属配線と交叉すべき部分に、第3の絶縁
膜を形成し、その後上記第3の金属配線を形成し、次に
上記第3の絶縁膜を他の絶縁膜を対して選択的に除去す
ることを特徴としたマイクロ波集積回路のキャパシタ製
造方法。
A first metal wiring, a first insulating film, a second metal wiring, a second insulating film, and a third metal wiring are sequentially formed in multiple layers on an insulating or semi-insulating substrate; First and second connecting the first metal wiring and the third metal wiring via a part of the second metal wiring in the first insulating film and the second insulating film. Metal connection pillars are respectively formed, the first metal wiring or the third metal wiring is used as a first electrode, the second metal wiring is used as a second electrode, and the first metal wiring and the first metal wiring are connected to each other. The first insulating film sandwiched between the intersections of the second metal wiring and the second insulating film sandwiched between the intersections of the second metal wiring and the third metal wiring; A method for manufacturing a capacitor of a microwave integrated circuit including a capacitor comprising a metal electrode / derivative / metal electrode having After the step of forming the first metal wiring, the first insulating film, the second metal wiring, the second insulating film, and the first and second metal insulating columns, the second metal A third insulating film is formed at a portion of the wiring that should cross the third metal wiring, and then the third metal wiring is formed. A method for manufacturing a capacitor of a microwave integrated circuit, comprising selectively removing an insulating film.
JP9405989A 1989-04-12 1989-04-12 Method for manufacturing capacitor of microwave integrated circuit Expired - Fee Related JP2736362B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9405989A JP2736362B2 (en) 1989-04-12 1989-04-12 Method for manufacturing capacitor of microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9405989A JP2736362B2 (en) 1989-04-12 1989-04-12 Method for manufacturing capacitor of microwave integrated circuit

Publications (2)

Publication Number Publication Date
JPH02271563A JPH02271563A (en) 1990-11-06
JP2736362B2 true JP2736362B2 (en) 1998-04-02

Family

ID=14099965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9405989A Expired - Fee Related JP2736362B2 (en) 1989-04-12 1989-04-12 Method for manufacturing capacitor of microwave integrated circuit

Country Status (1)

Country Link
JP (1) JP2736362B2 (en)

Also Published As

Publication number Publication date
JPH02271563A (en) 1990-11-06

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