JPS627699B2 - - Google Patents
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- Publication number
- JPS627699B2 JPS627699B2 JP7735779A JP7735779A JPS627699B2 JP S627699 B2 JPS627699 B2 JP S627699B2 JP 7735779 A JP7735779 A JP 7735779A JP 7735779 A JP7735779 A JP 7735779A JP S627699 B2 JPS627699 B2 JP S627699B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- organic compound
- sio
- semiconductor device
- cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 22
- 150000002894 organic compounds Chemical class 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000011282 treatment Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 59
- 229910004298 SiO 2 Inorganic materials 0.000 description 55
- 239000010410 layer Substances 0.000 description 38
- 239000011229 interlayer Substances 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011261 inert gas Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910001415 sodium ion Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- NEHMKBQYUWJMIP-UHFFFAOYSA-N chloromethane Chemical compound ClC NEHMKBQYUWJMIP-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置及びその製造方法に関
し、特に半導体装置の多層配線に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to multilayer wiring of a semiconductor device.
従来、半導体装置において多層配線を行なう場
合、層間絶縁膜として堆積被膜例えば気相成長
（CVD）法によるCVD−SiO2膜が用いられてき
た。しかし、層間絶縁膜としてCVD−SiO2膜を
用いて多層配線を行なつた場合、下地に段差部
（例えば一層目の電極配線の段差部あるいはフイ
ールドSiO2膜の段差部等）がある半導体基板上
にCVD−SiO2膜を形成すると、段差部上のCVD
−SiO2膜がオーバーハングになり、より急峻な
傾斜をもつ段差がCVD−SiO2膜にもできる。こ
のような段差のあるCVD−SiO2膜上に二層目の
電極配線を形成すると、前記段差部で電極配線の
断線が起こつたり、あるいは、段差部側面の
CVD−SiO2膜が薄くなりピンホール等の欠陥が
多発し、一層目と二層目の電極配線がシヨートし
たりして歩留りを著しく下げる問題があつた。 Conventionally, when performing multilayer wiring in a semiconductor device, a deposited film such as a CVD-SiO 2 film formed by vapor phase deposition (CVD) has been used as an interlayer insulating film. However, when multilayer interconnection is performed using a CVD-SiO 2 film as an interlayer insulating film, a semiconductor substrate with a step part (for example, a step part of the first layer electrode wiring or a step part of the field SiO 2 film, etc.) in the underlying layer may be used. When a CVD-SiO 2 film is formed on top, the CVD on the stepped part
-The SiO 2 film becomes overhanging, and a step with a steeper slope is also formed in the CVD-SiO 2 film. If a second layer of electrode wiring is formed on a CVD-SiO 2 film with such a step, the electrode wiring may break at the step, or the side surface of the step may become disconnected.
As the CVD-SiO 2 film became thinner, defects such as pinholes occurred frequently, and the electrode wiring in the first and second layers was shot, which significantly lowered the yield.
そこで、層間絶縁膜として有機被膜を用いた半
導体装置がたとえば特開昭51−69378号にて提案
されており、この構造を第１図を用いて説明す
る。 Therefore, a semiconductor device using an organic film as an interlayer insulating film has been proposed, for example, in Japanese Patent Laid-Open No. 51-69378, and the structure thereof will be explained with reference to FIG.
選択拡散法により拡散層２，３が形成された半
導体基板１上にコンタクトホールの形成された
SiO2膜４が形成されており、前記SiO2膜４のコ
ンタクトホールを通じて拡散層２，３の電極とな
る一層目の配線５がSiO2膜４上に形成されてお
り、前記一層目の配線５およびSiO2膜４上に層
間絶縁膜となる所望の窓を有するイオン注入され
た有機被膜（ホトレジスト膜）６が形成されてお
り、前記有機被膜６の窓により一層目の配線５に
通じる二層目の配線７が有機被膜６上に形成され
た構造からなる半導体装置である。 A contact hole is formed on a semiconductor substrate 1 on which diffusion layers 2 and 3 are formed by a selective diffusion method.
A SiO 2 film 4 is formed, and a first layer wiring 5 that becomes the electrodes of the diffusion layers 2 and 3 is formed on the SiO 2 film 4 through a contact hole in the SiO 2 film 4. 5 and the SiO 2 film 4, an ion-implanted organic film (photoresist film) 6 having a desired window to serve as an interlayer insulating film is formed. This is a semiconductor device having a structure in which a layer of wiring 7 is formed on an organic film 6.
しかし、上記の構造においては、一層目の配線
５上に直接ホトレジスト膜６が形成されているた
め、ホトレジスト膜６中のNa+イオン等の可動イ
オンによる半導体基板１への汚染が問題となる。 However, in the above structure, since the photoresist film 6 is formed directly on the first layer wiring 5, contamination of the semiconductor substrate 1 by mobile ions such as Na + ions in the photoresist film 6 becomes a problem.
また、ホトレジスト膜６を半導体基板１上に塗
布しプリベークなどの熱処理を施すと流動して、
ホトレジストの膜厚は下地が凸部の箇所は薄く、
凹部の箇所は厚く形成される。そのため、ホトレ
ジスト膜６の膜厚が薄くなる例えば一層目の配線
５上のホトレジスト膜６にはピンホールが発生
し、一層目の配線５とクロスするように二層目の
配線６を行なうとシヨートしたり、あるいは、ホ
トレジスト膜６は誘電体であるため、コンデンサ
になつたりして歩留りを下げたり、半導体素子に
悪い影響をおよぼす要因となる。また、ホトレジ
スト膜６にイオン注入を施すことによつて耐熱性
は向上するが、完全には硬化していないため、二
層目の配線を行なつた後、保護膜としてCVD−
SiO2膜を形成すると、CVD−SiO2膜の形成温度
が高い（約350〜450℃程度）ため、ホトレジスト
膜６の未硬化の部分が流動する。そのため、ホト
レジスト膜６上の二層目の配線７が断線したり、
パターンくずれをおこしたりする。 Furthermore, when the photoresist film 6 is applied onto the semiconductor substrate 1 and subjected to heat treatment such as prebaking, it flows.
The photoresist film thickness is thinner where the underlying surface is convex.
The concave portion is formed thickly. Therefore, the film thickness of the photoresist film 6 becomes thinner, for example, pinholes are generated in the photoresist film 6 on the first layer wiring 5, and if the second layer wiring 6 is formed so as to cross the first layer wiring 5, shorts may occur. Alternatively, since the photoresist film 6 is a dielectric, it may become a capacitor, lowering the yield or having a negative effect on the semiconductor device. Although heat resistance is improved by ion implantation into the photoresist film 6, since it is not completely cured, CVD-
When the SiO 2 film is formed, the uncured portion of the photoresist film 6 flows because the formation temperature of the CVD-SiO 2 film is high (approximately 350 to 450° C.). Therefore, the second layer wiring 7 on the photoresist film 6 may be disconnected, or
This may cause pattern distortion.
したがつて、本発明の目的は、ほぼ平坦な表面
を有し、しかも、無機質の絶縁膜と有機質の絶縁
膜からなる積層膜を用いることによつて、電極配
線の断線や層間のシヨートがなく歩留りの良い多
層配線を有する半導体装置及びその製造方法を提
供することである。 Therefore, an object of the present invention is to eliminate disconnections in electrode wiring and shorts between layers by using a laminated film that has a substantially flat surface and is composed of an inorganic insulating film and an organic insulating film. An object of the present invention is to provide a semiconductor device having multilayer wiring with high yield and a method for manufacturing the same.
すなわち、本発明は多層配線の層間絶縁膜とし
て無機質の堆積被膜と前記堆積被膜の凹部上に形
成した有機質の完全に硬化した有機化合物膜の２
層からなる積層膜、あるいは、無機質の堆積被膜
と前記堆積被膜上に形成した有機質の完全に硬化
した有機化合物膜と前記有機化合物膜及び前記無
機質の堆積膜上に形成した第２の無機質の堆積被
膜の３層からなる積層膜を用いることを特徴とす
る半導体装置及びその製造方法である。 That is, the present invention uses two inorganic deposited films and a completely cured organic compound film formed on the recesses of the deposited film as interlayer insulating films for multilayer wiring.
A laminated film consisting of layers, or an inorganic deposited film, an organic completely cured organic compound film formed on the deposited film, and a second inorganic deposited film formed on the organic compound film and the inorganic deposited film. A semiconductor device and a method for manufacturing the same characterized by using a laminated film consisting of three layers of films.
本発明は、完全に硬化したホトレジスト膜等の
有機化合物膜と無機質の堆積被膜からなる積層膜
を層間絶縁膜として用いることによつて容易に絶
縁効果の良い膜厚の厚い絶縁層を形成することが
でき、しかも前記絶縁層の表面が有機化合物膜に
よつて平坦な構造を有していることを特徴とする
半導体装置及びその製造方法である。従来、感光
性樹脂膜は高温の熱処理を施すとパターンくずれ
や飛び散りがおこるため、熱処理工程の前には必
ず除去されるのが普通である。 The present invention aims to easily form a thick insulating layer with good insulation effect by using a laminated film consisting of a completely cured organic compound film such as a photoresist film and an inorganic deposited film as an interlayer insulating film. A semiconductor device and a method for manufacturing the same, characterized in that the surface of the insulating layer has a flat structure due to an organic compound film. Conventionally, when a photosensitive resin film is subjected to high-temperature heat treatment, the pattern may be distorted or splattered, so it is usually always removed before the heat treatment step.
しかるに、本発明者は、ホトレジストの少なく
とも表面を
ホトレジストに170〜200℃の不活性ガス中で
熱処理を施す。 However, the present inventor heat-treated at least the surface of the photoresist in an inert gas at 170 to 200°C.
ホトレジストに不活性ガス（例えば、He，
Ne，Ar，Kr，Xe）およびN2、フレオン系ガス
（例えばCC3F，CC2F2，CCF3，CF4，
CHC2Fなど），クロロカーボン系ガス（例え
ばCC４，C2C６など）などのガスプラズ
マ照射を施す。 Inert gas (e.g. He,
Ne, Ar, Kr, Xe) and N 2 , Freon gases (e.g. CC 3 F, CC 2 F 2 , CCF 3 , CF 4 ,
CHC 2 F, etc.), chlorocarbon-based gas (eg, CC 4 , C 2 C 6 , etc.), etc.).
ホトレジストに不活性ガス（例えば、He，
Ne，Ar，Kr，Xe）のイオン注入を施す。 Inert gas (e.g. He,
Perform ion implantation of Ne, Ar, Kr, Xe).
等の処理を施すことによつて、ホトレジストが
変質し硬化することを見い出した。そしてホトレ
ジストを変質、硬化させておくと、例えば、
CVD膜形成時における比較的高温（800℃程度）
の熱処理までホトレジストが飛び散らず、ホトレ
ジストパターンをくずすことのないことを確認し
た。また、本発明者はホトレジストの少なくとも
表面を上記の３方法のいずれかによつて変質し硬
化した後、比較的高温（400℃程度）の熱処理を
施して完全に硬化したホトレジストは、防湿効果
の良い良質な絶縁層となつていることを確認し
た。 It has been found that photoresist changes in quality and hardens by performing such treatments. Then, if the photoresist is altered and hardened, for example,
Relatively high temperature during CVD film formation (about 800℃)
It was confirmed that the photoresist did not scatter and the photoresist pattern was not damaged until the heat treatment. In addition, the present inventors have discovered that after at least the surface of the photoresist has been altered and hardened by one of the three methods described above, the photoresist that has been completely cured by heat treatment at a relatively high temperature (approximately 400°C) has a moisture-proofing effect. It was confirmed that the insulating layer was of good quality.
本発明は、このような技術的認識を背景に絶縁
被膜と有機化合物膜を絶縁層として用いることに
よつて多層配線プロセスにおいて歩留りを大巾に
改善したものであり、以下本発明を実施例ととも
に説明する。以下、有機化合物膜として感光性樹
脂膜であるポジタイプのホトレジスト（商品名：
AZ−1350J）を用いて例について説明する。 Based on this technical recognition, the present invention greatly improves the yield in a multilayer interconnection process by using an insulating film and an organic compound film as an insulating layer. explain. Hereinafter, a positive type photoresist (product name:
An example will be explained using the AZ-1350J).
第２図は、CVD−SiO2膜とホトレジスト膜の
２層膜を層間絶縁膜として用いた本発明の半導体
装置の実施例を示す。第２図は、層間絶縁膜とし
て膜厚の厚いCVD−SiO2膜１５とCVD−SiO2膜
１５の凹部内のみに形成した完全に硬化したホト
レジスト膜１６とからなる２層膜を用いた本発明
の一実施例を示す。その工程は、通常工程により
拡散層１２、SiO2パターン１３、第１の配線層
となる拡散されたPoIySiパターン１４が形成され
た半導体基板１１上にCVD法によりCVD−SiO2
膜１５を堆積する。その後、ホトレジスト膜を厚
く塗布してブリベーク等の熱処理を施してホトレ
ジスト膜の表面を平坦にした後、O2プラズマ法
によつてCVD−SiO2膜１５の凸部すなわち
PoIySiパターン１４上のホトレジスト膜の厚さ分
だけ除去するか、あるいは、凸部上のホトレジス
ト膜の厚さ分だけ露光・現像を行なつて除去する
方法等によつてCVD−SiO2膜１５の凹部内のみ
にホトレジスト膜１６を残存させる。このとき、
CVD−SiO2膜１５の凸部表面とホトレジスト膜
１６の表面はほぼ平坦となる。 FIG. 2 shows an embodiment of a semiconductor device of the present invention using a two-layer film of a CVD-SiO 2 film and a photoresist film as an interlayer insulating film. Figure 2 shows a book using a two-layer film consisting of a thick CVD-SiO 2 film 15 and a completely hardened photoresist film 16 formed only in the recesses of the CVD-SiO 2 film 15 as an interlayer insulating film. An example of the invention is shown. In this process, CVD-SiO 2 is deposited by a CVD method on a semiconductor substrate 11 on which a diffusion layer 12, a SiO 2 pattern 13, and a diffused PoIySi pattern 14 which will become a first wiring layer are formed in a normal process.
A film 15 is deposited. Thereafter, a photoresist film is applied thickly and heat treated such as brie-bake to make the surface of the photoresist film flat, and then the convex portions of the CVD-SiO 2 film 15 are removed using an O 2 plasma method.
The CVD-SiO 2 film 15 is removed by removing the thickness of the photoresist film on the PoIySi pattern 14, or by exposing and developing the thickness of the photoresist film on the convex portions. The photoresist film 16 is left only in the recess. At this time,
The surface of the convex portion of the CVD-SiO 2 film 15 and the surface of the photoresist film 16 become substantially flat.
次に、ホトレジスト膜１６の少なくとも表面を
硬化する。本実施例では、170℃程度の不活性ガ
ス中で30分間熱処理を施した。この工程により、
ホトレジスト膜１６が硬化し、耐熱性が向上し
た。その後、ホトレジスト膜１６に高温（400℃
程度）の熱処理を10分間施す。この工程により、
ホトレジスト膜１６は未硬化部分が完全に硬化さ
れ、安定した良質な絶縁膜になつたことを確認し
た。さらにこのとき、ホトレジスト膜１６の飛び
散りや変形のないことを確認した。次に、ホトエ
ツチング技術によつて、CVD−SiO2膜１５にコ
ンタクトホールを形成する。このとき、CVD−
SiO2膜１５のコンタクトホールを形成するため
に用いたホトレジストパターンを除去する場合、
例えばレジスト剥離液（商品名：Ｊ−100）ある
いは発煙硝酸を用いれば、ホトレジスト膜１６を
残存させたままホトレジストパターンだけを除去
することができる。 Next, at least the surface of the photoresist film 16 is hardened. In this example, heat treatment was performed for 30 minutes in an inert gas at about 170°C. Through this process,
The photoresist film 16 was cured and its heat resistance was improved. After that, the photoresist film 16 is heated to a high temperature (400°C).
heat treatment for 10 minutes. Through this process,
It was confirmed that the uncured portions of the photoresist film 16 were completely cured, resulting in a stable and high-quality insulating film. Furthermore, at this time, it was confirmed that there was no scattering or deformation of the photoresist film 16. Next, contact holes are formed in the CVD-SiO 2 film 15 by photoetching technology. At this time, CVD−
When removing the photoresist pattern used to form the contact hole in the SiO 2 film 15,
For example, by using a resist stripper (trade name: J-100) or fuming nitric acid, only the photoresist pattern can be removed while leaving the photoresist film 16 remaining.
次に、第２の配線層となるＡ膜を蒸着した
後、ホトエツチング技術によつてＡパターン１
７を形成すれば第２図のような構造が得られる。
このときも、CVD−SiO2膜１５のコンタクトホ
ールを形成したときと同様にＡパターン１７を
形成するために用いたホトレジストパターンを除
去する場合、例えばレジスト剥離液（商品名：Ｊ
−100）あるいは発煙硝酸を用いればホトレジス
ト膜１６に影響を与えることなく除去できる。上
記実施例では、凹部領域のみにホトレジスト膜１
６を形成することによつて、下地基板による凹凸
がなくなり平坦な表面を有する層間絶縁膜を形成
することができる。従つて、Ａパターン１７形
成時には下地に段差がなく、Ａパターンの断線
及びシヨートは生じない。しかも、PoIySiパター
ン１４上は、6000ÅのCVD−SiO2膜１５が形成
されているだけなので、容易に微細コンタクトが
形成できる。さらに、PoIySiパターン１４とＡ
パターン１７を直接電気的に接続してもコンタク
ト部の段差は6000Åであるため、Ａパターン１
７の膜厚を１μｍ程度にすればコンタクト部にお
ける断線は一切生じなかつた。 Next, after depositing the A film that will become the second wiring layer, the A pattern 1 is formed using photoetching technology.
7, a structure as shown in FIG. 2 can be obtained.
At this time as well, when removing the photoresist pattern used to form the A pattern 17 in the same way as when forming the contact hole of the CVD-SiO 2 film 15, for example, resist stripping liquid (product name: J
-100) or using fuming nitric acid, it can be removed without affecting the photoresist film 16. In the above embodiment, the photoresist film 1 is applied only to the concave region.
By forming 6, it is possible to form an interlayer insulating film having a flat surface without unevenness caused by the underlying substrate. Therefore, when the A pattern 17 is formed, there is no step on the base, and no breakage or shorting of the A pattern occurs. Furthermore, since only the 6000 Å CVD-SiO 2 film 15 is formed on the PoIySi pattern 14, fine contacts can be easily formed. Furthermore, PoIySi pattern 14 and A
Even if pattern 17 is directly electrically connected, the height difference in the contact area is 6000 Å, so pattern A 1
When the film thickness of No. 7 was set to about 1 μm, no disconnection occurred at the contact portion.
第３図は、CVD−SiO2膜とホトレジスト膜と
CVD−SiO2膜の３層膜を層間絶縁膜として用い
た本発明の実施例を示す。 Figure 3 shows CVD-SiO 2 film and photoresist film.
An embodiment of the present invention will be shown in which a three-layer film of CVD-SiO 2 film is used as an interlayer insulating film.
第３図は、層間絶縁膜として膜厚の薄いCVD
−SiO2膜３５とCVD−SiO2膜３５の凹部内のみ
に形成した完全に硬化したホトレジスト膜３６と
CVD−SiO2膜３５およびホトレジスト膜３６の
表面上に形成された膜厚の厚いCVD−SiO2膜３
７とからなる３層膜を用いた本発明の一実施例を
示す。その工程は、通常工程により拡散層３２、
SiO2パターン３３、第１の配線層となる拡散さ
れたPoIySiパターン３４が形成された半導体基板
３１上にCVD法によりCVD−SiO2膜３５を1000
Å積度堆積する。次に、ホトレジストを塗布し、
第２図ａのホトレジスト膜１６をCVD−SiO2膜
１５の凹部内のみに残存させた方法と同様な方法
によつてCVD−SiO2膜３５の凹部内のみにホト
レジスト膜３６を残存させる。このとき、CVD
−SiO2膜３５の凸部表面とホトレジスト膜３６
の表面がほぼ平坦になるように残存させる。 Figure 3 shows thin CVD film used as an interlayer insulating film.
- SiO 2 film 35 and CVD - Completely hardened photoresist film 36 formed only in the recessed part of the SiO 2 film 35
A thick CVD-SiO 2 film 3 formed on the surfaces of the CVD-SiO 2 film 35 and the photoresist film 36
An example of the present invention using a three-layer film consisting of 7 will be shown. In this process, the diffusion layer 32,
On the semiconductor substrate 31 on which the SiO 2 pattern 33 and the diffused PoIySi pattern 34 which will become the first wiring layer are formed, a CVD-SiO 2 film 35 of 1000% is deposited by the CVD method.
A: Deposit. Next, apply photoresist,
The photoresist film 36 is left only in the recesses of the CVD-SiO 2 film 35 by a method similar to the method of leaving the photoresist film 16 only in the recesses of the CVD-SiO 2 film 15 in FIG. 2a. At this time, CVD
- Convex surface of SiO 2 film 35 and photoresist film 36
Leave the surface so that it is almost flat.
次に、ホトレジスト膜３６の少なくとも表面を
プラズマ照射あるいはイオン注入等の方法によつ
て硬化させた後、高温（400℃程度）の熱処理を
10分間程度施してホトレジスト膜３６を完全に硬
化する。その後、CVD法によつてCVD−SiO2膜
３７を6000Å程度堆積し、ホトエツチング技術に
よりSiO2膜３５およびCVD−SiO2膜３７にコン
タクトホールを形成する。次に第２の配線層とな
るＡ膜を蒸着した後、ホトエツチング技術によ
つてＡパターン３８を形成すれば第３図のよう
な構造が得られる。 Next, after hardening at least the surface of the photoresist film 36 by a method such as plasma irradiation or ion implantation, heat treatment at a high temperature (approximately 400°C) is performed.
The photoresist film 36 is completely cured by applying it for about 10 minutes. Thereafter, a CVD-SiO 2 film 37 of about 6000 Å is deposited by the CVD method, and contact holes are formed in the SiO 2 film 35 and the CVD-SiO 2 film 37 by photoetching. Next, after depositing an A film which will become a second wiring layer, an A pattern 38 is formed by photo-etching to obtain a structure as shown in FIG.
上記実施例では、ホトレジスト膜３６がCVD
−SiO2膜３５とCVD−SiO2膜３７によつて囲ま
れ、且つ、CVD−SiO2膜３７の表面が平坦な構
造を有する層間絶縁膜を形成することができる。
従つて、Ａパターン３８形成時には下地に段差
がなく、Ａパターンの断線及びシヨートは生じ
なかつた。しかも、PoIySiパターン３４上には
1000ÅのCVD−SiO2膜３５と6000ÅのCVD−
SiO2膜３７が形成されているだけなので、容易
に微細コンタクトが形成できる。さらに、PoIySi
パターン３４とＡパターン３８を直接電気的に
接続しても、コンタクト部の段差は7000Å程度で
あるため、Ａパターン３８の膜厚を１μｍ程度
にすればコンタクト部における断線は一切生じな
かつた。また、CVD−SiO2膜３７を形成するこ
とによつて、Ａパターン３８形成におけるレジ
スト除去がO2プラズマでできるなどホトレジス
ト膜３６を層間絶縁膜として用いることによる後
工程の処理方法に対して制限がなくなる。且つ、
ホトレジスト膜表面からの汚染防止及び絶縁性を
高めることができる。 In the above embodiment, the photoresist film 36 is formed by CVD.
An interlayer insulating film can be formed that is surrounded by the -SiO 2 film 35 and the CVD-SiO 2 film 37 and has a structure in which the surface of the CVD-SiO 2 film 37 is flat.
Therefore, when the A pattern 38 was formed, there was no step on the base, and no breakage or shorting of the A pattern occurred. Moreover, on PoIySi pattern 34,
1000 Å CVD-SiO 2 film 35 and 6000 Å CVD-
Since only the SiO 2 film 37 is formed, fine contacts can be easily formed. Furthermore, PoIySi
Even if the pattern 34 and the A pattern 38 were directly electrically connected, the step difference in the contact portion was about 7000 Å, so if the thickness of the A pattern 38 was set to about 1 μm, no disconnection occurred at the contact portion. In addition, by forming the CVD-SiO 2 film 37, the resist in forming the A pattern 38 can be removed using O 2 plasma, which limits the processing method in the post-process by using the photoresist film 36 as an interlayer insulating film. disappears. and,
It is possible to prevent contamination from the surface of the photoresist film and improve insulation.
以上本発明によれば、層間絶縁膜としてCVD
−SiO2膜とホトレジスト膜の２層膜あるいは
CVD−SiO2膜とホトレジスト膜とCVD−SiO2膜
の３層膜を用いることによつて容易に膜厚の厚い
絶縁層を形成することができる。しかも、下地基
板に段差があつてもホトレジスト膜によつて容易
に段差を緩和することができ表面をほぼ平坦にす
ることができる。また、第１の配線上にCVD−
SiO2膜が形成されているため、ホトレジスト膜
のNa+イオン等の可動イオンによる汚染を防止す
ることができる。そして、ホトレジスト膜を完全
に硬化しておくことによつて、Ａシンターや
CVD−SiO2膜堆積時等の熱処理による流動がな
く、しかも、防湿効果の良い良質な絶縁膜とな
る。したがつて、第２の配線層を行なつた場合、
断線や層間のシヨートがなくなり歩留り良い多層
配線を行なうことができる。 As described above, according to the present invention, CVD is used as an interlayer insulating film.
-Two-layer film of SiO 2 film and photoresist film or
By using a three-layer film of a CVD-SiO 2 film, a photoresist film, and a CVD-SiO 2 film, a thick insulating layer can be easily formed. Moreover, even if there is a step difference in the base substrate, the step difference can be easily alleviated by the photoresist film, and the surface can be made substantially flat. Also, CVD− on the first wiring
Since the SiO 2 film is formed, it is possible to prevent the photoresist film from being contaminated by mobile ions such as Na + ions. By completely curing the photoresist film, A sinter and
There is no flow due to heat treatment during CVD-SiO 2 film deposition, and the result is a high-quality insulating film with good moisture-proofing effects. Therefore, when performing the second wiring layer,
There are no disconnections or shorts between layers, making it possible to perform multilayer wiring with high yield.
以上、本発明の実施例では二層目の配線までし
か説明しなかつたが、三層目、四層目の配線を行
なう場合にも同様に行なうことができる。なお、
絶縁被膜として無機質の堆積被膜であるCVD−
SiO2膜を用いて説明したが他の無機質の堆積被
膜例えばSi3N4膜、PSG膜等を用いても良い。ま
た、有機化合物膜として感光性樹脂であるポジタ
イプのホトレジスト（商品名：AZ−1350J）を用
いて説明したが、他の熱硬化性有機化合物膜を用
いても良い。 Although the embodiments of the present invention have only been described up to the second layer of wiring, the same can be applied to the third and fourth layer wiring. In addition,
CVD is an inorganic deposited film used as an insulating film.
Although the explanation has been made using a SiO 2 film, other inorganic deposited films such as a Si 3 N 4 film, a PSG film, etc. may also be used. Moreover, although the description has been made using a positive type photoresist (trade name: AZ-1350J), which is a photosensitive resin, as the organic compound film, other thermosetting organic compound films may be used.
第１図は従来の多層配線構造の半導体装置の構
造断面図、第２図は層間絶縁膜としてCVD−
SiO2膜とホトレジスト膜の２層膜を用いた本発
明の一実施例の半導体装置の断面図、第３図は層
間絶縁膜としてCVD−SiO2膜とホトレジスト膜
とCVD−SiO2膜の３層膜を用いた本発明の他の
実施例の半導体装置断面図である。
１１，３１……半導体基板、１３，３３……
SiO2パターン、１４，３４……PoIySiパター
ン、１５，３５，３７…CVD−SiO2パターン、
１６，３６……ホトレジスト膜、１７，３８……
Ａパターン。
Figure 1 is a structural cross-sectional view of a semiconductor device with a conventional multilayer wiring structure, and Figure 2 is a CVD-
FIG . 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention using a two-layer film of a SiO 2 film and a photoresist film. FIG. 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention using a layered film. 11, 31... semiconductor substrate, 13, 33...
SiO 2 pattern, 14, 34... PoIySi pattern, 15, 35, 37... CVD-SiO 2 pattern,
16,36...Photoresist film, 17,38...
A pattern.
Claims (1)
前記半導体基板及び前記第１の配線層上に形成さ
れた無機質の堆積被膜と、前記半導体基板の凹部
領域のみに形成された硬化処理により完全に硬化
した有機化合物膜と、前記堆積被膜及び前記有機
化合物膜上に形成された第２の配線層とで構成さ
れ、且つ、前記第１の配線層と前記第２の配線層
とが直接電気的に接続されていることを特徴とす
る半導体装置。 ２ 第１の配線層上に形成された無機質の堆積被
膜の表面と凹部領域のみに形成された有機化合物
膜の表面がほぼ平坦であることを特徴とする特許
請求の範囲第１項に記載の半導体装置。 ３ 有機化合物膜が感光性樹脂膜であることを特
徴とする特許請求の範囲第１項に記載の半導体装
置。 ４ 堆積被膜及び有機化合物膜上に第２の無機質
の堆積被膜が形成されていることを特徴とする特
許請求の範囲第１項に記載の半導体装置。 ５ 第１の配線層が形成された凹凸の表面を有す
る半導体基板上に無機質の堆積被膜を形成する工
程と、前記堆積被膜の凹部領域のみに有機化合物
膜を形成する工程と、前記有機化合物膜の少なく
とも表面を硬化する第１の硬化処理を施す工程
と、前記有機化合物膜を完全に硬化する熱処理に
よる第２の硬化処理を施す工程と、前記第１の配
線層上の前記無機質の堆積被膜の所望の領域にコ
ンタクト窓を形成する工程と、前記堆積被膜及び
前記有機化合物膜上に第２の配線層を形成する工
程とを有することを特徴とする半導体装置の製造
方法。 ６ 堆積被膜の表面と有機化合物膜の表面がほぼ
平堆であることを特徴とする特許請求の範囲第５
項に記載の半導体装置の製造方法。 ７ 有機化合物膜が感光性樹脂膜であることを特
徴とする特許請求の範囲第５項に記載の半導体装
置の製造方法。 ８ 第１の硬化処理が(i)170℃〜200℃の熱処理(ii)
ガスプラズマ照射(iii)イオン注入のいずれかの方法
によつて行なうことを特徴とする特許請求の範囲
第５項に記載の半導体装置の製造方法。 ９ 有機化合物膜を完全に硬化する熱処理による
第２の硬化処理を施した後、全面に第２の無機質
の堆積被膜を形成する工程を有することを特徴と
する特許請求の範囲第５項に記載の半導体装置の
製造方法。[Claims] 1. A first wiring layer formed on a semiconductor substrate;
an inorganic deposited film formed on the semiconductor substrate and the first wiring layer; an organic compound film completely cured by a curing process formed only in the recessed region of the semiconductor substrate; 1. A semiconductor device comprising a second wiring layer formed on a compound film, the first wiring layer and the second wiring layer being directly electrically connected. 2. The method according to claim 1, wherein the surface of the inorganic deposited film formed on the first wiring layer and the surface of the organic compound film formed only in the recessed region are substantially flat. Semiconductor equipment. 3. The semiconductor device according to claim 1, wherein the organic compound film is a photosensitive resin film. 4. The semiconductor device according to claim 1, wherein a second inorganic deposited film is formed on the deposited film and the organic compound film. 5. A step of forming an inorganic deposited film on a semiconductor substrate having an uneven surface on which a first wiring layer is formed, a step of forming an organic compound film only in the recessed region of the deposited film, and a step of forming the organic compound film on the semiconductor substrate having an uneven surface. a step of performing a first hardening treatment to harden at least the surface of the organic compound film; a step of performing a second hardening treatment by heat treatment to completely harden the organic compound film; and a step of performing a second hardening treatment by heat treatment to completely harden the organic compound film, and the deposited inorganic film on the first wiring layer. 1. A method of manufacturing a semiconductor device, comprising: forming a contact window in a desired region of the semiconductor device; and forming a second wiring layer on the deposited film and the organic compound film. 6. Claim 5, characterized in that the surface of the deposited film and the surface of the organic compound film are substantially flat.
A method for manufacturing a semiconductor device according to paragraph 1. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the organic compound film is a photosensitive resin film. 8 The first hardening treatment is (i) heat treatment at 170°C to 200°C (ii)
6. The method of manufacturing a semiconductor device according to claim 5, wherein the method is performed by any one of gas plasma irradiation (iii) and ion implantation. 9. According to claim 5, the process comprises a step of forming a second inorganic deposited film on the entire surface after performing a second hardening treatment by heat treatment to completely harden the organic compound film. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7735779A JPS561547A (en) | 1979-06-19 | 1979-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7735779A JPS561547A (en) | 1979-06-19 | 1979-06-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS561547A JPS561547A (en) | 1981-01-09 |
| JPS627699B2 true JPS627699B2 (en) | 1987-02-18 |
Family
ID=13631650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7735779A Granted JPS561547A (en) | 1979-06-19 | 1979-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS561547A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250771U (en) * | 1988-09-30 | 1990-04-10 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972745A (en) * | 1982-10-19 | 1984-04-24 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US4523372A (en) * | 1984-05-07 | 1985-06-18 | Motorola, Inc. | Process for fabricating semiconductor device |
| US5070037A (en) * | 1989-08-31 | 1991-12-03 | Delco Electronics Corporation | Integrated circuit interconnect having dual dielectric intermediate layer |
-
1979
- 1979-06-19 JP JP7735779A patent/JPS561547A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250771U (en) * | 1988-09-30 | 1990-04-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS561547A (en) | 1981-01-09 |
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