JPS6125219B2 - - Google Patents
Info
- Publication number
- JPS6125219B2 JPS6125219B2 JP54113710A JP11371079A JPS6125219B2 JP S6125219 B2 JPS6125219 B2 JP S6125219B2 JP 54113710 A JP54113710 A JP 54113710A JP 11371079 A JP11371079 A JP 11371079A JP S6125219 B2 JPS6125219 B2 JP S6125219B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring conductor
- film
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 34
- 239000010410 layer Substances 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000002952 polymeric resin Substances 0.000 claims description 9
- 229920003002 synthetic resin Polymers 0.000 claims description 9
- ZFSLODLOARCGLH-UHFFFAOYSA-N isocyanuric acid Natural products OC1=NC(O)=NC(O)=N1 ZFSLODLOARCGLH-UHFFFAOYSA-N 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- -1 isocyanuric acid ester Chemical class 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 238000000034 method Methods 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 10
- 239000009719 polyimide resin Substances 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- 239000011651 chromium Substances 0.000 description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 6
- 229910052804 chromium Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- KOMNUTZXSVSERR-UHFFFAOYSA-N 1,3,5-tris(prop-2-enyl)-1,3,5-triazinane-2,4,6-trione Chemical compound C=CCN1C(=O)N(CC=C)C(=O)N(CC=C)C1=O KOMNUTZXSVSERR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004634 thermosetting polymer Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- FXHOOIRPVKKKFG-UHFFFAOYSA-N N,N-Dimethylacetamide Chemical compound CN(C)C(C)=O FXHOOIRPVKKKFG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- XMPZTFVPEKAKFH-UHFFFAOYSA-P ceric ammonium nitrate Chemical compound [NH4+].[NH4+].[Ce+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O XMPZTFVPEKAKFH-UHFFFAOYSA-P 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- IXFOBQXJWRLXMD-ZIQFBCGOSA-N para-nitrophenyl 1-thio-β-d-glucopyranoside Chemical compound O[C@@H]1[C@@H](O)[C@H](O)[C@@H](CO)O[C@H]1SC1=CC=C([N+]([O-])=O)C=C1 IXFOBQXJWRLXMD-ZIQFBCGOSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000379 polymerizing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の構造、特に電極配線が
２層以上に及ぶ多層配線構造をそなえた半導体装
置における層間絶縁膜の改良に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, particularly to an improvement of an interlayer insulating film in a semiconductor device having a multilayer wiring structure including two or more layers of electrode wiring.
従来、半導体装置、特にモノリシツク集積回路
においては、トランジスタなどの半導体能動素子
を形成したシリコン基板上に二酸化シリコンなど
の絶縁被膜を化学気相成長法などによつて形成し
た後、前記基板の能動素子と、その上の絶縁被膜
上に形成成される配線導体との接続に必要な部分
の絶縁被膜を周知の写真蝕刻法によつて除去し、
これによつて露出された基板と絶縁被膜の全面に
アルミニウムなどからなる導体金属を蒸着し、写
真蝕刻法を用いて不要部分の金属被膜を選択除去
し、所望の配線パターンを得ていた。 Conventionally, in semiconductor devices, particularly monolithic integrated circuits, an insulating film such as silicon dioxide is formed on a silicon substrate on which semiconductor active elements such as transistors are formed by chemical vapor deposition, and then the active elements on the substrate are formed. and the insulating film formed on the insulating film on the part necessary for connection with the wiring conductor formed on the insulating film by a well-known photolithography method,
A conductive metal such as aluminum is deposited on the entire surface of the exposed substrate and insulating film, and unnecessary portions of the metal film are selectively removed using photolithography to obtain a desired wiring pattern.
さらにこの配線導体層上に１層以上の配線導体
層を構成しようとすれば、この上に再び二酸化シ
リコンあるいは窒化シリコンなどの絶縁被膜を前
記の方法または高周波スパツタリング法等により
被着したのち、その上に形成される配線導体層と
の接続に必要な部分の絶縁被膜を写真蝕刻法で選
択的に除去し、その全面に導体金属を蒸着して写
真蝕刻法によつて所望の配線パターンを形成する
ようにすればよいのであるが、このような構成に
よれば、第１層の配線導体によつて生じる段差、
また導体層間の接続部において絶縁被膜に設けた
スルホールによつて生ずる段差などによつて第２
層の配線導体が段差の側面において断線しやすく
なり、信頼性に欠ける欠点があつた。 Furthermore, if one or more wiring conductor layers are to be constructed on this wiring conductor layer, an insulating film such as silicon dioxide or silicon nitride is deposited thereon again by the above-mentioned method or high-frequency sputtering method. The insulating film is selectively removed from the parts necessary for connection with the wiring conductor layer formed above by photolithography, and a conductive metal is deposited on the entire surface to form the desired wiring pattern by photolithography. However, according to such a configuration, the level difference caused by the first layer wiring conductor,
In addition, at the connection between conductor layers, the second
The wiring conductor of the layer is likely to be disconnected on the side surface of the step, resulting in a lack of reliability.
従つてこのような欠点を改善するため、前記基
板上に第１層の配線導体を形成したのち、その上
面に層間絶縁膜すなわち前記二酸化シリコン等か
らなる無機絶縁膜を設けるかわりに絶縁性のよい
熱硬化性高分子樹脂膜を形成し、前記第１層の配
線導体及び、前記基板の能動素子と第１層の配線
導体間の接続部におけるスルホール等によつて形
成された凸凹を平担にし、段差を解消する配線構
造がとられていた。この熱硬化性高分子樹脂膜と
しては、一般に市販のポリイミド樹脂、例えば東
洋レーヨン製のトレニース、あるいはデユポン製
のパイレーML等を用い、適当な溶剤、例えばＮ
−メチル−２−ピロリドンあるいはジメチルアセ
トアシドを加えて所望の粘度に調整し、回転塗布
あるいは浸漬、吹き付けなどの方法により前記配
線導体構成基板上に塗布し、所定の加熱処理によ
つて溶剤を揮発し、重合硬化させることにより表
面の平担な樹脂絶縁膜を得ていた。 Therefore, in order to improve such drawbacks, instead of forming a first layer of wiring conductors on the substrate and then providing an interlayer insulating film, that is, an inorganic insulating film made of silicon dioxide, etc., on the upper surface, forming a thermosetting polymer resin film to flatten unevenness formed by through holes, etc. in the wiring conductor of the first layer and the connection portion between the active element of the substrate and the wiring conductor of the first layer; , a wiring structure was used to eliminate the level difference. This thermosetting polymer resin film is generally made of a commercially available polyimide resin, such as Toyo Rayon's Trenice or Dupont's Pyre ML, and a suitable solvent, such as N
- Add methyl-2-pyrrolidone or dimethylacetoacide to adjust the viscosity to the desired level, apply it on the wiring conductor component substrate by spin coating, dipping, spraying, etc., and volatilize the solvent by a prescribed heat treatment. Then, by polymerizing and curing, a resin insulating film with a flat surface was obtained.
しかしながら上記の層間絶縁膜、即ちポリイミ
ド樹脂は、二酸化シリコンや窒化シリコン、PSG
（リンガラス）等に対する密着性が悪く、特に高
温高湿の雰囲気にさらされるとその接着性が劣化
する問題があつた。 However, the above interlayer insulating film, that is, polyimide resin, is made of silicon dioxide, silicon nitride, PSG.
(phosphorus glass) etc., and there was a problem that the adhesiveness deteriorated especially when exposed to a high temperature and high humidity atmosphere.
そこでこれらの接着性を改善するため、前記配
線導体構成基板上にポリイミド樹脂からなる層間
絶縁膜を形成するに先だち、例えばポリメタクリ
ル酸メチル（PMMA）又はAZ1350J等のレジスト
膜、あるいはアルミニウム（Al）の酸化膜など
をあらかじめ形成しておき、その上に前記ポリイ
ミド樹脂からなる層間絶縁膜を被着形成し接着性
を高めることが知られているが、上述のようにレ
ジスト膜を介在させると、前記ポリイミド樹脂を
熱硬化、あるいはAlからなる配線導体の形成後
のアニール処理等によりレジスト膜が変質しやす
くなる。またAlの酸化膜を介在させると熱的に
問題はなく接着性も改善されるが、Al酸化膜を
形成するには熱酸化等の工程において配線導体自
体を劣化させない配慮が必要であり、このため陽
極酸化法を用いることから工程が煩雑となる欠点
がある。従つて耐熱性を有し、かつ二酸化シリコ
ン等の絶縁膜及びポリイミド樹脂等と密着性のよ
い下地絶縁膜を介して層間絶縁膜を形成すること
が望まれていた。 Therefore, in order to improve the adhesion of these, prior to forming an interlayer insulating film made of polyimide resin on the wiring conductor constituent substrate, for example, a resist film such as polymethyl methacrylate (PMMA) or AZ1350J, or aluminum (Al) is used. It is known that an oxide film or the like is formed in advance, and then an interlayer insulating film made of the polyimide resin is deposited thereon to improve adhesion. However, when a resist film is interposed as described above, The resist film tends to change in quality due to thermal curing of the polyimide resin or annealing treatment after forming the wiring conductor made of Al. In addition, interposing an Al oxide film causes no thermal problems and improves adhesion, but in order to form an Al oxide film, care must be taken not to deteriorate the wiring conductor itself during processes such as thermal oxidation. Therefore, since an anodic oxidation method is used, there is a drawback that the process is complicated. Therefore, it has been desired to form an interlayer insulating film through a base insulating film that has heat resistance and has good adhesion to an insulating film such as silicon dioxide and polyimide resin.
従つて本発明は前記従来の実情に鑑みなされた
もので、その目的は半導体素子に対する多層配線
導体間に、配線導体等によつて段差を生じないこ
とは勿論のこと、絶縁性を低下することなく、耐
熱性を有しかつ密着性の優れた層間絶縁膜の構成
を提供することである。 Therefore, the present invention has been made in view of the above-mentioned conventional situation, and its purpose is not only to prevent the formation of a level difference due to the wiring conductors, etc., but also to reduce the insulation properties between the multilayer wiring conductors for the semiconductor element. However, it is an object of the present invention to provide a structure of an interlayer insulating film that has heat resistance and excellent adhesion.
上記の目的を達成するため、本発明の半導体装
置は、高分子樹脂絶縁膜を挾んで、少なくとも２
層に配設してなる配線導体をそなえた半導体装置
において、前記層間絶縁膜を、その下の配線導体
に直接、接するイソシアヌル酸エステルの重合体
の絶縁膜とし、その上に形成した別の高分子樹脂
絶縁膜とで構成したことを特徴とするものであ
る。 In order to achieve the above object, the semiconductor device of the present invention has at least two
In a semiconductor device having wiring conductors arranged in layers, the interlayer insulating film is an insulating film of an isocyanuric acid ester polymer that is in direct contact with the underlying wiring conductor, and another high It is characterized by being composed of a molecular resin insulating film.
以下図面を用いて本発明に係る半導体装置の実
施例について詳細に説明する。 Embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the drawings.
図ａ〜ｅは本発明に係る２層配線間に層間絶縁
膜を構成する場合の一実施例を工程順に示す概略
断面図である。 Figures a to e are schematic cross-sectional views showing, in order of process, one embodiment of forming an interlayer insulating film between two-layer interconnections according to the present invention.
図ａに示すように、コレクタ領域Ｃ、ベース領
域Ｂ、エミツタ領域Ｅからなる半導体素子が形成
されているシリコン基板１の表面に周知の化学気
相成長法によつて、例えば二酸化シリコン膜２を
形成し、次いで電極引出し部分となる所定部分を
写真蝕刻法によつて除去し、二酸化シリコン膜２
にスルホール（窓）３を設け、前記エミツタ領域
Ｅ及びベース領域Ｂの一部を露出させる。しかる
後、前記スルホール３上に図示のごとくアルミニ
ウム（Al）の蒸着と写真蝕刻法によつて第１層
の配線導体４を形成する。しかして本発明におい
ては、ポリイミド樹脂からなる層間絶縁膜を前記
配線導体構成基板１上に形成するに先だち、あら
かじめ耐熱性（470℃で分解する）がよく、かつ
密着性の優れているイソシアヌル酸エステルの重
合体、例えば具体的にはトリアリルイソシアヌレ
ート
を回転塗布法等により1000Å程度塗布した後、例
えば約60℃で15分の加熱処理を行なつて溶剤を揮
発し、重合硬化させて有機絶縁膜５を形成する。
次いで図ｂに示すように、前記有機絶縁膜５上
に、ポリイミド樹脂、例えば東洋レーヨン製トレ
ニースあるいはデユポン製のパイレMLなどを適
当な溶剤、例えばＮ−メチル−２−ピロリドンあ
るいはジメチルアセトアミド等を加えて粘度調整
し、回転塗布法などにより例えば２μ程度の厚さ
に塗布し、しかる後、所定の加熱処理、例えば約
150℃で60分、次いで約300℃で60分程度処理を行
なつて樹脂を重合させて十分に硬化させ高分子樹
脂絶縁膜６を形成し、第１層の配線導体４及び半
導体素子からの電極引出し部分のスルホール３に
よつて形成された凹凸を平担にして段差を解消す
る。次いで図ｃに示すごとく前記樹脂膜６上にク
ロム（Cr）を蒸着し、該クロム蒸着膜７の所定
部分即ち、第１層の配線導体４と電気的接続をす
べき所定部位上を写真蝕刻法によつて除去してエ
ツチングマスクを形成する。次いでO2ガスプラ
ズマ放電によつて前記クロム蒸着膜７を除去した
部分の樹脂と、さらにその下部にあるトリアリル
イソシアヌレートからなる有機絶縁膜５とを選択
的にスパツタエツチングして除去し、第１層の配
線導体４の所定部分を露出させた窓８を設ける。
残つたクロム蒸着膜７は例えば硝酸セリウムアン
モニウム等の水溶液からなるクロムのエツチング
液によつて前記樹脂層、二酸化シリコン、アルミ
ニウムなどを腐蝕することなく全面的にエツチン
グ除去し、しかる後図ｄに示すごとくAlの蒸着
と写真蝕刻法によつて第２層の配線導体９を形成
する。 As shown in FIG. A silicon dioxide film 2
A through hole (window) 3 is provided in the wafer to expose a portion of the emitter region E and base region B. Thereafter, a first layer of wiring conductor 4 is formed on the through hole 3 by vapor deposition of aluminum (Al) and photolithography as shown in the figure. Therefore, in the present invention, prior to forming an interlayer insulating film made of polyimide resin on the wiring conductor constituent substrate 1, isocyanuric acid, which has good heat resistance (decomposes at 470°C) and excellent adhesion, is used. Polymers of esters, such as specifically triallylisocyanurate After coating the film to a thickness of about 1000 Å using a spin coating method or the like, heat treatment is performed at, for example, about 60° C. for 15 minutes to volatilize the solvent and polymerize and harden to form the organic insulating film 5.
Next, as shown in FIG. b, a polyimide resin such as Toyo Rayon's Trenice or Dupont's Pyre ML is added to the organic insulating film 5 in a suitable solvent such as N-methyl-2-pyrrolidone or dimethylacetamide. to adjust the viscosity, apply it to a thickness of, for example, about 2μ by a spin coating method, and then undergo a predetermined heat treatment, e.g.
Processing is performed at 150°C for 60 minutes and then at about 300°C for about 60 minutes to polymerize and cure the resin sufficiently to form a polymer resin insulating film 6. The unevenness formed by the through-hole 3 in the electrode lead-out portion is flattened to eliminate the level difference. Next, as shown in FIG. c, chromium (Cr) is deposited on the resin film 6, and a predetermined portion of the chromium deposited film 7, that is, a predetermined portion to be electrically connected to the first layer wiring conductor 4, is photo-etched. The etching mask is formed by removing the etching mask using a method. Next, the resin in the area where the chromium vapor deposited film 7 has been removed by O 2 gas plasma discharge and the organic insulating film 5 made of triallyl isocyanurate located below it are selectively removed by sputter etching. A window 8 exposing a predetermined portion of the first layer wiring conductor 4 is provided.
The remaining chromium vapor deposited film 7 is completely removed by etching with a chromium etching solution made of an aqueous solution of cerium ammonium nitrate, etc., without corroding the resin layer, silicon dioxide, aluminum, etc., and then is shown in FIG. d. A second layer of wiring conductor 9 is formed by Al vapor deposition and photolithography.
この様に前記層間絶縁膜を第１層の配線導体４
と、その周辺の二酸化シリコン膜２上に直線被着
するイソシアヌル酸エステルの重合体からなる有
機絶縁膜５と、さらにその上に形成した例えばポ
リイミド樹脂からなる高分子樹脂絶縁膜６とで構
成することにより、その接着性は本半導体装置を
形成する工程間の各種熱処理に耐え、実用上十分
な密着性が維持でき、従来のごとき接着性の劣化
等の不都合は解消した。 In this way, the interlayer insulating film is connected to the first layer wiring conductor 4.
, an organic insulating film 5 made of a polymer of isocyanuric acid ester that is linearly deposited on the silicon dioxide film 2 around it, and a polymer resin insulating film 6 made of, for example, polyimide resin formed thereon. As a result, the adhesiveness can withstand various heat treatments during the process of forming the present semiconductor device, maintains adhesion sufficient for practical use, and eliminates the conventional disadvantages such as deterioration of adhesiveness.
さらに第３層の配線導体の形成あるいは、ボン
デング穴を形成するには前記第２層の配線導体９
と高分子樹脂絶縁膜６上にさらに高分子樹脂絶縁
膜１０を図ｅのように形成し、前記第２層の配線
導体９部分上面の露出、次いで第３層の配線導体
の形成あるいは、ボンデングパツド部を形成する
ことができる。 Furthermore, in order to form a third layer wiring conductor or to form a bonding hole, the second layer wiring conductor 9 is
Then, a polymer resin insulating film 10 is further formed on the polymer resin insulating film 6 as shown in FIG. can form a section.
以上の説明から明らかなように本発明の半導体
装置においては、上述したように少なくとも半導
体等の基板上に設けられた第１層の配線導体とそ
の周辺の二酸化シリコン膜上に直接イソシアヌル
酸エステルの重合体からなる有機絶縁膜を被着し
該有機絶縁膜の上部にポリイミド樹脂からなる高
分子樹脂絶縁膜を設けて層間絶縁膜を構成するこ
とにより、多層配線導体間に段差が生じないこと
は勿論のこと、絶縁性を低下させることなく、容
易に耐熱性が改善され、密着性を向上することが
可能となり、本装置は極めて安定なものとなり、
信頼性が向上する等実用上有利である。 As is clear from the above description, in the semiconductor device of the present invention, isocyanurate ester is directly applied to at least the first layer wiring conductor provided on a substrate such as a semiconductor and the silicon dioxide film around it. By depositing an organic insulating film made of a polymer and providing a polymeric resin insulating film made of polyimide resin on top of the organic insulating film to form an interlayer insulating film, it is possible to eliminate steps between multilayer wiring conductors. Of course, it is possible to easily improve heat resistance and improve adhesion without reducing insulation properties, making this device extremely stable.
This has practical advantages such as improved reliability.
図ａ〜ｅは本発明に係る半導体装置を構成する
多層配線間の層間絶縁膜を説明するための一実施
を工程順に示す概略断面図である。
１：基板、２：二酸化シリコン膜、３：導体接
続穴、４：第１層の配線導体、５：有機絶縁膜、
６：高分子樹脂絶縁膜、７：クロム蒸着膜、８：
導体接続穴、９：第２層の配線導体、１０：高分
子樹脂絶縁膜。
FIGS. a to e are schematic cross-sectional views showing one implementation step by step to explain an interlayer insulating film between multilayer interconnections constituting a semiconductor device according to the present invention. 1: Substrate, 2: Silicon dioxide film, 3: Conductor connection hole, 4: First layer wiring conductor, 5: Organic insulating film,
6: Polymer resin insulating film, 7: Chromium vapor deposited film, 8:
Conductor connection hole, 9: second layer wiring conductor, 10: polymer resin insulating film.
Claims (1)
に配設してなる配線導体をそなえた半導体装置に
おいて、前記層間絶縁膜を、その下の配線導体に
直接、接するイソシアヌル酸エステル重合体の絶
縁膜と、その上に形成した別の高分子樹脂絶縁膜
とで構成したことを特徴とする半導体装置。1. In a semiconductor device comprising a wiring conductor arranged in at least two layers with a polymer resin insulating film sandwiched therebetween, the interlayer insulating film is an insulator made of an isocyanuric acid ester polymer that is in direct contact with the underlying wiring conductor. A semiconductor device comprising a film and another polymer resin insulating film formed on the film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11371079A JPS5637632A (en) | 1979-09-05 | 1979-09-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11371079A JPS5637632A (en) | 1979-09-05 | 1979-09-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5637632A JPS5637632A (en) | 1981-04-11 |
| JPS6125219B2 true JPS6125219B2 (en) | 1986-06-14 |
Family
ID=14619188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11371079A Granted JPS5637632A (en) | 1979-09-05 | 1979-09-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5637632A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6389827U (en) * | 1986-12-01 | 1988-06-10 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442237A (en) * | 1991-10-21 | 1995-08-15 | Motorola Inc. | Semiconductor device having a low permittivity dielectric |
-
1979
- 1979-09-05 JP JP11371079A patent/JPS5637632A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6389827U (en) * | 1986-12-01 | 1988-06-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5637632A (en) | 1981-04-11 |
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