JPS5972745A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5972745A
JPS5972745A JP18396782A JP18396782A JPS5972745A JP S5972745 A JPS5972745 A JP S5972745A JP 18396782 A JP18396782 A JP 18396782A JP 18396782 A JP18396782 A JP 18396782A JP S5972745 A JPS5972745 A JP S5972745A
Authority
JP
Japan
Prior art keywords
insulating film
film
oxide
wiring
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18396782A
Other languages
Japanese (ja)
Inventor
Hiraaki Tsujii
辻井 平明
Takeshi Konuma
小沼 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18396782A priority Critical patent/JPS5972745A/en
Publication of JPS5972745A publication Critical patent/JPS5972745A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a highly reliable interlayer insulating film having a small diffusing coefficient against movable ions, by forming a first insulating layer comprising an oxide or nitride on a first layer, forming a second insulating layer comprising macromolecular resin thereon, forming a third insulating layer comprising an oxide or nitride thereon, thereby reducing the wiring capacity between the layers. CONSTITUTION:A first layer wiring 2 is formed on a GaAs substrate 1, wherein a specified semiconductor element is formed in advance. Si3N4 as a first insulating layer 3 is formed by a plasma CVD method at a temperature of 300 deg.C. As the insulating film 3, an oxide film can be used. Polyimide PIQ is rotatably applied on the film 3 as a second insulating film 4 comprising a macromolecular resin. The film is heated and hardened at 330 deg.C. Furthermore, an SiO2 film is formed by a plasma CVD method as a third insulating film 5. Then, a second wiring 6 is formed by evaporating Ti/Pt/Au, and thereafter performing lift off.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、多層の配線を行うために、層間絶縁膜を用い
ている半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device using an interlayer insulating film for multilayer wiring.

従来例の構成とその問題点 半導体装置、における多層配線の眉間絶縁膜の材料とし
ては、S 102または八2203に代表される酸化物
、Si3N4に代表される窒化物、高分子の2へ。
Conventional Structure and Problems Materials for the glabellar insulating film of multilayer wiring in semiconductor devices include oxides such as S102 or 82203, nitrides such as Si3N4, and polymers.

樹脂等がある。これらの膜を第1層目の配線と第2層目
の配線の間にはさむことにより、相互の配線の絶縁を行
っている。
There are resins, etc. By sandwiching these films between the first layer wiring and the second layer wiring, the wirings are insulated from each other.

このような層間絶縁膜として要求されていることは、絶
縁耐圧が大きいこと、使用する半導体装置の寿命より長
期にわたり安定であること、可動イオンに対する拡散係
数が小さいこと、半導体装置の高速動作に妨げとならな
い程度に配線間の寄生容量が小さいことである。
Such an interlayer insulating film is required to have a high dielectric strength, be stable for a longer period than the life of the semiconductor device used, have a small diffusion coefficient for mobile ions, and have a material that does not interfere with the high-speed operation of the semiconductor device. The parasitic capacitance between wirings is small enough to avoid the following.

しかしながら、酸化物、窒化物による絶縁膜は通常CV
、D法により形成されており、これら膜の熱膨張係数と
基板のそれとの間に差があり、これが絶縁膜にクラック
を生じさせる原因となるため膜厚を厚くすることが出来
ない。従って配線間の寄生容量が大きくなる。また高分
子の樹脂を用いて層間絶縁膜を形成した場合、膜厚は前
述の酸化物または窒化物からなる絶縁膜に較べて厚くす
ることが出来るが、組成の安定性が不十分であり、さら
にNa+イオン等の可動イオンに対する遮蔽能力も十分
でなかった。
However, insulating films made of oxides and nitrides usually have a CV
, D method, and there is a difference between the coefficient of thermal expansion of these films and that of the substrate, and this causes cracks in the insulating film, so the film thickness cannot be increased. Therefore, the parasitic capacitance between wirings increases. Furthermore, when an interlayer insulating film is formed using a polymer resin, the film thickness can be made thicker than the above-mentioned insulating film made of oxide or nitride, but the stability of the composition is insufficient. Furthermore, the shielding ability against mobile ions such as Na + ions was not sufficient.

3・\−−シ゛ 発明の目的 本発明は、このような欠点を改善したものであり、その
目的は、膜厚を厚くして層間の配線容量を小さくし、か
つ可動イオンに対する拡散係数が小さく、高信頼性の層
間絶縁膜を形成することである。
3. Purpose of the Invention The present invention improves the above-mentioned drawbacks.The purpose of the present invention is to increase the film thickness to reduce the interlayer wiring capacitance, and to reduce the diffusion coefficient for mobile ions. , to form a highly reliable interlayer insulating film.

発明の構成 所定の半導体装置が形成されている半導体基板において
、第1層目の配線が施され、その上に、酸化物または窒
化物から成る第1の絶縁膜を形成し、その上に密着して
高分子の樹脂から成る第2の絶縁膜を形成する。さらに
その上に密着して酸化物または窒化物から成る第3の絶
縁膜を形成する。第2層目の配線は、その後施される。
Structure of the Invention A first layer of wiring is formed on a semiconductor substrate on which a predetermined semiconductor device is formed, and a first insulating film made of oxide or nitride is formed on the first layer of wiring, and is tightly adhered thereon. Then, a second insulating film made of polymer resin is formed. Furthermore, a third insulating film made of oxide or nitride is formed in close contact thereon. The second layer of wiring is then applied.

この場合、酸化物または窒化物からなる第1の絶縁膜と
第3の絶縁膜とは、高分子の樹脂から成る絶縁膜の上と
下にそれぞれ施されるが、この2層の絶縁膜は同じ材料
である必要はない。
In this case, the first insulating film and the third insulating film made of oxide or nitride are respectively applied on top and bottom of the insulating film made of polymer resin, but these two insulating films are made of the same material. It doesn't have to be.

実施例の説明 本発明を図面に示す実施例を用いて詳細に説明する。第
1図において、あらかじめ所定の半導体素子が形成され
ているGaA s基板1上に、第1層目の配線2がAu
Ge/Auをo、eミクロンの厚さに蒸着後リフトオン
することにより形成されている。
DESCRIPTION OF EMBODIMENTS The present invention will be described in detail using embodiments shown in the drawings. In FIG. 1, a first layer of wiring 2 is made of Au on a GaAs substrate 1 on which predetermined semiconductor elements are formed in advance.
It is formed by evaporating Ge/Au to a thickness of 0, e microns and then lift-on.

第1の絶縁膜3としてSi3N4をプラズマCVD法を
用いて300℃の生成温度で0.4ミクロン形成する。
As the first insulating film 3, Si3N4 is formed to a thickness of 0.4 microns using a plasma CVD method at a formation temperature of 300.degree.

なおこの絶縁ノ摸3としては酸化膜でもよい。その上に
高分子の樹脂から成る第2の絶縁膜4としてポリイミド
系の” IQ (IX)IVimide 1soind
r。
Note that this insulating layer 3 may be an oxide film. On top of that, a second insulating film 4 made of polymeric resin is made of polyimide "IQ (IX)IVimide 1soind".
r.

quinazol 1nedione )を回転塗布し
、330℃で加熱硬化させる。この膜4の厚さは、2.
2ミクロンである。
quinazol 1nedione) was applied by spin coating and cured by heating at 330°C. The thickness of this film 4 is 2.
It is 2 microns.

さらに第3の絶縁膜5としてプラズマCVD法によるS
iO2膜を0.4ミクロン形成した後、第2層目の配線
6をTi / Pt /Auを蒸着後リフトオフするこ
とKより形成する。
Further, as the third insulating film 5, S is formed by plasma CVD method.
After forming an iO2 film of 0.4 microns, a second layer wiring 6 is formed by depositing Ti/Pt/Au and then lifting off.

第2図は、本発明の第2の実施例である。半導体基板1
上において、第1層の配線2および第2層目の配線6の
間に、酸化物または窒化物からなる第1の絶縁膜3、第
3の絶縁縁5、第5の絶縁5心゛ 膜8と、高分子の樹脂から成る第2の絶縁膜4、第4の
絶縁膜7とが交互に密着して形成されている。この場合
も、酸化物または窒化物から成る第1の絶縁膜3と、第
3の絶縁膜6と、第5の絶縁膜8とは、それぞれ同じ材
料である必要はなく、高分子の樹脂から成る第2の絶縁
膜4と、第4の絶縁膜7とも同じである必要はない。
FIG. 2 shows a second embodiment of the invention. Semiconductor substrate 1
Above, between the first layer wiring 2 and the second layer wiring 6, a first insulating film 3 made of oxide or nitride, a third insulating edge 5, and a fifth insulating five-core film are formed. 8, a second insulating film 4 made of polymer resin, and a fourth insulating film 7 are alternately formed in close contact with each other. In this case as well, the first insulating film 3 made of oxide or nitride, the third insulating film 6, and the fifth insulating film 8 do not need to be made of the same material, but are made of polymer resin. The second insulating film 4 and the fourth insulating film 7 do not need to be the same.

層間の接続のための開口部は、第1図の実施例の場合、
次のようにして形成する。第3の絶縁膜5であるS 1
02は、フォトレジストによるマスクを形成後、CHF
3ガスによりリアクティブイオンエツチングを行うこと
により、エツチング出来る。第2の絶縁膜4であるPI
Qは、第3の絶縁膜5をマスクとして02 ガスでリア
クティブイオンエツチングが可能である。この際フォト
レジストも除去される。その後その下の第1の絶縁膜で
あるSi3N4膜3をCF4と20チのN2ガスの混合
ガスにより、第3の絶縁膜6をマスクとしてリアクティ
ブイオンエツチングで行うことが出来る。
In the embodiment of FIG. 1, the openings for connections between layers are as follows:
Form as follows. S 1 which is the third insulating film 5
02 is CHF after forming a photoresist mask.
Etching can be performed by performing reactive ion etching using three gases. PI which is the second insulating film 4
Q can be subjected to reactive ion etching with 02 gas using the third insulating film 5 as a mask. At this time, the photoresist is also removed. Thereafter, the Si3N4 film 3, which is the first insulating film underneath, can be etched by reactive ion etching using a mixed gas of CF4 and 20 inches of N2 gas, using the third insulating film 6 as a mask.

このような積層型の絶縁膜構造を用いることにより、本
実施例の場合のように、GaAs  基板1と接する面
には、熱処理によるGaA s基板からのA8  の拡
散を防ぐことに適する813N4膜3を用いることがで
き、かつ高分子の樹脂PIQ膜4を形成することにより
クラックを生じさせることがなく膜厚を厚くすることが
出来る。さらにその上面に半導体装置に悪影響を及すN
a″−イオンに対する拡散係数の小さい513N4膜5
を形成することにより半導体装置全体の信頼性を高く出
来る。
By using such a laminated insulating film structure, as in the case of this embodiment, an 813N4 film 3 suitable for preventing diffusion of A8 from the GaAs substrate 1 due to heat treatment is provided on the surface in contact with the GaAs substrate 1. By forming the polymer resin PIQ film 4, the film thickness can be increased without causing cracks. Furthermore, the upper surface contains N, which has an adverse effect on semiconductor devices.
513N4 membrane 5 with a small diffusion coefficient for a″-ions
By forming this, the reliability of the entire semiconductor device can be increased.

第3図にGaAs基板上の絶縁膜全体の厚さと、発生す
るクラック数を示す。1の曲線はプラズマCVDによる
513N4膜のクラック数、2の曲線は本発明による絶
縁膜のクラック数を示す。これによると本発明の構造に
することにより、クラック数は同じで膜厚を厚くするこ
とが出来ることがわかる。先に示した実施例の場合、絶
縁膜の厚さは、合計3ミクロンであるので、仮に3ミク
ロンを比誘電率7.0のSi3N4膜から成る絶縁膜で
形成したとすると、比誘電率3.6のPIQ膜を2.2
7 〆・− ミクロン用いた本発明の絶縁膜と単位面積当りの静電容
量は、本発明による絶縁膜の方が約り6%小さい。
FIG. 3 shows the total thickness of the insulating film on the GaAs substrate and the number of cracks that occur. The curve 1 shows the number of cracks in the 513N4 film by plasma CVD, and the curve 2 shows the number of cracks in the insulating film according to the present invention. This shows that by adopting the structure of the present invention, the film thickness can be increased while keeping the number of cracks the same. In the case of the example shown above, the total thickness of the insulating film is 3 microns, so if 3 microns is formed of an insulating film made of Si3N4 film with a relative permittivity of 7.0, the relative permittivity is 3. .6 PIQ membrane to 2.2
The capacitance per unit area of the insulating film of the present invention using 7 μm is about 6% smaller than that of the insulating film of the present invention.

また高分子の樹脂から成る絶縁膜は、可動イオンに対し
て障壁を持つ絶縁膜によりはさまれているため、高分子
の樹脂中の不純が他の層あるいは半導体装置への影響を
軽減出来る。
Furthermore, since the insulating film made of polymeric resin is sandwiched between insulating films that have a barrier against mobile ions, the influence of impurities in the polymeric resin on other layers or the semiconductor device can be reduced.

さらに本発明の構造を用いることにより、第1層目の配
線や、半導体基板上の凹凸と段差は、高分子の樹脂の回
転塗布により平坦化される。その結果第2層目以後の信
頼性が向上し、また第2層目以後の上に形成する構造の
微細加工が可能である。丑だ、層間の開口部は、エツチ
ングガスを変えることにより、同一工程で形成すること
が出来しかも、上方にある絶縁膜をエツチングのマスク
として利用する自己整合構造となり、開口部の加工精度
も高く出来る。
Further, by using the structure of the present invention, the first layer wiring and unevenness and steps on the semiconductor substrate can be flattened by spin coating of a polymer resin. As a result, the reliability of the second and subsequent layers is improved, and fine processing of the structure formed on the second and subsequent layers is possible. By changing the etching gas, the openings between the layers can be formed in the same process. Furthermore, the openings can be formed in a self-aligned structure using the upper insulating film as an etching mask, and the openings can be formed with high precision. I can do it.

第1図に示された構成において、第4の絶縁膜7と第5
の絶縁膜8を加えることにより、第2図に示された構成
になる。これにより、第1図に示した構成の絶縁膜より
、よりいっそうNa+イオンに対する遮蔽効果が大きく
なり、絶縁耐圧も犬きぐなる。
In the configuration shown in FIG. 1, the fourth insulating film 7 and the fifth insulating film 7
By adding the insulating film 8, the structure shown in FIG. 2 is obtained. As a result, the shielding effect against Na+ ions is even greater than that of the insulating film having the structure shown in FIG. 1, and the dielectric strength voltage is also much higher.

この発明の工業的な実施に当っては、通常の絶縁膜製造
工程、およびフォトレジストの回転塗布とほぼ同じ工程
によって可能である。
Industrial implementation of the present invention can be carried out using a normal insulating film manufacturing process and a process that is almost the same as photoresist spin coating.

発明の効果 本発明によれば、層間の容量が小さく、可動イオンの拡
散も生じにくくかつ信頼性の高い絶縁膜構造を得ること
ができる。
Effects of the Invention According to the present invention, an insulating film structure with low interlayer capacitance, less likely to cause diffusion of mobile ions, and high reliability can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明における第1の実施例の半導体装置の断
面図、第2図は本発明の第2の実施例の半導体装置の断
面図、第3図は絶縁膜の膜厚と発生するクラック数との
関係を示す説明図である。 1・・・・・・半導体装置を含む半導体基板、2・・・
・・・第1層目の配線、3・・・・・・酸化物または窒
化物から成る第1の絶縁膜、4・・・・・・高分子の樹
脂から成る第2の絶縁膜、5・・・・・・酸化物または
窒化物から成る第3の絶縁膜、6・・・・・・第2層目
の配線、7・・・・・・高9べ一′ 分子の樹脂から成る第4の絶縁膜、8・・・・・・酸化
物捷たは窒化物から成る第5の絶縁膜。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is an explanatory diagram showing the relationship with the number of cracks. 1... Semiconductor substrate including a semiconductor device, 2...
...First layer wiring, 3...First insulating film made of oxide or nitride, 4... Second insulating film made of polymer resin, 5 ...Third insulating film made of oxide or nitride, 6...Second layer wiring, 7...Made of resin with a high molecular weight of 9% Fourth insulating film, 8...Fifth insulating film made of oxide or nitride. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に、酸化物または窒化物から成る第
1の絶縁膜と4、その上に高分子の樹脂から成る第2の
絶縁膜と、その上に酸化物または窒化物から成る第3の
絶縁膜とが存在することを特徴とする半導体装置。
(1) A first insulating film made of an oxide or nitride on a semiconductor substrate, a second insulating film made of a polymer resin on it, and a second insulating film made of an oxide or nitride on it. A semiconductor device characterized in that an insulating film of No. 3 is present.
(2)第1の絶縁膜と第2の絶縁膜とが交互に密着して
積み重なって形成されたことを特徴とする特許請求の範
囲第1項に記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are alternately stacked in close contact with each other.
JP18396782A 1982-10-19 1982-10-19 Semiconductor device Pending JPS5972745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18396782A JPS5972745A (en) 1982-10-19 1982-10-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18396782A JPS5972745A (en) 1982-10-19 1982-10-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5972745A true JPS5972745A (en) 1984-04-24

Family

ID=16144951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18396782A Pending JPS5972745A (en) 1982-10-19 1982-10-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5972745A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246652A (en) * 1984-05-22 1985-12-06 Nec Corp Formation of flattened conductor wiring
JPS6165456A (en) * 1984-09-07 1986-04-04 Hitachi Ltd Multilayer interconnection structure of semiconductor device
JPS63308323A (en) * 1987-06-10 1988-12-15 Nec Corp Semiconductor device
US5034044A (en) * 1988-05-11 1991-07-23 General Electric Company Method of bonding a silicon package for a power semiconductor device
US5133795A (en) * 1986-11-04 1992-07-28 General Electric Company Method of making a silicon package for a power semiconductor device
US5905298A (en) * 1996-10-03 1999-05-18 Fujitsu Limited Semiconductor device having an insulation film of low permittivity and a fabrication process thereof
US5990491A (en) * 1994-04-29 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Active matrix device utilizing light shielding means for thin film transistors
US5990542A (en) * 1995-12-14 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US6225218B1 (en) 1995-12-20 2001-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US6800875B1 (en) 1995-11-17 2004-10-05 Semiconductor Energy Laboratory Co., Ltd. Active matrix electro-luminescent display device with an organic leveling layer
US7098544B2 (en) * 2004-01-06 2006-08-29 International Business Machines Corporation Edge seal for integrated circuit chips
US7163854B2 (en) 1996-11-07 2007-01-16 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of a semiconductor device
EP3046146A1 (en) * 2015-01-14 2016-07-20 Fuji Electric Co. Ltd. High breakdown voltage passive element and high breakdown voltage passive element manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561547A (en) * 1979-06-19 1981-01-09 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561547A (en) * 1979-06-19 1981-01-09 Matsushita Electric Ind Co Ltd Semiconductor device

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0326540B2 (en) * 1984-05-22 1991-04-11 Nippon Electric Co
JPS60246652A (en) * 1984-05-22 1985-12-06 Nec Corp Formation of flattened conductor wiring
JPH0582744B2 (en) * 1984-09-07 1993-11-22 Hitachi Ltd
JPS6165456A (en) * 1984-09-07 1986-04-04 Hitachi Ltd Multilayer interconnection structure of semiconductor device
US5133795A (en) * 1986-11-04 1992-07-28 General Electric Company Method of making a silicon package for a power semiconductor device
JPS63308323A (en) * 1987-06-10 1988-12-15 Nec Corp Semiconductor device
US5034044A (en) * 1988-05-11 1991-07-23 General Electric Company Method of bonding a silicon package for a power semiconductor device
US6800873B2 (en) 1994-04-29 2004-10-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
US8319715B2 (en) 1994-04-29 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Active matrix type liquid crystal display device
US5990491A (en) * 1994-04-29 1999-11-23 Semiconductor Energy Laboratory Co., Ltd. Active matrix device utilizing light shielding means for thin film transistors
US7423291B2 (en) 1994-04-29 2008-09-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
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