JPS6260242A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6260242A
JPS6260242A JP19997485A JP19997485A JPS6260242A JP S6260242 A JPS6260242 A JP S6260242A JP 19997485 A JP19997485 A JP 19997485A JP 19997485 A JP19997485 A JP 19997485A JP S6260242 A JPS6260242 A JP S6260242A
Authority
JP
Japan
Prior art keywords
film
polyimide
psg
polyimide organic
organic film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19997485A
Other languages
Japanese (ja)
Inventor
Shinichi Tonari
真一 隣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19997485A priority Critical patent/JPS6260242A/en
Publication of JPS6260242A publication Critical patent/JPS6260242A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To improve adhesion by a method wherein one or more compounds of specified elements are implanted into the interface between a polyimide film and a film thereunder for the blending of polyimide and PSG. CONSTITUTION:On the surface of a semiconductor substrate 1 with a prescribed semiconductor element built thereon is covered by a groundwork film that is a PSG film 2 of a required thickness. A lower wiring layer 3 of aluminum or the like is formed on the PSG film 2. A polyimide layer is formed by application on the entire surface, covering the lower wiring layer 3 and PSG film 2. Ion implantation follows, wherein one or more out silicon, nitrogen, carbon, oxygen, hydrogen, or their compounds are driven into the polyimide film 4. The implantation is so effected that the implanted ions may form an ion implanted layer 5 in the vicinity of the interface of the poplyimide film 4 and PSG film 2. In this way, the two films 2 and 4 are allowed to be physically blended with each other, which results in a stronger adhesion between the two films 2 and 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線構造を有する半導体装置の製造方法に
関し、特に眉間絶縁膜としてポリイミド有機膜を用いた
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure, and particularly to a method for manufacturing a semiconductor device using a polyimide organic film as a glabellar insulating film.

〔従来の技術〕[Conventional technology]

近年における半導体装置の微細化及び高集積化に伴って
、半導体基板上に形成する配線の多層化が進められてい
る。従来、この種の多層配線では層間絶縁膜としてCV
D法により形成したシリコン酸化膜やシリコン窒化膜を
用いているが、これらの膜は表面における平坦性極めて
悪く、この上に形成する上側配線層に段切れ等の不具合
を生じ、配線を微細化する上での障害となっている。こ
のため、これまでの半導体装置の製造工程では層間絶縁
膜の表面の平坦化を図るための工程が必須のものとされ
ており、この平坦化のための工程が半導体装置の製造工
程を複雑化し、かつ製造工程数を増大させる原因となっ
ている。
2. Description of the Related Art With the miniaturization and higher integration of semiconductor devices in recent years, the number of layers of wiring formed on a semiconductor substrate is increasing. Conventionally, in this type of multilayer wiring, CV was used as an interlayer insulating film.
Silicon oxide films and silicon nitride films formed by the D method are used, but these films have extremely poor surface flatness, causing defects such as step breaks in the upper wiring layer formed on top of them, making it difficult to miniaturize the wiring. It is an obstacle to doing so. For this reason, in the conventional manufacturing process of semiconductor devices, a process to planarize the surface of the interlayer insulating film is essential, and this flattening process complicates the manufacturing process of semiconductor devices. , and causes an increase in the number of manufacturing steps.

このようなことから、最近では層間絶縁膜にポリイミド
有機膜を使用する試みがなされており、このポリイミド
有機膜の特質により十分な平坦性が得られている。
For this reason, attempts have recently been made to use a polyimide organic film as an interlayer insulating film, and the characteristics of this polyimide organic film provide sufficient flatness.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように眉間絶縁膜にポリイミド有機膜を使用し
た場合、その下地膜にPSG膜を用いている半導体装置
では、ポリイミド有機膜とPSG膜との密着性(接着性
)が乏しく、層間絶縁膜乃至上層配線層の剥離を招き、
半導体装置としての信頼性が低下される等の問題が生じ
ている。この密着性についての詳細な原因、メカニズム
は明らかではないが、本発明者の検討によれば、両者の
界面において双方の膜が化学的或いは物理的に結合する
度合が小さいこと、またポリイミド有機膜はPSG膜に
比較して熱膨張係数が1〜2桁程大きいために熱的スト
レスを受は易いことが関係しているものと思われる。
As mentioned above, when a polyimide organic film is used as an insulating film between the eyebrows, in semiconductor devices that use a PSG film as the underlying film, the adhesion between the polyimide organic film and the PSG film is poor, and the interlayer insulating film This may lead to peeling of the upper wiring layer,
Problems have arisen, such as reduced reliability as a semiconductor device. The detailed cause and mechanism of this adhesion are not clear, but according to the inventor's study, the degree of chemical or physical bonding between the two films at the interface is small, and the polyimide organic film This seems to be related to the fact that the film has a coefficient of thermal expansion one to two orders of magnitude larger than that of the PSG film, so it is easily subjected to thermal stress.

〔問題点を解決するための手段〕 、 本発明の半導体装置の製造方法は、眉間絶縁膜としての
ポリイミド有機膜と、下地膜としてのPSG膜との密着
性を向上して信頼性の高い半導体装置を得るために、ポ
リイミド有機膜を形成した後、珪素、窒素、炭素、酸素
、水素及びこれらの元素の化合物の中のいずれか一種或
いは複数種をポリイミド有機膜と下地膜との界面にイオ
ン注入し、両者の界面においてポリイミドとPSGとを
混合せしめてその密着性を向上させる工程を有している
[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention improves the adhesion between the polyimide organic film as the glabella insulating film and the PSG film as the base film, thereby producing a highly reliable semiconductor. In order to obtain a device, after forming a polyimide organic film, one or more of silicon, nitrogen, carbon, oxygen, hydrogen, and compounds of these elements are ionized at the interface between the polyimide organic film and the underlying film. The process includes a step of mixing polyimide and PSG at the interface between the two to improve their adhesion.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図乃至第4図は本発明の一実施例を製造工程順に示
す断面図である。
1 to 4 are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps.

先ず、第1図のように、所定の半導体素子を形成した半
導体基板1の表面上に下地膜としてのPSG膜2を所要
の厚さに形成し、この−ヒにアルミニウム等の金属膜か
らなる下側配線層3を形成する。
First, as shown in FIG. 1, a PSG film 2 as a base film is formed to a required thickness on the surface of a semiconductor substrate 1 on which a predetermined semiconductor element is formed, and then a metal film such as aluminum is formed on this film. A lower wiring layer 3 is formed.

次いで、第2図のように、ポリイミド有機材をスピンコ
ード法によって全面に塗布し、前記下側配線層3及びP
SG膜2を覆うポリイミド有機膜4を形成する。このポ
リイミド有機膜4の膜厚は、前記下側配線層3の厚さや
線幅等の下地構造に見合うだけの平坦性及び電気的特性
(例えば、層間静電容量)に応じた厚さとし、通常では
1μmに形成する。
Next, as shown in FIG. 2, a polyimide organic material is applied over the entire surface by a spin code method, and
A polyimide organic film 4 covering the SG film 2 is formed. The film thickness of this polyimide organic film 4 is determined to be a thickness that corresponds to the underlying structure such as the thickness and line width of the lower wiring layer 3, and the flatness and electrical characteristics (for example, interlayer capacitance). Then, it is formed to have a thickness of 1 μm.

しかる上で、第3図のように、珪素、窒素、炭素、酸素
、水素及びこれらの元素の化合物の中、いずれか一種或
いは複数種を前記ポリイミド有機膜4内にイオン注入法
によって導入する。この際、注入物がポリイミド有機膜
4とPSG膜2との界面近傍に分布されてイオン注入層
5を形成するようにイオン注入時の加速電圧を制御する
。例えば、珪素では約250KeV 、窒素では約15
0KeV、炭素では約200KeV、酸素では約150
KeV、水素では約30KeVに夫々設定する。
Then, as shown in FIG. 3, one or more of silicon, nitrogen, carbon, oxygen, hydrogen, and compounds of these elements are introduced into the polyimide organic film 4 by ion implantation. At this time, the acceleration voltage during ion implantation is controlled so that the implanted material is distributed near the interface between the polyimide organic film 4 and the PSG film 2 to form the ion implantation layer 5. For example, about 250 KeV for silicon and about 15 KeV for nitrogen.
0KeV, about 200KeV for carbon, about 150 for oxygen
KeV and hydrogen are set to about 30 KeV, respectively.

そして、第4図のように、下側配線層3に接続させるた
めのコンタクトホール7を形成する場合には、シリコン
酸化膜とフォトレジスト膜との積層構造のマスク膜6を
形成し、CF、を主体としたガスプラズマ中でシリコン
酸化膜を開孔し、また酸素ガスプラズマでポリイミド有
機膜4を開孔する。しかる上で、同図鎖線のようにアル
ミニウム等で上側配線層8を形成することにより、上側
配線層8と下側配線層2とをコンタクトホール7を通し
て接続させることができる。
As shown in FIG. 4, when forming a contact hole 7 for connection to the lower wiring layer 3, a mask film 6 having a laminated structure of a silicon oxide film and a photoresist film is formed, and CF, A silicon oxide film is opened in a gas plasma mainly composed of , and a polyimide organic film 4 is opened in an oxygen gas plasma. In addition, by forming the upper wiring layer 8 of aluminum or the like as indicated by the chain line in the figure, the upper wiring layer 8 and the lower wiring layer 2 can be connected through the contact hole 7.

したがって、このようにして製造された多層配線構造で
は、眉間絶縁膜としてのポリイミド有機膜4は、下地膜
としてのPSG膜2との界面に前述した種々の元素種の
イオン注入層5が形成されることになるため、両膜2.
4が界面において互いに物理的に混合し、両者の密着性
を向−トさせることになる。これにより、ポリイミド有
機膜4がPSG膜2から容易に剥離されることもなく、
多層配線構造、即ち半導体装置の信頼性を向上すること
ができる。勿論、ポリイミド有機膜の特性により、その
表面の平坦性を極めて良好なものにでき、上側配線層8
における段切れ等を防止して、配線の微細化を達成でき
ることは言うまでもない。
Therefore, in the multilayer wiring structure manufactured in this way, the polyimide organic film 4 as the glabella insulating film has the ion-implanted layer 5 of the various element types described above formed at the interface with the PSG film 2 as the base film. Therefore, both membranes 2.
4 physically mix with each other at the interface, improving the adhesion between the two. This prevents the polyimide organic film 4 from being easily peeled off from the PSG film 2.
The reliability of the multilayer wiring structure, that is, the semiconductor device can be improved. Of course, due to the characteristics of the polyimide organic film, its surface can be extremely flat, and the upper wiring layer 8
Needless to say, it is possible to achieve miniaturization of wiring by preventing step breaks and the like.

なお、前記実施例ではイオン注入層5を下側配線層3と
ポリイミド有機膜4との界面にも形成しており、両者間
での密着性を改善することもできる。
In the embodiment described above, the ion implantation layer 5 is also formed at the interface between the lower wiring layer 3 and the polyimide organic film 4, so that the adhesion between the two can be improved.

〔発明の効果〕〔Effect of the invention〕

以」二説明したように本発明は、層間絶縁膜としてのポ
リイミド有機膜と、下地膜としてのPSG膜とを有する
多層配線構造の製造に際し、ポリイミド有機膜を形成し
た後、珪素、窒素、炭素、酸素、水素及びこれらの元素
の化合物の中のいずれか一種或いは複数種をポリイミド
有機膜と下地膜との界面にイオン注入しているので、両
者の界面においてポリイミドとPSGとを混合せしめて
その密着性を向上させることができ、ポリイミド有機膜
の長所である表面平坦性を利用して上側配線層の微細化
を図るとともにポリイミド有機膜の剥離等を防止し、高
集積でかつ信頼性の高い半導体装置を製造することがで
きる。
As explained below, in the present invention, when manufacturing a multilayer interconnection structure having a polyimide organic film as an interlayer insulating film and a PSG film as an underlying film, silicon, nitrogen, and carbon are added after forming the polyimide organic film. , oxygen, hydrogen, and compounds of these elements are ion-implanted into the interface between the polyimide organic film and the underlying film. Adhesion can be improved, and the upper wiring layer can be made finer by utilizing the surface flatness, which is an advantage of polyimide organic films, and peeling of the polyimide organic film can be prevented, resulting in high integration and reliability. Semiconductor devices can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第4図は本発明の製造方法を工程順に示す断
面図である。 1・・・半導体基板、2・・・下地膜(PSG膜)、3
・・・下側配線層、4・・・ポリイミド有機膜、5・・
・イオン注入層、6・・・マスク、7・・・コンタクト
ホール、8・・・上側配線層。 代理人 弁理士   内 原  晋、、’、’、’、M
払(・イ5;7.J −7’rJ’r’E/ \−−/′ −へ      の べ       憾       帳 寸 怖
1 to 4 are cross-sectional views showing the manufacturing method of the present invention in the order of steps. 1... Semiconductor substrate, 2... Base film (PSG film), 3
... Lower wiring layer, 4... Polyimide organic film, 5...
- Ion implantation layer, 6... mask, 7... contact hole, 8... upper wiring layer. Agent Patent Attorney Susumu Uchihara,,',',',M
Pay (・I5; 7.J -7'rJ'r'E/ \--/' -to 达 Sorry for the loss)

Claims (1)

【特許請求の範囲】 1、層間絶縁膜としてのポリイミド有機膜と、下地膜と
してのPSG膜とを有する多層配線構造の半導体装置の
製造に際し、前記ポリイミド有機膜を形成した後、珪素
、窒素、炭素、酸素、水素及びこれらの元素の化合物の
中のいずれか一種或いは複数種をポリイミド有機膜と下
地膜との界面にイオン注入する工程を備え、これら両者
の界面においてポリイミドとPSGとを混合せしめるこ
とを特徴とする半導体装置の製造方法。 2、下地膜の上にPSG膜を形成するとともに、この下
側配線層の上にポリイミド有機膜を形成し、しかる上で
ポリイミド有機膜の表面から所要の加速電圧でイオン注
入を行ってなる特許請求の範囲第1項記載の半導体装置
の製造方法。
[Claims] 1. When manufacturing a semiconductor device with a multilayer wiring structure having a polyimide organic film as an interlayer insulating film and a PSG film as a base film, after forming the polyimide organic film, silicon, nitrogen, A step of ion-implanting one or more of carbon, oxygen, hydrogen, and compounds of these elements into the interface between the polyimide organic film and the base film, and mixing the polyimide and PSG at the interface between the two. A method for manufacturing a semiconductor device, characterized in that: 2. A patent in which a PSG film is formed on a base film, a polyimide organic film is formed on this lower wiring layer, and then ions are implanted from the surface of the polyimide organic film at a required acceleration voltage. A method for manufacturing a semiconductor device according to claim 1.
JP19997485A 1985-09-09 1985-09-09 Manufacture of semiconductor device Pending JPS6260242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19997485A JPS6260242A (en) 1985-09-09 1985-09-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19997485A JPS6260242A (en) 1985-09-09 1985-09-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6260242A true JPS6260242A (en) 1987-03-16

Family

ID=16416680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19997485A Pending JPS6260242A (en) 1985-09-09 1985-09-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6260242A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63278258A (en) * 1987-05-09 1988-11-15 Fujitsu Ltd Manufacture of semiconductor device
US6177343B1 (en) 1995-09-14 2001-01-23 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6214749B1 (en) 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US6235648B1 (en) 1997-09-26 2001-05-22 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6326318B1 (en) 1995-09-14 2001-12-04 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
US6831015B1 (en) 1996-08-30 2004-12-14 Sanyo Electric Co., Ltd. Fabrication method of semiconductor device and abrasive liquid used therein
US6917110B2 (en) 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63278258A (en) * 1987-05-09 1988-11-15 Fujitsu Ltd Manufacture of semiconductor device
US6214749B1 (en) 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US6177343B1 (en) 1995-09-14 2001-01-23 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6268657B1 (en) 1995-09-14 2001-07-31 Sanyo Electric Co., Ltd. Semiconductor devices and an insulating layer with an impurity
US6326318B1 (en) 1995-09-14 2001-12-04 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
US6831015B1 (en) 1996-08-30 2004-12-14 Sanyo Electric Co., Ltd. Fabrication method of semiconductor device and abrasive liquid used therein
US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6235648B1 (en) 1997-09-26 2001-05-22 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US6917110B2 (en) 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer

Similar Documents

Publication Publication Date Title
US3801880A (en) Multilayer interconnected structure for semiconductor integrated circuit and process for manufacturing the same
EP0238089B1 (en) Three-dimensional integrated circuit and manufacturing method therefor
JPH0613470A (en) Manufacture of semiconductor device
JPS6260242A (en) Manufacture of semiconductor device
US6960492B1 (en) Semiconductor device having multilayer wiring and manufacturing method therefor
US20070082475A1 (en) Method for forming bonding pad and semiconductor device having the bonding pad formed thereby
JPH0620102B2 (en) Semiconductor device and manufacturing method thereof
JPS6070743A (en) Manufacture of semiconductor device
US5793103A (en) Insulated cube with exposed wire lead
US5609772A (en) Cube maskless lead open process using chemical mechanical polish/lead-tip expose process
JPH0230137A (en) Method forming wiring of semiconductor device
JPH06267935A (en) Manufacture of semiconductor device
JPH0817923A (en) Semiconductor integrated circuit device and its manufacture
JPH0117254B2 (en)
JPS5966150A (en) Semiconductor device and manufacture thereof
JPH11274296A (en) Multilayer wiring structure and method of forming the same
KR100246101B1 (en) Multi-layer metal wiring structure of semiconductor device
JPS61260639A (en) Manufacture of semiconductor device
JPH0794490A (en) Etching method
JPS6347946A (en) Manufacture of semiconductor device
JPH0462855A (en) Semiconductor device and manufacture thereof
KR20020057340A (en) Multi-interconnection structure of semiconductor device and method for fabricating the same
JPS62293644A (en) Manufacture of semiconductor device
JPH05308072A (en) Manufacture of semiconductor integrated circuit
JPH0410420A (en) Manufacture of semiconductor integrated circuit