JPS6276564A - Semiconductor device - Google Patents

Abstract

PURPOSE:To remove the partial charge of the surface of a chip, and to prevent the malfunction of a semiconductor integrated circuit by forming a conductive thin film onto a final protective insulating film on the surface of the chip, to which an EPROM integrated circuit is formed, in a meshy or striped manner and using the conductive thin film as an antistatic means. CONSTITUTION:A wiring 3 consisting of an N<+> diffusion layer and an insulator layer 4 on the surface of a chip are shaped to an Si semiconductor substrate (the chip) 2, and the semiconductor device consists of a thermal oxide film (SiO2) on the surface of the substrate, an inter-layer insulating film such as PSG and a final protective insulating film, and contains multilayer electrodes and wirings. Conductive films 8 through the evaporation of Al are shaped in a meshy or striped manner at some intervals onto the final protective insulating film as antistatic films. The Al evaporated films are formed in the meshy or striped manner on a wiring such as an Al electrode wiring (a data line) 9 as a first layer or along sections such as the superposing sections 11 of the first layer Al wiring and poly Si wirings 10, avoiding sections required for the transmission of ultraviolet rays for erasing the informations of an EPROM memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for preventing static electricity on the surface of a semiconductor integrated circuit chip.

EP ROM (Erasable Program
In ReadOnly Memory), in order to erase the information stored in the memory cell by UV irradiation, after wire bonding between the IC (semiconductor integrated circuit) chip and the lead, quartz or sapphire is exposed to UV light (λ-250OA). On the other hand, the lid (cap) or window of the package is made of a highly transparent material to seal the package. The lid or window of such a package is transparent to ultraviolet rays and is an almost perfect electrical insulator, that is, a dielectric material. On the other hand, A-gt& wiring is provided on the surface of the memory cell area of the IC chip, and CV D
(Chemical Vaporl) epositio
n) PSG (Phosph.

The surface resistivity is 1Q14~1015Ω/mm, and the surface resistivity is high.

In a semiconductor device having such a structure, as shown in FIG.
When static electricity is charged due to rubbing or Freon spray, an electric field is generated in the space inside the cap (between the semiconductor chip surface and the transparent window) due to the electrostatic potential on the surface of the semiconductor chip 2 and the electrostatic potential on the transparent window, and the strength of this electric field increases. is about 15~
When the voltage exceeds 30I (V/tan), corona discharge 3 occurs and the charge moves to the chip surface. Distance d between the chip surface and the transparent window
Since the voltage is about INIL, if the cap is charged with static electricity of 1500 V or more, the charge will move.

If a positive charge is applied to the surface of the bancipation film (protective film) 4 of the n-channel EFROM.

And its potential is 50■ (based on the Si substrate)
Vth of the parasitic channel seen from the bancivation surface
), a current bus will be generated between the isolated (separated) Beginn+ wires 5, resulting in malfunction of the device, especially the EPROM.

In order to solve the above-mentioned drawbacks of the prior art, the inventors of the present application have proposed that the charges locally charged on the chip surface be spread over the entire surface of the chip to make them uniform, thereby eliminating the high potential areas, or We focused on the fact that it is sufficient to make the charge on the chip surface the same as the ground line by dropping the charge on the ground. Therefore, an object of the present invention is to eliminate local charging on the chip surface caused by static charges generated on the package lid, thereby preventing malfunction of a semiconductor integrated circuit, and providing a highly reliable semiconductor device.

In order to achieve the above object, the gist of the present invention is to form a conductive thin film in the form of a mesh or stripe on the final protective insulating coating on the surface of the chip on which the EPROM integrated circuit is formed to serve as an antistatic means.

The present invention will be described in detail below with reference to Examples.

FIG. 2 is a sectional view of an EPROM semiconductor device showing the principle of an embodiment of the present invention. In the figure, 2 is a Si semiconductor substrate (chip), 5 is a wiring made of an n+ diffusion layer, 4 is an insulating layer on the surface of the chip, and a thermal oxide film (S10) on the surface of the substrate.
2) It consists of an interlayer insulating film such as PSG and a final protective insulating film, and includes multilayer electrodes and wiring (not shown).

On the final protective insulating film, a conductive film 8 is formed by AA vapor deposition as an antistatic film, partially at certain intervals, that is, in the form of a mesh or stripes. As shown in the plan view of FIG. 3, this AA vapor-deposited film is applied onto the AA electrode wiring (data line) 9 of the first layer, for example, by avoiding the area necessary for ultraviolet 1 transmission to erase information in the EPROM memory cell. Or the first layer Al
It is formed in a mesh shape or a stripe shape along the overlapping portion 11 of the wiring and the polySI wiring 10. The wiring of this antistatic Aa vapor deposited film may be connected to the substrate potential terminal, or may not be particularly connected. FIG. 4 shows an example of a layout in which an opaque conductive film is formed in a mesoche shape within a pellet. In this case, the entire surface of the peripheral circuit (hatched portion) 12 that is not required to transmit ultraviolet light is covered with a conductive film, only the memory cell portion 13 is wired in a mesh or stripe shape, and the chip peripheral portion 14 outside the bonding pad 7 is It becomes connected to the substrate potential.

The opaque conductive thin film is formed as follows.

(a) Conductor film formation: In addition to A2, M6°W or toppo IJ Si may be used as the conductor, and any of vapor deposition, sputtering, and CVD may be used as the thin film forming method.

(b) Photoetching of conductor thin film: pattern is third
It becomes as shown in the figure and FIG.

(C) The final pansivation film on the bonding pad portion is removed by photoetching.

According to the present invention shown in the above embodiments, the objects of the invention can be achieved for the following reasons.

The distance between the AA meshes is sufficiently small compared to the distance between the chip and the transparent window, and corona discharge from the window occurs against the A2 grid, so no local charge accumulation occurs.
Device characteristics will not deteriorate.

According to the present invention, even when using a mensche-like metal thin film, the effect can be obtained even if it is not necessarily connected to the substrate potential because the purpose can be achieved to some extent by eliminating local potential build-up. Probably.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the principle structure of a conventional EPROM in which charging occurs, and FIG. 2 is a cross-sectional view of an EPROM according to the present invention.
In the example of
The figure corresponds to the embodiment shown in Fig. 2 and is a partial plan view showing the positional relationship between the antistatic film and the electrode wiring, and Fig. 4 shows the pattern of the formation position of the antistatic film in the pellet in the embodiment shown in Fig. 2. FIG. 1... Transparent window, 2... Semiconductor chip, 3... Corona discharge, 4... Pansivation (maintenance MIW), 5...
... n+ wiring, 6... Nesa film, 7... bonding bathode, 8... mesh-like conductive film, 9... first layer 1
3 electrode wire, 10... poly-Si wiring, work 1... overlapping portion of first layer Aa electrode wire and poly-Si wiring, 12... peripheral circuit section, 13... memory cell section, 14...・Around the chip. Agent: Patent Attorney Katsoo Ogawa Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. A semiconductor device characterized in that a mesh-like or stripe-like conductive thin film is formed on a final protective insulating film on the surface of a chip on which an EPROM is formed. 2. The semiconductor device according to claim 1, wherein the conductive thin film is connected to a substrate potential terminal.