CN1979860A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- CN1979860A CN1979860A CN 200610166739 CN200610166739A CN1979860A CN 1979860 A CN1979860 A CN 1979860A CN 200610166739 CN200610166739 CN 200610166739 CN 200610166739 A CN200610166739 A CN 200610166739A CN 1979860 A CN1979860 A CN 1979860A
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Abstract
A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.
Description
Technical field
The present invention relates to the filler that prevents the sealing resin is set on the Semiconductor substrate of utilizing the wiring layer that interlayer dielectric insulate corrodes the semiconductor device of buffering coating film of usefulness and the manufacture method of semiconductor device having.
Background technology
In recent years, along with the miniaturization of semiconductor integrated circuit, highly integrated, miniaturization such as the wiring of the metal line in the power-supply wiring that forms on the Semiconductor substrate etc. at interval makes progress, and adopts the little low-k film of dielectric constant, to suppress the parasitic capacitance of interlayer dielectric.Yet, compare with interlayer dielectric in the past, not only film is withstand voltage low, and the thickness of low-k film is little, forms finelyr at interval than the wiring of metal line, and it is essential and important to prevent that device management that the electrostatic breakdown of interlayer dielectric is used and process management from becoming.Electrostatic breakdown in the semiconductor device, discharge owing to the charged electric charge of friction in the static that stays because of people itself, manufacturing process or the conveying operation, therefore outside input and output terminal is applied extremely several kilovolts high pressure of several hectovolts quickly, make grid oxidation film, interlayer dielectric and metal line produce insulation breakdown, cause the IC circuit working bad.As the measure that solves electrostatic breakdown, cmos device comprises the protective circuit of resistance and diode by input and output terminal setting externally, prevents from the IC circuit is applied overvoltage protection IC circuit.
Here, Fig. 7 is the circuit diagram that the protective circuit on routine existing external input terminals is shown.
The structure that has in the protective circuit of Fig. 7; when applying high pressure; utilize resistance 112 will apply voltage and be attenuated to the degree that applies noise; make electric current leak into power supply (Vcc) line and ground connection (GND) line by protection diode 113, protection diode 114 during this period; thereby prevent from grid oxidation film 111 is directly applied the high pressure that discharge causes, protection device.This translation circuit is because the electric current of protection diode 113,114 circulation is limited, applying under the big situation of energy that noise has, and diode also junction breakdown can take place sometimes.Here, resistance 112 is made of diffusion layer and polysilicon, is generally 1 kilo-ohm to 10 kilo-ohms.
Fig. 8 is the cutaway view that near the example of structure the element electrode of existing semiconductor device is shown.
Among Fig. 8, for example Semiconductor substrate 101, and then Semiconductor substrate 101 inside have interlayer dielectric 102 and metal line 103.Be provided with on the Semiconductor substrate 101 and carry out a plurality of element electrodes 104 that outside input/output signal is used, and have part or all passivating film 105 that opens wide that makes on the element electrode 104, prevent in addition on the passivating film 105 that the filler of sealing resin from corroding the buffering coating film 106 of usefulness.The material of buffering coating film 106 generally adopts this insulation organic material of polyimides, and thickness is several microns.With the various films that form on the Semiconductor substrate 101 be hundreds of nanophase ratio, the thickness of buffering coating film 106 is very thick, and the surface of buffering coating film 106 has electronegative characteristic easily.General common aluminium, the copper etc. of adopting of the material of metal line 103.
As shown in Figure 8, in the existing semiconductor device, the static that manufacturing process and manufacturing installation take place makes buffering coating film 106 surfaces on the Semiconductor substrate 101 accumulate electric charge, thereby produces parasitic capacitance 107 between electric charge that accumulates and the metal line 103.Because parasitic capacitance 107, electric charge is accumulated on the surface of buffering coating film 106 in rapid succession continuously, but when accumulating the electric charge that is not less than certain degree, and produce because of parasitic capacitance 107 between the immediate element electrode 104 of potential difference and discharge, internal circuit is applied high pressure.Resistance 112 in the existing protective circuit shown in Figure 7 or protection diode 113,114 can not be followed the tracks of the noise that applies that this high pressure causes, and are difficult to protect grid oxidation film 111.And, when surpassing interlayer dielectric 102 withstand voltage, the destruction of interlayer dielectric 102 and the fusing of metal line 103 take place, sometimes between the interlayer dielectric 102 or produce the disadvantage of open circuit or short circuit between the metal line 103.In the assembling procedure, the operation in atmosphere is many, and in order to be cut into a sheet from wafer, the easiest this film from the outside of static that is subjected to rings.Especially in back-grinding or bond sequence, extremely several kilovolts electric charge of hundreds of volt is accumulated on the surface of buffering coating film 106, thereby utilizes the electricity that disappears of ionizer essential.
Yet, because the miniaturization of diffusion technology in recent years, with conventional interlayer dielectric withstand voltage 10
7Volt/centimetre compare, the withstand voltage of low-k film that interlayer dielectric 102 uses (is not more than 10
6Volt/centimetre) low, antistatic behaviour reduces, and exists static to cause the problem of semiconductor device fault finally successively.
The present invention is used to address the above problem, and its purpose is to provide the manufacture method of a kind of semiconductor device and semiconductor device, and antistatic behaviour is improved, and prevents the electrostatic breakdown of metal line or interlayer dielectric.
Summary of the invention
In order to achieve the above object, semiconductor device of the present invention is characterized by: have the Semiconductor substrate that forms semiconductor integrated circuit and element electrode; The buffering coating film that on the protection dielectric film that forms on the described Semiconductor substrate, described protection dielectric film, forms in described semiconductor integrated circuit district; And the conduction region that is electrically connected with described buffering coating film.
It is characterized by: one or more bights that described conduction region are arranged on described Semiconductor substrate again.
Its feature is again: the periphery in described Semiconductor substrate is arranged to ring-type with described semiconductor region.
Its feature is again: the inhibition pattern is peeled off at the sealing ring or the angle that form on the described Semiconductor substrate, as described conduction region.
Its feature is again: described buffering coating film is extended to the zone of the described conduction region of described formation, be connected with described conduction region.
Its feature is again to spread all over a plurality of wiring layers district and form described conduction region.
Its feature is again: spread all over a plurality of wiring layers district described conduction region is arranged to helical form.
Its feature is again: spread all over the semiconductor silicon substrate and form described conduction region.
And, it is characterized by: have the Semiconductor substrate that forms semiconductor integrated circuit and element electrode; The protection dielectric film that on described Semiconductor substrate, forms; And being formed on the described protection dielectric film in described semiconductor integrated circuit district, and the buffering coating film that is connected with one or more grounding electrodes in the described element electrode.
Its feature is again: described buffering coating film is extended, and be connected to described grounding electrode.
Moreover, it is characterized by: when having the conduction region that forms the electrostatic withstand voltage raising usefulness that makes semiconductor device, on the Semiconductor substrate that forms semiconductor integrated circuit and element electrode, form the 1st operation of described conduction region; On Semiconductor substrate, form the 2nd operation be provided with the protection dielectric film that makes the opened portion that described conduction region and described element electrode expose; And the 3rd operation that on described protection dielectric film, forms the buffering coating film that is connected with the described conductive layer that exposes in the described opened portion.
Its feature is again: in described the 1st operation, from lower floor, form described conduction region with circuit simultaneously with metal line.
Its feature is again: in described the 1st operation, spread all over the dense zone of p type impurity concentration of the p type island region of the silicon portion that is arranged on described Semiconductor substrate, form described conduction region.
Again, it is characterized by: have when forming the electrostatic withstand voltage make semiconductor device and improving the conduction region of usefulness, form the 1st operation that is provided with the protection dielectric film that makes the opened portion that described element electrode exposes on semiconductor integrated circuit and the element electrode Semiconductor substrate forming; And the 2nd operation that on described protection dielectric film, forms the buffer film that is connected with one or more grounding electrodes in the described element electrode that exposes in the described opened portion.
Description of drawings
Figure 1A is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 1.
Figure 1B is the crucial portion cutaway view of the semiconductor device of the embodiment of the invention 1.
Fig. 2 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 2.
Fig. 3 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 3.
Fig. 4 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 4.
Fig. 5 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 5.
Fig. 6 A is the operation cutaway view that the PD layer formation operation of semiconductor device of the present invention is shown.
Fig. 6 B is the operation cutaway view that the wiring layer formation operation of semiconductor device of the present invention is shown.
Fig. 6 C is the operation cutaway view that the buffering coating film formation operation of semiconductor device of the present invention is shown.
Fig. 7 is the circuit diagram that the protective circuit on routine existing external input terminals is shown.
Fig. 8 is near the cutaway view of the example of structure the element electrode that illustrates in the existing semiconductor device.
Embodiment
Below, with reference to the description of drawings embodiments of the invention.
Fig. 1 is the figure that the semiconductor device of the embodiment of the invention 1 is shown, and Figure 1A is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 1, and Figure 1B is the crucial portion cutaway view of the semiconductor device of the embodiment of the invention 1, is the cutaway view of the A-A ' line of Figure 1A.
Fig. 2 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 2, and Fig. 3 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 3.
Fig. 4 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 4, and Fig. 5 is the crucial portion vertical view of the semiconductor device of the embodiment of the invention 5.
Fig. 6 is the operation cutaway view of part manufacture method that the semiconductor device of the embodiment of the invention 1 is shown, Fig. 6 A is the operation cutaway view that the PD layer formation operation of semiconductor device of the present invention is shown, Fig. 6 B is the operation cutaway view that the wiring layer formation operation of semiconductor device of the present invention is shown, and Fig. 6 C is the operation cutaway view that the buffering coating film formation operation of semiconductor device of the present invention is shown.
Embodiment 1
Among Fig. 1, form in inside on the Semiconductor substrate 11 of the semiconductor integrated circuit constitute by semiconductor elements such as transistors, be provided with and carry out a plurality of element electrodes 12 that outside input/output signal is used.At whole of the Semiconductor substrate 11 that at least a portion on the element electrode 12 is opened wide, form the passivating film 13 of conduct protection dielectric film, and on the passivating film 13 in the semiconductor integrated circuit formation district, form the buffering coating film 14 that insulate.This sensitization organic material of buffering coating film 14 general employing polyimides, and utilize the optical graving platemaking technology to form pattern accurately, thickness is several microns.Bight 16 in Semiconductor substrate 11 forms conduction region 15-1, and at least a portion of conduction region 15-1 is identical with element electrode 12, also passivating film 13 is opened wide, thereby is exposed.The part of the conduction region 15-1 that exposes has the wiring of the surperficial end of contact buffering coating film 14, and formation will cushion the conductive path that the electric charge that the surface of coating film 14 accumulates flows to conduction region 15-1.The easiest electric charge that accumulates in periphery surface of buffering coating film 14 is the high zones of charge density, so the possibility of discharging is big.Therefore, the structure of formation is provided with conductive path by the bight 16 in Semiconductor substrate 11, easily the element electrode 12 past conduction region 15-1 circulation electric charges from exposing metal.The conduction region 15-1 that forms on the bight 16 is so long as the pattern that can form, and whatsoever the shape of sample is all no problem.Form the example of the conduction region 15-1 of ring-type shown in the figure in the outside of the photoetching plate-making alignment mark that forms ring-type, but also the electric conducting material of available wiring layer etc. forms photoetching plate-making alignment mark, and conductive path with conduction region 15-1 is set, thereby form the conduction region of double-ring structure, the alignment mark of also photoetching can being made a plate moves makes conduction region 15-1 usefulness.And, bigger in order to ensure the formation area of conduction region 15-1, can be formed on the outside in bight 16, the charge capacity of conduction region 15-1 is increased, improve antistatic behaviour.
The electric charge that accumulates by the surface of buffering coating film 14 discharges to conduction region 15-1, can prevent the insulation breakdown and the IC circuit damage of interlayer dielectric 18.Because discharge, 15-1 applies high pressure to conduction region, and insulation breakdown takes place sometimes in this district, but conduction region 15-1 is formed on this zone that separates with element circuitry, bight 16 of Semiconductor substrate 11, so circuit characteristic is had no effect.And, form conduction region 15-1 in a plurality of bights of Semiconductor substrate 11, the conductive paths of the electric charge that accumulates on many buffering coating film surfaces are set, thereby the charge density that the surface of buffering coating film 14 is accumulated reduces further, suppresses the generation of discharge itself.The bight 16 of Semiconductor substrate 11 is concentrated positions such as shrinkage stress of the sealing resin of assembly, peeling off of the easiest generation interlayer dielectric 18, thereby the inhibition pattern is peeled off in setting sometimes, effectively utilize as conduction region 15-1 but this can be peeled off pattern, the quality of circuit aspect is had no effect.Conduction region 15-1 can use circuit metal line 19 identical materials with the IC circuit, particularly, adopts aluminium (Al), copper metal materials such as (Cu).
In sum, the conduction region that is electrically connected with buffering coating film is set by 1 bight in Semiconductor substrate at least, make that charged electric charge discharges to conduction region on the buffering coating film, thereby can suppress that discharge to element electrode causes circuit region is applied high pressure, prevent the electrostatic breakdown of metal line or interlayer dielectric, the antistatic behaviour of semiconductor device is improved.
And, among Fig. 1, conduction region 15-1 is electrically connected at least 1 metal line 15a that the wiring that forms on the wiring layer is electrically connected, and the electric charge that the surface of buffering coating film 14 is accumulated flow into metal line 15a, and the surface charge density of buffering coating film 14 is reduced.As the method that surface charge density is reduced, also can constitute by making metal line 15a connect Semiconductor substrate 11, the electric charge that the surface of buffering coating film 14 is accumulated flows into Semiconductor substrate 11.On the P type substrate on the Semiconductor substrate 11, form the dense p type diffusion region of p type impurity concentration, be PD layer 17, and use the composition identical to form the metal line 15b that is electrically connected PD17 and conduction region 15-1 with metal line 15a.The electric charge that the surface of buffering coating film 14 is accumulated flow into metal line 15b, accumulate in the PD layer, the charge density that the surface of buffering coating film 14 is accumulated reduces, and itself suppresses discharging, thereby can improve antistatic behaviour to the static that is subjected to external action.And metal line 15a, 15b form helical form by each layer, and the length of arrangement wire that can extend increases the electric charge that accumulates, thereby antistatic behaviour is improved.Metal line 15a has the wiring size identical with wiring with 15b, and is no problem aspect technological procedure, and the circuit of available and IC circuit particularly, adopts metal materials such as aluminium, copper with metal line 19 identical materials.
Embodiment 2
Among Fig. 2, in the periphery district that does not form element circuitry of Semiconductor substrate 11, the periphery that the conduction region 15-2 that conduction region 15-1 is electrically connected is formed on Semiconductor substrate 11 in the form of a ring.Utilize the conduction region 15-2 that forms ring-type, can guarantee the conductive path that area is bigger, capacity is bigger, the electric charge that its surface that flows into buffering coating film 14 is accumulated, thereby the charge density that accumulate on the surface that can reduce buffering coating film 14, itself suppress discharging, the static that is subjected to external action is improved antistatic behaviour.At the periphery of Semiconductor substrate 11, general configuration purpose is to suppress interlayer dielectric that bonding causes and peels off and prevent that sealing invades inner sealing ring from the outside, thereby can be with sealing ring effectively as conduction region 15-2, and the quality of circuit aspect is had no effect.Conduction region 15-2 can use circuit metal line 19 identical materials with the IC circuit, particularly, adopts metal materials such as aluminium, copper.
Again, identical with embodiment 1, also can further improve antistatic behaviour by adding metal line 15a, connect the metal line 15b of PD layer 17 etc. in the mode of combination at conduction region 15-2.
Embodiment 3
In the semiconductor device of embodiment 1 or embodiment 2, as shown in Figure 3, can make the surperficial end of buffering coating film 14 connect the conduction region 15-3 that exposes by cushioning the conduction region 15-3 that exposes that coating film 14 extends to the bight 16 of Semiconductor substrate 11, form conductive path.Buffering coating film 14 is formed into always the bight of Semiconductor substrate 11, dwindle the area of conduction region 15-3, it is more with the area of metal line that thereby configuration circuit can be guaranteed in the bight 16 of Semiconductor substrate 11, can prevent the electrostatic breakdown of metal line and interlayer dielectric again, improve the antistatic behaviour of semiconductor device, can suppress chip area again and increase.The buffering coating film 14 general this sensitization organic materials of polyimides that adopt utilize the optical graving platemaking technology, and the degree of freedom of pattern is big, can form the good pattern of dimensional accuracy.Conduction region 15-3 can use and the circuit of IC circuit metal line identical materials, particularly, adopts metal materials such as aluminium, copper.
Again, identical with embodiment 1, also can further improve antistatic behaviour by adding metal line 15a, connect the metal line 15b of PD layer 17 etc. in the mode of combination at conduction region 15-3.
Embodiment 4
Among Fig. 4, form in inside on the Semiconductor substrate 11 of the semiconductor integrated circuit constitute by semiconductor elements such as transistors, be provided with and carry out a plurality of element electrodes 12 and element wiring 12-1 that outside input/output signal is used.At whole of the Semiconductor substrate 11 that at least a portion on the element electrode 12 is opened wide, form the passivating film 13 of conduct protection dielectric film, and on the passivating film 13 in the semiconductor integrated circuit formation district, form the buffering coating film 14 that insulate.The buffering coating film 14 general this sensitization organic materials of polyimides that adopt utilize the optical graving platemaking technology to form pattern with good precision, and thickness are several microns.Identical with element electrode 12, passivating film 13 opened wide and the surperficial end of the element wiring 12-1 contact buffering coating film 14 that exposes, form the conductive path that the electric charge that the surface that makes buffering coating film 14 accumulates flows to element wiring 12-1.The periphery surface of buffering coating film 14 is because the easiest electric charge that accumulates is the high zone of charge density, and the possibility of discharging is big, so by at element wiring 12-1 conductive path being set, form the electric charge structure of circulation easily.At this moment, by the element electrode 12 that will be connected with buffering coating film 12 through element wiring 12-1 as ground connection (GND) electrode, make the PD layer ground connection of grounding electrode and Semiconductor substrate 11, electric charge from buffering coating film 14 by element wiring 12-1, flow into the PD layer as the element electrode 12 of grounding electrode, to not influence of internal circuit.
And, is connected with buffering coating film 14 by many element wiring 12-1 that make Semiconductor substrate 11, can further reduce the charge density that accumulate on the surface of cushioning coating film 14, itself suppress discharging.
In sum, be electrically connected with buffering coating film 14 by at least 1 the element electrode 12 that makes Semiconductor substrate 11 as grounding electrode, charged electric charge discharges to Semiconductor substrate by element wiring 12-1 on the buffering coating film 14, thereby can suppress the discharge circuit region is applied high pressure, prevent the electrostatic breakdown of metal line and interlayer dielectric, improve the antistatic behaviour of semiconductor device.
Embodiment 5
In the semiconductor device of embodiment 4, as shown in Figure 5, by the buffering coating film 14-1 that setting makes buffering coating film 14 contact with element electrode 12 as grounding electrode, the surperficial end of buffering coating film 14-1 can connect the unlimited position of passivating film 13 of element electrode 12, formation conductive path.Buffering coating film 14 can be formed into element electrode 12 always, and not influence the wires design of internal circuit, from and the antistatic behaviour of semiconductor device is improved, can suppress chip area again and increase.The buffering coating film 14 general this sensitization organic materials of polyimides that adopt utilize the optical graving platemaking technology, and the degree of freedom of pattern is big, can form the good pattern of dimensional accuracy.
Embodiment 6
Then, with reference to the manufacture method of the operation sectional views semiconductor device of the present invention shown in Fig. 6 A to C.
At first, among Fig. 6 A, on the P type substrate of the Semiconductor substrate 11 that forms semiconductor integrated circuit, form PD layer 17.
Secondly, identical with metal line 19 among Fig. 6 B with circuit, also form technology (sputter, etching method) and form metal line 15a and metal line 15b, and form technology (plasma CVD method) formation interlayer dielectric 18 with interlayer dielectric with wiring.
At last, among Fig. 6 C, form and to be provided with the passivating film 13 that makes the opened portion that metal line 15-1 exposes, and on passivating film 13, form the buffering coating film 14 that the metal line 15-1 that exposes in surperficial end and the described opened portion is connected.
Like this, the conduction region 15-1 that comprises metal line 15a and metal line 15b forms conductive path, and passivating film 13 is connected with metal line 15-1 with the surperficial end of buffering coating film 14.Can with the operation that forms product circuit in the interlayer dielectric formation technology (plasma CVD method) the used technological procedure identical with wiring formation technology (sputter, etching method) form above-mentioned operation, do not increase worker ordinal number or lengthening manufacturing process's time, even spread all over lower layer part formation metal line 15a from the opened portion of passivating film 13, also, have no effect owing to be and the identical technological procedure of formation product circuit.In order further to reduce the charge density on buffering coating film 14 surfaces, Semiconductor substrate 11 is formed PD layer 17 in advance on P type substrate, and connect metal line 15b, thereby can accumulate more electric charge by metal line 15b at PD layer 17 charged electric charge on the buffering coating film 14.The PD layer 17 that forms on the P type substrate makes change in concentration by control ion injection rate, thereby can make the charge capacity increase and decrease.As shown in the Examples, utilize the sealing ring that forms on the periphery that suppresses pattern, Semiconductor substrate 11 of peeling off that was in the past forming on the bight 16 of Semiconductor substrate 11, then can form conduction region 15-1, to manufacturing process much less, design also has no effect to the element circuitry of Semiconductor substrate.
Claims (16)
1, a kind of semiconductor device is characterized in that, has
Form the Semiconductor substrate of semiconductor integrated circuit and element electrode;
The protection dielectric film that on described Semiconductor substrate, forms;
The buffering coating film that on the described protection dielectric film in described semiconductor integrated circuit district, forms; And
The conduction region that is electrically connected with described buffering coating film.
2, the semiconductor device described in claim 1 is characterized in that,
Described conduction region is arranged on one or more bights of described Semiconductor substrate.
3, the semiconductor device described in claim 1 is characterized in that,
Periphery in described Semiconductor substrate is arranged to ring-type with described semiconductor region.
4, the semiconductor device described in claim 1 is characterized in that,
The inhibition pattern is peeled off at the sealing ring or the angle that form on the described Semiconductor substrate, as described conduction region.
5, the semiconductor device described in claim 2 is characterized in that,
Described buffering coating film is extended to the zone of the described conduction region of described formation, be connected with described conduction region.
6, the semiconductor device described in claim 2 is characterized in that,
Spread all over a plurality of wiring layers district and form described conduction region.
7, the semiconductor device described in claim 3 is characterized in that,
Spread all over a plurality of wiring layers district and form described conduction region.
8, the semiconductor device described in claim 2 is characterized in that,
Spread all over a plurality of wiring layers district described conduction region is arranged to helical form.
9, the semiconductor device described in claim 6 is characterized in that,
Spread all over the semiconductor silicon substrate and form described conduction region.
10, the semiconductor device described in claim 7 is characterized in that,
Spread all over the semiconductor silicon substrate and form described conduction region.
11, a kind of semiconductor device is characterized in that, has
Form the Semiconductor substrate of semiconductor integrated circuit and element electrode;
The protection dielectric film that on described Semiconductor substrate, forms; And
Be formed on the described protection dielectric film in described semiconductor integrated circuit district, and the buffering coating film that is connected with one or more grounding electrodes in the described element electrode.
12, the semiconductor device described in claim 11 is characterized in that,
Described buffering coating film is extended, and be connected to described grounding electrode.
13, a kind of manufacture method of semiconductor device is characterized in that, has
When formation makes the electrostatic withstand voltage of semiconductor device improve the conduction region of usefulness,
On the Semiconductor substrate that forms semiconductor integrated circuit and element electrode, form the 1st operation of described conduction region;
On Semiconductor substrate, form the 2nd operation be provided with the protection dielectric film that makes the opened portion that described conduction region and described element electrode expose; And
On described protection dielectric film, form the 3rd operation of the buffering coating film that is connected with the described conductive layer that exposes in the described opened portion.
14, the manufacture method of the semiconductor device described in claim 13 is characterized in that,
In described the 1st operation,, form described conduction region simultaneously with metal line with circuit from lower floor.
15, the manufacture method of the semiconductor device described in claim 14 is characterized in that,
In described the 1st operation, spread all over the dense zone of p type impurity concentration of the p type island region of the silicon portion that is arranged on described Semiconductor substrate, form described conduction region.
16, a kind of manufacture method of semiconductor device is characterized in that, has
When formation makes the electrostatic withstand voltage of semiconductor device improve the conduction region of usefulness,
On the Semiconductor substrate that forms semiconductor integrated circuit and element electrode, form the 1st operation that is provided with the protection dielectric film that makes the opened portion that described element electrode exposes; And
On described protection dielectric film, form the 2nd operation of the buffer film that is connected with one or more grounding electrodes in the described element electrode that exposes in the described opened portion.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005354196 | 2005-12-08 | ||
| JP2005354196 | 2005-12-08 | ||
| JP2006272365 | 2006-10-04 |
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| Publication Number | Publication Date |
|---|---|
| CN1979860A true CN1979860A (en) | 2007-06-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200610166739 Pending CN1979860A (en) | 2005-12-08 | 2006-12-07 | Semiconductor device and method of manufacturing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102244046A (en) * | 2010-05-11 | 2011-11-16 | 扬州杰利半导体有限公司 | Passivated protection diode chip and processing method thereof |
| CN102629756A (en) * | 2011-02-03 | 2012-08-08 | 夏普株式会社 | Diode protection circuit, lnb and antenna system |
-
2006
- 2006-12-07 CN CN 200610166739 patent/CN1979860A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102244046A (en) * | 2010-05-11 | 2011-11-16 | 扬州杰利半导体有限公司 | Passivated protection diode chip and processing method thereof |
| CN102629756A (en) * | 2011-02-03 | 2012-08-08 | 夏普株式会社 | Diode protection circuit, lnb and antenna system |
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Open date: 20070613 |