KR0125583Y1 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- KR0125583Y1 KR0125583Y1 KR2019940034151U KR19940034151U KR0125583Y1 KR 0125583 Y1 KR0125583 Y1 KR 0125583Y1 KR 2019940034151 U KR2019940034151 U KR 2019940034151U KR 19940034151 U KR19940034151 U KR 19940034151U KR 0125583 Y1 KR0125583 Y1 KR 0125583Y1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- potential
- semiconductor device
- insulating layer
- metal wiring
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
Abstract
본 고안에 의한 반도체 장치는 금속배선층의 상면에 있는 절연물질층위에 반도체 소자의 전기적인 동작시에 발생되는 내부 잡음을 억제시키고, 외부 잡음을 차폐시키도록 도전형 물질로 형성시킨 정전위층을 포함하여 이루어진다.The semiconductor device according to the present invention includes an electrostatic potential layer formed of a conductive material on the insulating material layer on the upper surface of the metal wiring layer to suppress internal noise generated during electrical operation of the semiconductor device and shield external noise. Is done.
Description
제1도는 본 고안에 의한 반도체 장치를 도시한 도면.1 is a view showing a semiconductor device according to the present invention.
본 고안은 반도체 장치에 관한 것으로, 특히 고주파수, 고전력의 반도체 장치에서 발생되기 쉬운 잡음(noise)문제, 전자파장애(EMI) 문제를 감소시키기에 적당하도록 한 반도체 장치에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for reducing a noise problem and an electromagnetic interference (EMI) problem that are likely to occur in a high frequency, high power semiconductor device.
일반적으로 반도체 장치는 반도체기판상에 각 반도체 노드(node)의 불순물 채널(chennel)을 형성시킨 다음에, 그 상면에 절연층을 형성시키고, 절연층을 사진식각하여 콘택홀(contact hall)을 형성시키고, 그 상면에는 금속배선층을 형성시킨다.In general, a semiconductor device forms an impurity channel of each semiconductor node on a semiconductor substrate, then forms an insulating layer on the upper surface thereof, and forms a contact hole by photolithography the insulating layer. On the upper surface, a metal wiring layer is formed.
즉, 종래의 반도체 장치에서 바이폴라 트렌지스터(bipolar transistor) 소자인 경우에는 반도체기판의 상면에 형성시킨 매몰층(buried layer)과, 각 전극의 불순물 이온층이 형성되는 에피택셜층(epitaxial layer)을 포함하는 소자 형성층과, 그 상면에서 콘택홀을 형성시킨 절연 물질의 절연층과, 절연층 상에서 콘택홀을 통하여 각 전극의 불순물채널과 접촉하게 되는 금속배선층을 포함하여 이루어진다.(도면에 도시안함)That is, in the conventional semiconductor device, a bipolar transistor device includes a buried layer formed on an upper surface of a semiconductor substrate and an epitaxial layer on which impurity ion layers of each electrode are formed. An element forming layer, an insulating layer of an insulating material having a contact hole formed on the upper surface thereof, and a metal wiring layer which is brought into contact with an impurity channel of each electrode through the contact hole on the insulating layer (not shown).
그리고, 이층(double) 금속구조의 바이폴라 트렌지스터 소자에서는 소자형성층과, 그 상면에서 콘택홀을 형성시킨 절연 물질의 제 1절연층과, 제 1절연층상에서 콘택홀을 통하여 각 전극의 불순물채널과 접촉하게 되는 제 1금속배선층과, 제 1금속배선층상에는 전극의 불순물채널과 접촉하게 되는 금속배선층을 노출시키는 비아(via) 콘택홀을 형성시킨 절연 물질의 제 2절연층을 형성시키고, 그 상면에 비아콘택홀을 통하여 금속배선층과 접촉하게 되는 제 2금속배선층을 추가적으로 형성시켜서 각 반도체 소자간의 금속배선에 의한 연결상태를 보완시켰다.(도면에 도시안함)In the bipolar transistor device having a double metal structure, the element formation layer, a first insulating layer of an insulating material having a contact hole formed on the upper surface thereof, and an impurity channel of each electrode are contacted through the contact hole on the first insulating layer. On the first metal wiring layer and the first metal wiring layer, a second insulating layer of an insulating material having a via contact hole for exposing the metal wiring layer in contact with the impurity channel of the electrode is formed. A second metal wiring layer, which is in contact with the metal wiring layer through the contact hole, was additionally formed to compensate for the connection state caused by the metal wiring between the semiconductor elements (not shown).
그러나, 종래의 반도체 장치에서는 소자의 전기적인 동작시에 발생되는 내부의 잡음을 억제시키든지, 외부의 잡음을 차폐시키는 기능이 없어서, 외부잡음에 의한 동작상태가 교란되고 내부잡음이 쉽게 외부로 전달되어서 외부의 주변회로에 영향을 끼치게 되는 문제가 발생되었고, 이는 반도체 소자와 주변회로에서의 잡음문제와 전자파 장애등의 원인이 되었다.However, in the conventional semiconductor device, there is no function of suppressing the internal noise generated during the electrical operation of the device or shielding the external noise, so that the operation state caused by the external noise is disturbed and the internal noise is easily transmitted to the outside. Therefore, a problem occurs that affects external peripheral circuits, which causes noise problems and electromagnetic interference in semiconductor devices and peripheral circuits.
본 고안은 이러한 문제를 해결하기 위하여 인출된 것으로, 반도체 장치에 도전성 정전위층을 형성시켜서 동작적으로 안정된 반도체 회로의 구성을 용이하게 하는 것을 그 목적으로 한다.The present invention has been drawn to solve such a problem, and an object thereof is to facilitate the construction of a semiconductor circuit that is operatively stable by forming a conductive electrostatic potential layer in a semiconductor device.
본 고안의 반도체 장치는 소자가 형성된 반도체기판과, 반도체기판 상에 일정영역을 노출시키는 제 1비아콘택홀을 갖도록 형성된 제 1절연층과, 제 1절연층 상에 제 1비아콘택홀을 덮어 반도체기판의 일정영역과 전기적으로 연결되도록 형성된 제 1금속배선층과, 제 1금속배선층 상에 제 2비아콘택홀을 갖도록 형성된 제 2절연층과, 제 2절연층 상에 제 2비아콘택홀을 덮어 제 1금속배선층과 전기적으로 연결되도록 형성된 제 1정전위층과, 제 1정전위층 상에 제 3비아콘택홀을 갖도록 형성된 제 3절연층과, 제 3절연층 상에 제 3비아콘택홀을 덮어 제 1정전위층과 전기적으로 연결되도록 형성된 제 2금속배선층과, 제 2금속배선층 상에 제 4비아콘택홀을 갖도록 형성된 제 4절연층과, 제 4절연층 상에 제 4비아콘택홀을 덮어 제 2금속배선층과 전기적으로 연결되도록 형성된 제 2정전위층을 구비한 것이 특징이다.The semiconductor device of the present invention includes a semiconductor substrate on which a device is formed, a first insulating layer formed to have a first via contact hole exposing a predetermined region on the semiconductor substrate, and a semiconductor layer covering the first via contact hole on the first insulating layer. A first metal wiring layer formed to be electrically connected to a predetermined region of the substrate, a second insulating layer formed to have a second via contact hole on the first metal wiring layer, and a second via contact hole covered on the second insulating layer; A first potential layer formed to be electrically connected to the first metal wiring layer, a third insulating layer formed to have a third via contact hole on the first potential layer, and a third via contact hole covered on the third insulating layer; A second metal wiring layer formed to be electrically connected to the potential potential layer, a fourth insulating layer formed to have a fourth via contact hole on the second metal wiring layer, and a second via covering the fourth via contact hole on the fourth insulating layer Electrical connection with wiring layer It is characterized by having a second upper level electrostatic formed to.
이하, 첨부된 도면을 참조하여 본 고안을 설명하겠다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
제1도는 본 고안에 의한 반도체 장치를 도시한 도면으로, 제1도의 (a)는 단층 금속구조의 본 고안에 의한 반도체 장치를 도시한 도면이고, 제1도의 (b)는 이층(double) 금속구조의 본 고안에 의한 반도체 장치를 도시한 도면이다.1 is a view showing a semiconductor device according to the present invention, Figure 1 (a) is a view showing a semiconductor device according to the present invention of a single-layer metal structure, Figure 1 (b) is a double metal (double) metal. It is a figure which shows the semiconductor device by this invention of a structure.
본 고안에 의한 단층 금속구조의 반도체 장치는 제1도의 (a)와 같이, 소자가 형성된 반도체기판과, 반도체기판 상에 일정영역을 노출시키는 제 1비아콘택홀을 갖도록 형성된 제 1절연층과, 제 1절연층 상에 제 1비아콘택홀을 덮어 반도체기판의 일정영역과 전기적으로 연결되도록 형성된 금속배선층과, 금속배선층 상에 제 2비아콘택홀을 갖도록 형성된 제 2절연층과, 제 2절연층 상에 제 2비아콘택홀을 덮어 제 1금속배선층과 전기적으로 연결되도록 형성된 정전위층과, 정전위층 상에 형성된 보호막층으로 구성된다. 도면에서는 제 1절연층의 제 1비아콘택홀과, 제 2절연층의 제 2비아콘택홀이 도시되지 않았다.A semiconductor device having a single layer metal structure according to the present invention includes a first insulating layer formed to have a semiconductor substrate on which elements are formed, a first via contact hole exposing a predetermined region on the semiconductor substrate, as shown in FIG. A metal wiring layer formed to cover the first via contact hole on the first insulating layer to be electrically connected to a predetermined region of the semiconductor substrate, a second insulating layer formed to have the second via contact hole on the metal wiring layer, and a second insulating layer An electrostatic potential layer formed on the second via contact hole and electrically connected to the first metal wiring layer, and a protective layer formed on the electrostatic potential layer. In the drawing, the first via contact hole of the first insulating layer and the second via contact hole of the second insulating layer are not shown.
이 정전위층은 도전형 물질인 금속이나 불순물이 도핑(doping)된 폴리실리콘(poly silicon)으로 형성되며, 제 2절연층의 제 2비아콘택홀을 통하여 금속 배선층의 접지측 도선과 연결되거나, 금속배선층의 Vcc 전원단자측에 연결되며, 또한 별도로 정전위층을 형성시키지 않고, 표면보호막층을 도전형물질로 형성하여 정전위층으로 사용하기도 한다.The electrostatic potential layer is formed of a conductive material or polysilicon doped with impurities, and is connected to the ground-side lead of the metal wiring layer through the second via contact hole of the second insulating layer, or It is connected to the Vcc power supply terminal side of the wiring layer, and a surface protection film layer is formed of a conductive type material and is used as a potential layer without forming a potential layer.
그리고, 이층(double) 금속구조의 본 고안에 의한 반도체 소자의 단층구조는 제1도의 (b)와 같이, 소자가 형성된 반도체기판과, 반도체기판 상에 일정영역을 노출시키는 제 1비아콘택홀을 갖도록 형성된 제 1절연층과, 제 1절연층 상에 제 1비아콘택홀을 덮어 반도체기판의 일정영역과 전기적으로 연결되도록 형성된 제 1금속배선층과, 제 1금속배선층 상에 제 2비아콘택홀을 갖도록 형성된 제 2절연층과, 제 2절연층 상에 제 2비아콘택홀을 덮어 제 1금속배선층과 전기적으로 연결되도록 형성된 제 1정전위층과, 제 1정전위층 상에 제 3비아콘택홀을 갖도록 형성된 제 3절연층과, 제 3절연층 상에 제 3비아콘택홀을 덮어 제 1정전위층과 전기적으로 연결되도록 형성된 제 2금속배선층과, 제 2금속배선층 상에 제 4비아콘택홀을 갖도록 형성된 제 4절연층과, 제 4잘연층 상에 제 4비아콘택홀을 덮어 제 2금속배선층과 전기적으로 연결되도록 형성된 제 2정전위층과, 제 2정전위층 상에 형성된 보호막층으로 구성된다. 도면에서는 제 1, 제 2, 제 3비아콘택홀이 미도시되었다.The single-layer structure of the semiconductor device according to the present invention of the double metal structure includes a semiconductor substrate on which the device is formed and a first via contact hole exposing a predetermined region on the semiconductor substrate as shown in FIG. A first insulating layer formed to have the first insulating layer, the first metal contact layer formed to cover the first via contact hole on the first insulating layer, and to be electrically connected to a predetermined region of the semiconductor substrate, and the second via contact hole formed on the first metal wiring layer. A second insulating layer formed to have a second via contact hole on the second insulating layer, the first potential potential layer formed to be electrically connected to the first metal wiring layer, and a third via contact hole formed on the first potential potential layer. The third insulating layer formed to cover the third via contact hole on the third insulating layer, the second metal wiring layer formed to be electrically connected to the first potential layer, and the fourth via contact hole formed on the second metal wiring layer. Fourth insulating layer and fourth well A second upper level electrostatic formed to cover the fourth contact hole via the second metal wiring layer and electrically connected to the layer, the layer is composed of a protective film formed on the second upper power failure. In the drawing, the first, second and third via contact holes are not shown.
제 1, 제 2정전위층은 도전형 물질인 금속이나 불순물이 도핑된 폴리실리콘으로 형성된다. 제 1정전위층은 제 2절연층의 제 2비아콘택홀을 통하여 제 1 금속배선층의 접지측 도선과 연결되거나, 금속배선층의 Vcc 전원단자측에 연결되고, 제 2정전위층은 제 4절연층의 제 4비아콘택홀을 통하여 제 2금속배선층의 접지측 도선과 연결되거나, 금속배선층의 Vcc 전원단자측에 연결된다.The first and second potential potential layers are formed of a metal which is a conductive material or polysilicon doped with impurities. The first potential layer is connected to the ground-side lead of the first metal wiring layer through the second via contact hole of the second insulation layer, or is connected to the Vcc power terminal side of the metal wiring layer, and the second potential layer is connected to the fourth insulating layer. The fourth via contact hole is connected to the ground-side lead of the second metal wiring layer or to the Vcc power terminal side of the metal wiring layer.
그리고, 제 2정전위층을 형성시키지 않고, 보호막층을 도전형물질로 형성하여 제 2정전위층으로 사용하기도 한다.In addition, the protective film layer may be formed of a conductive material without using the second potential layer and may be used as the second potential layer.
본 고안에 의한 반도체 장치에서 금속배선층 상의 도전형 물질층에 일정한 전위를 공급하여 형성시키는 정전위층은 반도체 소자의 전기적인 동작시에 발생되는 내부의 잡음을 억제시키고, 외부의 잡음을 차폐시키는 역할을 하여, 반도체 소자와 주변회로에서의 잡음문제와 전자파 장애 등의 문제를 제거할 수 있다.In the semiconductor device according to the present invention, the electrostatic potential layer formed by supplying a constant potential to the conductive material layer on the metallization layer suppresses internal noise generated during electrical operation of the semiconductor device and shields external noise. Thus, problems such as noise problems and electromagnetic interference in semiconductor devices and peripheral circuits can be eliminated.
또한, 본 고안에 의한 반도체 장치에서 정전위층은 반도체 장치의 회로 구현시에 금속배선층의 접지측 도선, Vcc 전원단자 등의 배선에 이용하여 회로 배선을 용이하게 한다.In addition, in the semiconductor device according to the present invention, the electrostatic potential layer may be used for wiring of the ground-side conductor of the metal wiring layer, the Vcc power terminal, and the like in the circuit implementation of the semiconductor device, thereby facilitating circuit wiring.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940034151U KR0125583Y1 (en) | 1994-12-15 | 1994-12-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940034151U KR0125583Y1 (en) | 1994-12-15 | 1994-12-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960025532U KR960025532U (en) | 1996-07-22 |
| KR0125583Y1 true KR0125583Y1 (en) | 1998-10-01 |
Family
ID=19401438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019940034151U KR0125583Y1 (en) | 1994-12-15 | 1994-12-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0125583Y1 (en) |
-
1994
- 1994-12-15 KR KR2019940034151U patent/KR0125583Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960025532U (en) | 1996-07-22 |
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