JP3366403B2 - Manufacturing method of semiconductor nonvolatile memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable semiconductor non-volatile memory device and a method of manufacturing the same, and more particularly, to a semiconductor non-volatile memory device having an electrostatic resistance and storage data. It is related to improvement of the holding ability. 2. Description of the Related Art Conventionally, as an electrically rewritable semiconductor nonvolatile memory element, an MNOS (Metal-N
itride-Oxide-Semiconductor
r) type semiconductor nonvolatile memory element, for example,
MONOS described in JP-B-103966
(Metal-Oxide-Nitride-Oxid
2. Description of the Related Art An e-Semiconductor type semiconductor nonvolatile memory element is known. This MONOS type semiconductor nonvolatile memory element has a third layer formed on a silicon nitride film which is a second layer memory gate insulating film of the MNOS type semiconductor nonvolatile memory element.
A silicon oxide film as a memory gate insulating film. A conventional semiconductor non-volatile memory device includes a semiconductor non-volatile memory element and a MOS (Meta) for address selection.
It has a memory array area in which memory cells composed of l-oxide-semiconductor elements are arranged in a matrix, and a peripheral control circuit area for controlling the memory array area. [0005] A semiconductor nonvolatile memory device holds stored data by holding carriers (electrons or holes) in a physically stable state inside a semiconductor nonvolatile memory element. The semiconductor non-volatile memory element has a structure in which a carrier holding region (hereinafter, referred to as a trap region) is surrounded by an insulating film having a high energy barrier height, so that the carrier can be held in a physically stable state. Like that. For example, a memory gate insulating film of a MONOS type nonvolatile semiconductor memory device has a structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated on a semiconductor substrate. The silicon nitride film serving as a trap region is surrounded by a silicon oxide film serving as an insulating film having a high energy barrier height, so that carriers can be stably held. However, a semiconductor nonvolatile memory element cannot hold carriers in a completely physically stable state. For example, carriers held in the trap region by external energy such as heat energy are:
Tunnel through the insulating film with high energy barrier height,
It moves to the semiconductor substrate or the memory gate electrode. When this phenomenon occurs, the storage capability of the semiconductor nonvolatile storage element is reduced, and the storage capability of the semiconductor nonvolatile storage device is reduced. Note that the storage retention is the ability to retain carriers in the trap region of the semiconductor nonvolatile storage element. [0010] It is known that a semiconductor nonvolatile memory device is destroyed when an electrostatic breakdown phenomenon occurs, which causes a defect in manufacturing process and lowers reliability. The electrostatic breakdown phenomenon includes a human body charging model in which static electricity accumulated in a human body is discharged to a terminal of a semiconductor nonvolatile memory device and destroyed, and a semiconductor nonvolatile memory device itself is electrostatically charged and the semiconductor nonvolatile memory device is damaged. There is an electrostatic discharge breakdown phenomenon caused by a device charging model that occurs when a terminal comes into contact with a ground metal or the like. [0012] These electrostatic discharge breakdown phenomena occur due to discharge through external connection terminals. Therefore, as means for preventing destruction of the semiconductor nonvolatile memory device, a diode element serving as a voltage clamp element and a resistance element serving as a current limiting element are provided between the external connection terminal and the internal element of the semiconductor nonvolatile memory device. It has been practiced to provide a static electricity protection circuit. Conventionally, the electrostatic resistance has been improved by this means. However, in addition to the electrostatic discharge phenomena caused by the human body charging model and the device charging model, the electrostatic breakdown phenomena include, for example, guidelines for the electrostatic breakdown phenomena of semiconductor devices issued by the Japan Electronic Components Reliability Center and its evaluation method. (R-62-ES-02)
, There is a phenomenon called an electric field induction model. The electric field induction model will be described with reference to FIG. FIG. 4 is a sectional view showing an electric field induction model. This shows a state in which a semiconductor nonvolatile memory element including a memory gate insulating film 17 and a memory gate electrode 18 formed on the surface of a semiconductor substrate 11 is inserted into a high electric field generated by static electricity. In FIG. 4, an electric field generated by static electricity is generated between the external electric field electrode 27 and the ground electrode 28, and is shown by arrows. Due to the resistance of the semiconductor substrate 11 and the capacitance of the memory gate insulating film 17, a parasitic diode is generated between the memory gate electrode 18 and the semiconductor substrate 11, and until the parasitic diode responds, a parasitic diode is generated. Is applied with an overvoltage. Due to the application of the overvoltage, the memory gate insulating film 17 is broken. Conventionally, since the thickness of the memory gate insulating film 17 is large and the electrostatic breakdown phenomenon by the electric field induction model hardly occurs, no measures are taken to prevent the electrostatic breakdown phenomenon by the electric field induction model. In recent years, with the miniaturization of semiconductor non-volatile memory elements due to the increase in capacity of semiconductor non-volatile memory devices, the voltage for writing storage data to semiconductor non-volatile memory elements has been reduced. ing. This reduction in the write voltage can be realized by making the memory gate insulating film thin. For example, the MONOS type semiconductor nonvolatile memory element realizes a write voltage of 9 V or less by reducing the thickness of the memory gate insulating film to about 10 nm. When the memory gate insulating film of the semiconductor nonvolatile memory element becomes thinner, an electrostatic breakdown phenomenon based on an electric field induction model which has not conventionally occurred tends to occur. For this reason,
The static electricity resistance of the semiconductor nonvolatile memory device is reduced, and the semiconductor nonvolatile memory device is easily broken. The storage data of the semiconductor nonvolatile memory device is held by holding carriers in the trap region of the semiconductor nonvolatile memory element. For this reason, when the electrostatic breakdown phenomenon by the electric field induction model occurs, the carriers held in the semiconductor nonvolatile storage element move from the trap region even when a low electric field is applied so that the semiconductor nonvolatile storage device is not broken, and the semiconductor nonvolatile storage element Memory retention decreases. That is, in the semiconductor nonvolatile memory device, not only destruction but also deterioration of storage data retention ability occurs due to an electrostatic breakdown phenomenon based on an electric field induction model. From the above, it is difficult for a conventional semiconductor nonvolatile memory device to have a high electrostatic resistance and to have a sufficient storage data holding ability. An object of the present invention is to eliminate such a problem and to provide a structure of a semiconductor non-volatile memory device having high electrostatic resistance and excellent storage data retention ability, and a method of manufacturing the same. In order to achieve the above object, the present invention employs the following structure of a semiconductor nonvolatile memory device and a method of manufacturing the same. According to the semiconductor nonvolatile memory device of the present invention, a memory gate insulating film is formed on a surface of a semiconductor substrate of one conductivity type;
A metal blocking layer is provided which covers at least an upper portion of a semiconductor nonvolatile memory element including a memory gate electrode provided on the memory gate insulating film and is separated from the semiconductor nonvolatile memory element and a metal wiring. According to the semiconductor nonvolatile memory device of the present invention, a memory gate insulating film is formed on a surface of a semiconductor substrate of one conductivity type.
At least an upper portion of a semiconductor non-volatile memory element including a memory gate electrode provided on the memory gate insulating film is covered, separated from the semiconductor non-volatile memory element and a metal wiring, and is provided with a metal cut-off provided in connection with a ground terminal. With layers. According to the semiconductor nonvolatile memory device of the present invention, a memory gate insulating film is formed on a surface of a semiconductor substrate of one conductivity type;
A metal that covers at least an upper portion of a semiconductor nonvolatile memory element including a memory gate electrode provided on the memory gate insulating film, is separated from the semiconductor nonvolatile memory element and a metal wiring, and is connected to a reference potential terminal. Has a barrier layer. According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, there are provided a step of forming a metal wiring and forming an interlayer insulating film, a step of forming a blocking metal on the interlayer insulating film, and a step of forming a metal by photoetching. The method includes a step of forming a blocking layer and a step of forming a protective insulating film. According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, a step of forming a metal wiring and forming a protective insulating film, forming a blocking metal on the protective insulating film, and forming a metal blocking layer by photoetching And a step of performing. According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the metal wiring in the memory array area is the first metal wiring, and the metal wiring in the peripheral control circuit area is the first metal wiring and the second metal wiring. Forming a first metal wiring, forming a wiring interlayer insulating film, forming a blocking metal on the wiring interlayer insulating film, and forming the metal by photoetching. Barrier layer and second
And a step of forming a protective insulating film at the same time. According to the present invention, there is provided a semiconductor nonvolatile memory device comprising:
A metal blocking layer is provided to cover at least the upper part of the semiconductor nonvolatile memory element including the memory gate insulating film and the memory gate electrode. As a result, an electric field generated by static electricity can be prevented from reaching the semiconductor nonvolatile memory element, and thus the semiconductor nonvolatile memory device can be improved in static electricity resistance and storage data retention ability. The structure and manufacturing method of a semiconductor nonvolatile memory device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an example of the structure of a semiconductor nonvolatile memory device according to an embodiment of the present invention. First, the structure of the semiconductor nonvolatile memory device will be described with reference to FIG. As shown in FIG. 1, the semiconductor non-volatile memory device according to the present invention includes a semiconductor non-volatile memory element provided on a surface of a semiconductor substrate 11 and comprising a memory gate insulating film 17 and a memory gate electrode 18. This is a structure in which a metal barrier layer 12 is provided to cover. The metal barrier layer 12 is formed of the metal interlayer insulating film 1
4, the interlayer insulating film 1 is separated from the metal wiring 13.
5 and the metal interlayer insulating film 14 are separated from the memory gate electrode 18 of the semiconductor nonvolatile memory element. A protective insulating film 16 is provided on the metal blocking layer 12 to prevent moisture and the like from entering the semiconductor nonvolatile memory device from the outside. The semiconductor nonvolatile memory element has a memory gate insulating film 17 having a three-layer structure in which a silicon oxide film, a silicon nitride film and a silicon oxide film are sequentially stacked on a semiconductor substrate 11 sandwiched between source / drain regions 19. And a memory gate electrode 18 provided on the memory gate insulating film 17 to form a MONOS type semiconductor nonvolatile memory element. FIGS. 2 and 3 are plan views showing an example of the structure of the semiconductor nonvolatile memory device according to the embodiment of the present invention. As shown in FIG. 2, a semiconductor nonvolatile memory device according to an embodiment of the present invention includes a memory array region 20 having a semiconductor nonvolatile memory element, a peripheral control circuit region 21 having a peripheral control circuit element, and an external device. A ground terminal 22 connected to the ground potential, an external connection terminal 23, and a metal blocking layer 12 that covers the semiconductor nonvolatile memory element of the memory array region 20 and is connected to the ground terminal 22. Note that the memory array region 20 and the peripheral control circuit region 21 are connected to the external connection terminals 23 by metal wiring (not shown). As shown in FIG. 3, the semiconductor nonvolatile memory device of the present invention comprises a memory array region 20 having semiconductor nonvolatile memory elements, a peripheral control circuit region 21 having peripheral control circuit elements, and an external connection terminal. 23, a reference potential terminal 24 connected to an external power supply potential and having the same potential as the semiconductor substrate, and a metal blocking layer covering the semiconductor nonvolatile memory element of the memory array region 20 and electrically connected to the reference potential terminal 24 12 is provided. The structure shown in FIG. 3 is effective in a semiconductor nonvolatile memory device having no ground terminal built in a portable device or the like. 2 and 3, the metal cutoff layer 12 has a structure covering the semiconductor nonvolatile memory element in the memory array area 20, but the metal cutoff layer 12 connects the memory array area 20 and the peripheral control circuit area 21. You may make it the structure which covers all. Even in a structure in which the metal cut-off layer 12 is not electrically connected to the ground terminal 22 or the reference potential terminal 24, for the reason described below, it has a higher static immunity and storage data holding capacity than the conventional semiconductor nonvolatile memory device. And improve. Next, the reason why the semiconductor nonvolatile memory device of the present invention has improved static electricity resistance and storage data retention ability as compared with the related art will be described. In the conventional semiconductor non-volatile memory device, the static electricity resistance and the storage data retention ability are reduced due to the electrostatic breakdown phenomenon of the electric field induction model. In the semiconductor nonvolatile memory device according to the present invention, by providing the metal blocking layer 12 on the semiconductor nonvolatile memory element, a high electric field generated by static electricity is prevented from reaching the semiconductor nonvolatile memory element. . When the metal cut-off layer 12 is connected to the ground terminal 22, a high electric field from above the semiconductor non-volatile memory element is cut off by the metal cut-off layer 12 so that the high electric field does not reach the semiconductor non-volatile memory element. can do. When the metal barrier layer 12 is connected to the reference potential terminal 24, the metal barrier layer 12 has a reference potential, that is, the same potential as the semiconductor substrate, and the semiconductor nonvolatile memory element is shielded by the metal barrier layer 12 and the semiconductor substrate. . Therefore, the high electric field applied to the semiconductor nonvolatile memory element can be reduced. When the metal blocking layer 12 is not connected to the ground terminal 22 or the reference potential terminal 24, the surface area of the metal blocking layer 12 is increased. Thus, the high electric field applied to the semiconductor nonvolatile memory element is dispersed, and the high electric field applied to the semiconductor nonvolatile memory element can be reduced. Next, a method of manufacturing the semiconductor nonvolatile memory device according to the present invention will be described with reference to FIGS. 5 to 10 are sectional views showing a method of manufacturing the semiconductor nonvolatile memory device according to the embodiment of the present invention in the order of steps. First, as shown in FIG.
A semiconductor nonvolatile memory element on the surface of the substrate. Note that the semiconductor substrate 11 is a p-type single crystal silicon substrate. A semiconductor nonvolatile memory element is formed by sequentially laminating a silicon oxide film, a silicon nitride film and a silicon oxide film to form a memory gate insulating film 17, and a memory gate electrode 18 made of polysilicon on the memory gate insulating film 17. Is formed. Next, as shown in FIG.
Arsenic is implanted into the semiconductor substrate 11 as an n-type impurity into the surface region of the semiconductor substrate 11 by ion implantation.
9 is formed. Thereafter, CVD (Ch) using monosilane, phosphine, and oxygen as a reaction gas at a temperature of 400 ° C.
A silicon oxide film containing phosphorus having a thickness of 500 nm and serving as the interlayer insulating film 15 is formed by an electronic-vapor-deposition method. Thereafter, a predetermined portion of the interlayer insulating film 15 is removed by photoetching to form a contact hole. Thereafter, a wiring metal of an alloy of aluminum and silicon having a thickness of 1 μm is formed by a magnetron sputtering method, and then the wiring metal is etched into a predetermined pattern by photoetching to form a metal wiring 13. Next, as shown in FIG. 7, a metal interlayer insulating film 14 made of a silicon oxide film having a thickness of 500 nm is formed at a temperature of 350 ° C. by a plasma CVD method using monosilane and nitrous oxide as a reaction gas. . In the case of a structure in which the metal cut-off layer is connected to the ground terminal or the reference potential terminal, a photo-etching process is performed after the formation of the silicon oxide film serving as the metal interlayer insulating film 14, so that the potential on the ground terminal or the reference potential terminal is increased. What is necessary is just to remove the silicon oxide film on the terminal. Next, as shown in FIG. 8, the metal interlayer insulating film 14 is formed with a thickness of 700 nm by magnetron sputtering.
A barrier metal 25 made of aluminum is formed. The blocking metal 25 uses an alloy of aluminum and silicon, or an alloy of aluminum, silicon, and copper. Next, as shown in FIG. 9, a photo-etching process is performed to etch the blocking metal 25 into a predetermined pattern to form the metal blocking layer 12. Next, as shown in FIG.
Then, a protective insulating film 16 made of a silicon nitride film having a thickness of 500 nm is formed by a plasma CVD method using monosilane and ammonia as a reaction gas. The above embodiment is an embodiment in which the metal blocking layer 12 is formed on the metal interlayer insulating film 14 in the method of manufacturing a semiconductor nonvolatile memory device according to the present invention. Next, a method for forming the metal blocking layer 12 on the protective insulating film 16 according to an embodiment of the method for manufacturing a semiconductor nonvolatile memory device of the present invention will be described with reference to FIGS. FIGS. 11 to 13 are sectional views showing a method of manufacturing a semiconductor nonvolatile memory device according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 11, the metal wiring 13 is formed in the same manner as in the embodiment described with reference to FIGS.
To form Thereafter, a silicon nitride film having a thickness of 500 nm is formed by a plasma CVD method using monosilane and ammonia as a reaction gas at a temperature of 300 ° C., and the silicon nitride film is etched into a predetermined pattern by performing a photo-etching process. Then, a protective insulating film 16 is formed. Next, as shown in FIG.
Aluminum having a thickness of 700 nm serving as a blocking metal 25 is formed on the metal film 6 by magnetron sputtering. The blocking metal 25 uses an alloy of aluminum and silicon or an alloy of aluminum, silicon, and copper. Next, as shown in FIG. 13, by performing a photo-etching process, the barrier metal 25 is etched into a predetermined pattern to form the metal barrier layer 12. The manufacturing method for forming the metal barrier layer 12 on the protective insulating film 16 is as follows.
As compared with the manufacturing method formed thereon,
Since it is not necessary to form, the production process can be simplified, so that the yield in the production process can be increased. In the manufacturing method in which the metal barrier layer 12 is formed on the protective insulating film 16, the metal barrier layer 12 is not corroded by the invasion of moisture or the like since there is no protective insulating film 16 on the metal barrier layer 12. There is a slight possibility to do so. But,
This problem is caused by increasing the surface area of the metal barrier layer 12 or
By making the metal barrier layer 12 thicker, it can be completely prevented. Next, in the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, the metal wiring in the memory array area is the first metal wiring, and the metal wiring in the peripheral control circuit area is the first metal wiring and the second metal wiring. A method for manufacturing a semiconductor nonvolatile memory device having a structure having metal wiring will be described with reference to FIGS. With the structure of the metal wiring, the peripheral control circuit area is significantly larger than the memory array area of the semiconductor nonvolatile memory device. For example, in a semiconductor nonvolatile memory device incorporating another semiconductor device, the peripheral control circuit area can be reduced. This is effective in reducing the size of the semiconductor nonvolatile memory device. FIGS. 14 to 18 are sectional views showing a method of manufacturing a semiconductor nonvolatile memory device according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 14, by the same method as the embodiment described with reference to FIGS. 5 and 6, up to the first metal wiring 26 corresponding to the metal wiring 13 shown in FIG. . FIG. 14 shows a memory array area 20 including a semiconductor nonvolatile memory element and a peripheral control circuit area 21. Next, as shown in FIG.
Then, a wiring interlayer insulating film 29 made of a silicon oxide film having a thickness of 500 nm is formed by a plasma CVD method using monosilane and nitrous oxide as a reaction gas. Next, a predetermined portion of the wiring interlayer insulating film 29 is removed by photoetching to form a through hole. Thereafter, as shown in FIG. 16, the wiring interlayer insulating film 29 is formed by magnetron sputtering.
A barrier metal 25 made of aluminum having a thickness of 700 nm is formed. The blocking metal 25 uses an alloy of aluminum and silicon or an alloy of aluminum, silicon, and copper. Next, as shown in FIG. 17, by performing a photo-etching process, the blocking metal 25 is etched into a predetermined pattern, and the metal blocking layer 12 and the peripheral control circuit region 21 are etched in the memory array region 20 and the second region. Metal wiring 30
Are simultaneously formed. Next, as shown in FIG.
Then, a protective insulating film 16 made of a silicon nitride film having a thickness of 500 nm is formed by a plasma CVD method using monosilane and ammonia as a reaction gas. According to the above embodiment, according to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the metal blocking layer 12 and the second metal wiring 30 are formed simultaneously. Therefore, without adding a new step of providing the metal blocking layer 12, the metal wiring in the memory array region 20 is the first metal wiring 26, and the metal wiring in the peripheral control circuit region 21 is the first metal wiring 26. A semiconductor nonvolatile memory device having the second metal wiring 30 can be manufactured. Therefore, the manufacturing process of the semiconductor nonvolatile memory device can be simplified, and the yield in the manufacturing process can be increased. As is clear from the above description, the semiconductor nonvolatile memory device according to the present invention can improve the static electricity resistance and the storage data holding ability as compared with the conventional nonvolatile memory device. Further, according to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, the manufacturing process is simplified, so that the yield in the manufacturing process can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a configuration of a semiconductor nonvolatile memory device according to an embodiment of the present invention. FIG. 2 is a plan view showing a configuration of a semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 3 is a plan view showing a configuration of a semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating an electrostatic breakdown phenomenon by a conventional electric field induction model. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a sectional view showing the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory device according to an embodiment of the present invention. FIG. 8 is a cross-sectional view illustrating a method for manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 10 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 11 is a sectional view showing the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 12 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 13 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 14 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 15 is a sectional view showing the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 16 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 17 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. FIG. 18 is a sectional view illustrating the method of manufacturing the semiconductor nonvolatile memory device according to one embodiment of the present invention. [Description of Signs] 11 Semiconductor substrate 12 Metal barrier layer 13 Metal wiring 17 Memory gate insulating film 18 Memory gate electrode

Claims (1)

(57) [Claim 1] The memory array region is formed by a first metal wiring and
And this area is separated by a wiring interlayer insulating film.
And a peripheral control circuit region including a first metal wiring and a second metal wiring separated from the first metal wiring by a wiring interlayer insulating film.
Forming a first metal wiring in a memory array region and a peripheral control circuit region, and forming a wiring interlayer insulating film on the first metal wiring in the memory array region and the peripheral control circuit region . , formation of the wiring interlayer insulating coated with exclusion metal on the membrane, which second metal wiring to the formation of the metal blocking layer to the memory array region and the peripheral control circuit region by photoetching
Process and method of manufacturing a semiconductor nonvolatile memory device characterized by comprising a step of forming a protective insulating film thereon simultaneously performed.