JPH0335552A - High breakdown voltage semiconductor device - Google Patents

Abstract

PURPOSE:To prevent formation of a parasitic channel by widening a conductive material such as polysilicon and one-layer aluminum on an element so as to cover areas where parasitic channels may be formed. CONSTITUTION:When a high positive voltage is applied, a chip surface is positively charged, a lower side of a field oxide film 11 inside a P-well 2 is inverted to N-type and a parasitic channel is formed. However, this portion is covered with aluminum and polysilicon wirings 12, 13 of GND potential or VDD potential; then, it is possible to prevent an electric field from a charge of the chip surface and to prevent formation of a parasitic channel. it is possible to improve reliability without increasing a two-layer aluminum process of a diffusion process by preventing formation of a parasitic channel by a conductor such as polysilicon and one-layer aluminum, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a high voltage semiconductor device, and particularly to a structure that prevents the formation of parasitic channels.

Conventionally, this type of semiconductor device has an MO as shown in FIG.
S) After forming the transistor, cover the surface with an insulating film 14,
Furthermore, a two-layer aluminum wiring 15 is formed on the entire surface,
By connecting it to a GND potential or the like, the potential of the chip surface is fixed, and an electric field from charges generated on the chip surface is prevented, thereby preventing the formation of a parasitic channel.

The conventional semiconductor device described above uses solid aluminum wiring in order to prevent the generation of parasitic channels formed by charges generated by applying high voltage. This parasitic channel prevention aluminum wiring 15 is unnecessary for forming a MOS transistor, and causes problems of increased man-hours and costs for the diffusion process.

゛The semiconductor device of the present invention is characterized in that the formation of a parasitic channel is prevented by increasing the width of a conductive material on the element, such as polysilicon or single-layer aluminum, to cover the portion where the parasitic channel is formed. It is something to do.

According to the above configuration, by covering the part where the parasitic channel is formed with an aluminum electrode or the like at GND potential or VDD potential, it is possible to prevent the electric field due to high voltage and prevent the generation of leakage current due to the formation of the parasitic channel. . Further, in cases where it is not possible to cover the entire area because aluminum wiring runs through it, the present invention will be described below with reference to the drawings.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. In the figure, 1 is an N-type substrate, 2 is a P-well, 3.4°5 and 8
, 7.8 are the source, drain, and gate of NMO8 and PMO8, respectively. In addition, 9 and 10 are respectively P well 2. This is a diffusion layer that takes the potential of the N-type substrate 1. 12.13
are an aluminum wiring and a polysilicon wiring, respectively, which cover the channel forming portion according to the present invention.

This example is an example of a high-voltage semiconductor device that applies 10 voltages, and by applying 10 high voltages, the chip surface is charged to 10, and P
The bottom of the field oxide film 11 inside the well 2 is inverted to N type and a parasitic channel is formed.
．． By covering with 13, it is possible to prevent the electric field from the charge on the chip surface and prevent the formation of a parasitic channel.

Migarashi Spot 2 FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.

This embodiment is an embodiment in which ten applications of high voltage in the first embodiment are replaced with one application.

In the case of this embodiment, the part where the parasitic channel is formed is the N-type substrate 1.
The function of the aluminum and polysilicon wirings 12 and 13 is the same as in the first embodiment.

As explained above, the present invention uses polysilicon and 1M
By preventing the formation of parasitic channels with a conductor such as aluminum, reliability can be improved without increasing the number of diffusion steps compared to double-layer aluminum.

[Brief explanation of drawings]

FIG. 1 is a vertical sectional view of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a vertical sectional view of a semiconductor device according to another embodiment. FIG. 3 is a sectional view of a conventional semiconductor device. 1...N type substrate, 2...P well, 3...NMOS source, 4...NMOS drain, 5...NMOS gate Electrode, 6...PMOS source, 7...PMOS drain, 8...PMOS gate electrode, 9...P well contact, 10...・Sub-contact, 11...Field oxide film, 12...Aluminum wiring, 13...Polysilicon wiring. ] Figure Figure

Claims (1)

[Claims] A high voltage semiconductor device characterized in that, in a high voltage MOSIC, the width of a conductive material such as ordinary polysilicon or aluminum wiring is increased to cover a channel forming part to prevent the formation of a parasitic channel.