JP2612495B2 - High voltage semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high breakdown voltage MOSFET. High pressure resistant MO
SFETs are ICs as discrete elements or with other semiconductor elements
It has been used.

(Prior Art) In a high-breakdown-voltage MOSFET in which a region serving as a source of a source region carrier and a region serving as a drain of a drain region carrier are provided on the surface of a substrate so as to face each other, the area around the source region is increased in order to increase the breakdown voltage. Is formed in a shape surrounding the element, called a guard ring (field limiting ring) of an impurity diffusion region of the same conductivity type as the source region (hereinafter simply referred to as a diffusion region).

3 and 4 show such a high breakdown voltage MOSFET, FIG. 3 shows a region where the wiring of the source electrode passes through the surface, and FIG. 4 shows no wiring. This is a representation of the area.

3 and 4, the high breakdown voltage MOSFET is formed on an N ^- silicon substrate 6 separated by the dielectric film 2. High pressure resistant MO
In semiconductor integrated circuit devices with SFETs formed on the same chip,
A lower concentration substrate is used as compared with a conventional semiconductor integrated circuit device. 4 is an N ⁺ layer. Reference numeral 8 denotes a source region, and 10 denotes a drain region. A P ⁺ diffusion region 12 of a guard ring is provided so as to surround the source region 8. 14 is a silicon oxide film and 16 is a metal wiring connected to the source region 8.
Reference numeral 18 denotes a polycrystalline silicon layer that supports elements separated by a dielectric film.

When such a high breakdown voltage MOSFET is integrated, it is inevitable that the electrode wiring for the source electrode and the gate electrode passes through the surface of the FET.

Under these circumstances, surface depletion or inversion channel leakage often occurs easily in the region immediately below the electrode. In particular, because the surface depletion immediately below the electrodes progresses, the reach-through (the state shown in FIG. 3) in which the depletion layer (the broken line area in FIG. 3) is connected to the high-concentration region 10 having the same conductivity type as the substrate and taking the substrate potential is obtained. Occur. In the vicinity of the reach-through drain region 10, the electric field intensity increases, and reaches a critical value as the applied voltage + V increases. On the other hand, in the region where the wiring does not pass, as shown in FIG. 4, the surface depletion has not progressed, and the electric field strength increases in the source region 8 and the guard ring 12.

Several countermeasures have been proposed for the problem of reduction in withstand voltage as follows.

A channel stopper with a high-concentration region of the same conductivity type as the substrate is introduced on the substrate surface immediately below the wiring. However, the structure still has a problem of reduction in breakdown voltage.

The substrate potential is taken, and an FRR (FRR) in which a medium concentration region is provided on the source region side in contact with the high concentration region 10 of the same conductivity type as the substrate.
ield Reduction Region) structure.

A field plate in which the gate electrode is made equal to the potential on the high impurity concentration side.

EQR (Equ
ipotential Ring).

Connect the resistor between the field plate and the EQR,
A device in which the electric field is gradually weakened (see Japanese Patent Application Laid-Open No. 47-2773). However, the structure has a drawback of a large leak current and a drawback of an increase in capacitance.

An opening is formed in the insulating film on the guard ring, and an electrode connected to the card ring is formed so as not to extend outside the guard ring region through the opening, and the insulating film between the electrodes is made two or more layers. Films in which the conductivity of the upper insulating film is higher than that of the lower insulating film
59-76466).

One in which a polycrystalline silicon film containing carbon or the like is deposited to a thickness of 100 to 4500 ° so as to directly cover the bonding surface of the substrate (see JP-A-62-76673). It is said that the polycrystalline silicon film releases hot carrier injection from the substrate.

(Problems to be Solved by the Invention) The present invention also provides a semiconductor device having means for suppressing a decrease in withstand voltage, and aims to suppress a decrease in withstand voltage due to a reach-through immediately below a wiring using a guard ring potential. It is assumed that.

(Means for Solving the Problems) In the present invention, a conductive layer insulated from the substrate and the electrode wiring by an insulating film and short-circuited to the guard ring is formed below the source electrode wiring and the gate electrode wiring.

(Example) FIG. 1 is a sectional view showing a state in which one embodiment is cut at a region of a source electrode wiring, and FIG. 2 is a plan view of a source electrode wiring region of the same embodiment.

The MOSFET is formed in a silicon substrate region separated by a dielectric film 22 such as a silicon oxide film. Reference numeral 26 denotes an N-type silicon substrate having a low impurity concentration, and reference numeral 24 denotes a high-concentration N-type diffusion layer provided at the bottom of the substrate 26, which is connected to a high-concentration N-type diffusion region 30 which is a drain region provided on the surface. ing. Reference numeral 28 denotes a source region composed of a high-concentration P-type diffusion region, which is provided on the substrate surface.

On the substrate surface, a high-concentration P-type diffusion region 32 having a shape surrounding the source region 28 is formed as a guard ring. The guard ring 32 is introduced to increase the pressure resistance.

The surface of the substrate 26 is covered with a silicon oxide film 34 which is a field oxide film. On the silicon oxide film 34, a conductive layer 40 of an impurity-doped polycrystalline silicon film is formed in a region where the source electrode wiring and the gate electrode wiring pass. In the figure, only the conductive layer 40 in the portion of the source electrode wiring 36 is shown. As an insulating film between the polycrystalline silicon film 40 and the wiring 36 formed thereon, an interlayer insulating film 42 such as a silicon oxide film is formed. On the interlayer insulating film 42, a source electrode wiring 36 and a gate electrode wiring (not shown) made of aluminum or the like are formed. The wiring 36 is connected to the source region 28 via contact holes provided in the insulating films 42 and 34. 50 is a contact between the wiring 36 and the source region 28.

The conductive layer 40 is short-circuited with the guard ring 32 as shown in FIG. A metal wiring 44 is formed, the guard ring 32 and the metal wiring 44 are connected by a contact 46, and the metal wiring 44 is connected to the conductive layer 40 via the contact 48.

 Next, the operation of the present embodiment will be described.

When operating this high voltage MOSFET, the drain region 30
Is applied with a positive power supply voltage + V, and the source region 28 is grounded. As the voltage is applied to the drain region 30, the potential of the guard ring 32 increases in the positive direction, and the potential of the conductive layer 40 also becomes positive. In the area where the wiring 36 passes, some substrate
Since the conductive layer 40 having a positive potential exists on the layer 26 via the field oxide film 34, depletion of the substrate surface immediately below the wiring 36 is suppressed, and a decrease in breakdown voltage is suppressed.

Similarly, a conductive layer having the same potential as the guard ring potential exists immediately below the gate electrode wiring, so that the occurrence of reach-through when the gate electrode potential is OV is suppressed.

(Effects of the Invention) In the present invention, a conductive layer insulated from the substrate and the electrode wiring by an insulating film and short-circuited to the guard ring is formed below the source electrode wiring and the gate electrode wiring, so that the wiring is formed by the guard ring potential. It is possible to prevent a reach-through from occurring immediately below, and to prevent a decrease in the breakdown voltage of the high breakdown voltage MOSFET. For example, in a high-breakdown-voltage MOSFET using an N ^- substrate having a resistance value of 40 Ωcm, the present invention has a breakdown voltage of 60 to 70 V in comparison with a conventional MOSFET having no conductive layer below the electrode wiring.
Can be higher.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a state in which one embodiment is cut in a region of a source electrode wiring, and FIG. 2 is a plan view of a source electrode wiring region in the same embodiment. FIG. 3 is a cross-sectional view of the conventional high-breakdown-voltage MOSFET cut along a source electrode wiring region, and FIG. 4 is a cross-sectional view of the conventional high-breakdown-voltage MOSFET cut along a region where no source electrode wiring passes. . 26 ... substrate, 28 ... source region, 30 ... drain region,
32 ... guard ring, 34 ... field oxide film, 36 ...
Wiring, 40: conductive layer, 44: metal wiring, 46, 48: contact.

Claims (1)

(57) [Claims] A region serving as a source and a region serving as a drain of the carrier are provided on the surface of the substrate so as to face each other; an impurity diffusion region having the same conductivity type as the region serving as the source is formed between the two regions; A high-voltage semiconductor integrated circuit device, wherein a conductive layer insulated from the substrate and the electrode wiring by an insulating film and short-circuited with the impurity diffusion region is formed below the electric wiring and the gate electrode wiring.