JPH0864809A - Mos transistor - Google Patents

Abstract

PURPOSE: To provide a high voltage MOS transistor which has stable characteristics by widening a breakdown part from a point area to a linear area. CONSTITUTION: A MOS transistor is formed on a first conductivity type semiconductor substrate 1, and provided with a source area 3 and a drain area 2 of a second conductivity type, which is opposite to the first conductivity type, at an interval, and a gate area 4 is provided between the source area 3 and the drain area 2 at an interval at least from the drain area 2. The source area 3, the drain area 2 and the gate area 4 are provided with electrodes, and a second conductivity type offset area 8 is provided to surround at least the drain area 2 and the area that includes the area between the drain area 2 and the gate area 4. The MOS transistor is provided with a first conductivity type channel stopper area 9 on the external side of the offset area 8 to surround the offset area 8, being separated from the offset area 8. An electrode 21 whereupon a high voltage is to be applied is arranged so as to overlap at least a part with the gate electrode 7 and the channel stopper area 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a high voltage MOS transistor having an offset structure.

[0002]

2. Description of the Related Art Conventionally, as this type of device, for example,
There is one disclosed in JP-A-61-171165. FIG. 3 is a plan view of such a conventional MOS transistor, and FIG. 4 is a sectional view taken along the line EE 'of FIG.

As shown in these figures, taking an NMOS as an example, first, the N ⁺ drain region 2 and the N ⁺ source region 3 formed of the same N ⁺ diffusion layer formed in the P-type substrate 1 are separated from each other. In between, there is a gate portion 4 separated from the N ⁺ drain region 2 and the N ⁺ source region 3, and a metal drain electrode 5, a metal source electrode 6 and a gate electrode 7 are formed as electrodes on each of them.

In addition, the N ⁺ drain regions 2 and N are separated from each other.
^An N ⁻ offset region 8 made of an N ⁻ layer is formed in the region excluding the gate portion 4 so as to surround the source region 3 and a region between the source region 3 and the gate portion 4. The gate electrode 7 extends at least outside the N ⁻ offset region 8. Furthermore, the N ^- spaced outwardly offset region 8, the N ^- P ⁺ channel stopper region 9 of the P ⁺ layer so as to surround the offset region 8 is arranged. In FIG. 4, 10 is a field oxide film and 11 is a PSG film as an interlayer insulating film.

[0005]

However, in the conventional MOS transistor described above, as shown in FIG.
The electric field changes at the corners of the N ⁻ offset region 8 and at the B overlapping with the gate electrode 7, so that electric field concentration occurs and the breakdown voltage is lower than the other portions. In the A and B parts, the weaker one is broken down due to the process parameters such as the concentration of the N ⁻ offset region 8 and the PN junction depth x _j that are formed.

Therefore, ESD, which is one of the IC standards,
Withstand voltage (electrostatic breakdown) is A with low breakdown voltage.
Since energy is consumed only in the area of section B or section B,
It will be low. Depending on the process parameters, there was a problem that it became too low to be used in actual use. An object of the present invention is to provide a high-voltage MOS transistor having stable characteristics by eliminating the above-mentioned problems and expanding the breakdown point from the point region to the line region.

[0007]

In order to achieve the above-mentioned object, the present invention provides a second conductive type semiconductor substrate (1) which is formed in a semiconductor substrate (1) of a first conductive type and is spaced apart from the first conductive type. Has a source region (3) and a drain region (2) of conductivity type, and a gate region (4) at least separated from the drain region (2) between the source region (3) and the drain region (2). The source region (3), the drain region (2) and the gate region (4) each have electrodes (6, 5, 7), at least around the drain region (2) and its drain region (2). And an offset region (8) of the second conductivity type are provided so as to surround a region including between the offset region (8) and the gate region (4), and the offset region (8) is spaced apart from the offset region (8) outside the offset region (8). , Of the first conductivity type so as to surround the offset region (8). In MOS transistor having a Nerusutoppa region (9), (A) electrode (5) to which a high voltage is applied, at least part is disposed so as to overlap with the gate electrode (7) and the channel stopper region (9).

(B) The electrode (5) to which a high voltage is applied is
The gate electrode (7) and the channel stopper region (9)
A part of the electrode (5) to which the high voltage is applied is removed in parallel so as to face the channel stopper region (9), and the region to be removed ( 32, 33, 34) are arranged in a region including the semiconductor substrate (1) inside a region facing the offset region (8).

(C) The channel stopper region (41)
A part (42, 43, 44) of which a part of is close to parallel is formed so as to face the offset region (8), and the part (42, 43, 44) of which is close to the offset region (8) is formed. It is arranged inside the area facing the. (D) Outside the offset region (8), inside the channel stopper region (9), an electrode (51) in a layer different from that of the electrode (5) for applying a high voltage is arranged, and also in this layer. The electrodes (51) are arranged in parallel so as to face the offset regions (8), are formed inside the regions facing the offset regions (8), and have the potentials of the electrodes (51) of different layers. Is set to a voltage lower than the potential of the electrode (5) to which a high voltage is applied.

[0010]

According to the present invention, since it is configured as described above, (1) the metal drain electrode is covered up to the P ⁺ channel stopper region, and the breakdown is the entire region of the P ⁺ channel stopper region facing the N ⁻ offset region. Since it is set to occur in, it is possible to obtain stable characteristics. In addition, E
Regarding the SD tolerance, the tolerance per unit area is
Since it is determined by the structure and the breakdown voltage, the ESD resistance can be improved by increasing the breakdown area.

(2) A part of the metal drain electrode, which has been a field plate, is removed so that the metal plate is broken down there.
Since there is a field plate to relax the electric field,
Breakdown occurs not only in the portion parallel to the N ⁻ offset region. Therefore, electric field relaxation is insufficient, breakdown does not occur at the C portion or the D portion, and stable characteristics can be obtained. Further, breakdown occurs in the line region as compared with the conventional case, and therefore breaks at points. Since the breakdown area is larger than what was down, ESD
The withstand amount can be improved.

(3) Breakdown occurs at the parallel portion of the P ⁺ channel stopper region which is close to the N ⁻ offset region. That is, as in the second embodiment, N
^- By selecting the degree of approach the offset regions appropriately, the breakdown, A part, not the point region of the B section, N ^- parallel portion of the P ⁺ channel stopper region close to the offset region, that is, a line region Since it was made to happen, the characteristics are stable.

Further, according to the above (2), the wiring could not be formed in the direction in which the metal drain electrode was removed, but in this embodiment, it is possible and the restriction on the wiring direction can be eliminated. Therefore, there is no restriction on the wiring direction.
It is possible to obtain a high voltage MOS transistor having a high withstand voltage.

(4) The added polycrystalline silicon electrode is N
^- Due to the so as to break down in a parallel section which is opposed to the offset region, similarly to the third aspect of the present invention, without having to break down in the region of the A section or B section, stable characteristics obtained To be Further, since it is formed of a polycrystalline silicon electrode which is a layer different from the metal drain electrode, there is no restriction on the wiring direction as in (3) above.
Further, unlike the case where the breakdown is determined by the P ⁺ channel stopper layer as in the above (3), since it is determined by the polycrystalline silicon electrode, the breakdown voltage can be restricted by the potential and the ESD tolerance is required. You can lower the breakdown only when, and you can raise it otherwise.

[0015]

Embodiments of the present invention will be sequentially described below with reference to the drawings. 1 is a plan view of a MOS transistor showing a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line FF 'in FIG. Here, the NMOS will be described as an example. As shown in these figures, as in the conventional case, the N ⁺ drain region 2 and the N ⁺ source region 3 formed of the same N ⁺ diffusion layer formed in the P-type substrate 1 are arranged separately.
In the meantime, a gate portion 4 is arranged apart from the N ⁺ drain region 2 and the N ⁺ source region 3, and a metal drain electrode 21, a metal source electrode 6 and a gate electrode 7 are arranged as electrodes on each of them.

Further, in the region excluding the gate portion 4 so as to surround the N ⁺ drain region 2, the N ⁺ source region 3 and the region between the N ⁺ drain region 2 and the N ⁺ source region 3 and the gate portion 4, an N ⁻ offset region 8 made of an N ⁻ layer is formed. Are arranged. The gate electrode 7 extends at least to the outside of the N ⁻ offset region 8. Also, N ^- spaced outwardly offset region 8, the N ^- P ⁺ channel stopper region 9 of the P ⁺ layer so as to surround the offset region 8 is arranged. In FIG. 2, 10 is a field oxide film and 11 is a PSG film as an interlayer insulating film.

As described above, the metal drain electrode 21 is
It is arranged so that at least a part thereof overlaps with the gate electrode 7 and the P ⁺ channel stopper region 9. With this configuration, when a high potential is applied to the metal drain electrode 21, a reverse junction is applied to the N ⁻ offset region 8 and the P-type substrate 1, and the N ⁻ offset region 8 is depleted.
A high breakdown voltage can be obtained by relaxing the electric field.

The place where the breakdown occurs is the place where the electric field is strongest, and changes depending on the concentration, shape, and depth of the N ^- offset region, but the breakdown generally occurs at the corners and the silicon surface. In this embodiment, the metal drain electrode 2
Since 1 is extended to the P ⁺ channel stopper region 9 outside the N ⁻ offset region 8, the metal drain electrode 21 serves as a field plate and relaxes the surface electric field particularly in the N ⁻ offset region 8. Therefore, the breakdown is performed by appropriately selecting the N ⁻ offset region 8, the concentration of the P-type substrate 1 and the insulating film thickness under the metal drain electrode 21, and by selecting the corner portion (A portion) and B of the N ⁻ offset region 8. By fully relaxing the electric field in the region, it occurs where the depletion layer from the P ⁺ channel stopper region 9 and the N ⁺ drain region 2 collide.

At this time, if the electric fields of the A part and the B part are sufficiently relaxed, the electric field difference between the C part and the D part and the other parts is almost eliminated, and the P ⁺ channel stopper region 9 on the N ⁺ drain region 2 side. However, breakdown occurs in the entire region facing the N ⁻ offset region 8. In other words, breakdown will occur at the line AA in FIG.
It is possible to reduce the concentration of the electric field.

In this way, the metal drain electrode 21 is
By covering up to the ⁺ channel stopper region 9, breakdown is caused to occur in the entire region of the P ⁺ channel stopper region 9 facing the N ⁻ offset region 8. Here, as for the ESD tolerance, the tolerance per unit area is
Since it is determined by the material, structure, and breakdown voltage, increasing the area for breakdown improves the ESD resistance. Therefore, in the first embodiment, since the breakdown area is increased, a high voltage MOS transistor having a high ESD withstand can be obtained.

FIG. 5 shows a MOS showing a second embodiment of the present invention.
FIG. 6 is a plan view of the transistor, and FIG. 6 is a sectional view taken along line GG ′ of FIG. Here, the NMOS will be described as an example. First
In the metal drain electrode 21 of the embodiment, in the region overlapping with the P ⁺ channel stopper region 9, at least the inner portion of the extended region of the N ⁻ offset region 8 on one side is
It is installed so as to be removed so as to include at least the P-type substrate region. That is, the metal drain electrode 31 is formed.

In this case, from the N ^- offset area 8 to P ⁺
The relationship between the distance l ₁ to the channel stopper region 9 and the distance l ₂ from the N ⁻ offset region 8 of the removed portion 32 of the metal drain electrode 31 to the metal drain electrode 31 is l ₂ <
to be l ₁ . Further, the removed portion has a portion which is parallel to the N ⁻ offset region 8.

Similar to the first embodiment, the metal drain electrode 31 serves as a field plate to extend the depletion layer from the N ⁺ drain region 2, but the portion where the metal drain electrode 31 is partially removed is further depleted. Since the layer does not extend, the breakdown will occur in the parallel portion facing the removed N ⁻ offset region 8, and the concentration of the electric field can be relieved.

FIG. 7 is a plan view of a MOS transistor showing a modification of the second embodiment of the present invention. As shown in this figure, the metal drain electrode 3 is formed in the longitudinal direction of the gate electrode 7.
Alternatively, the first removed portions 33 and 34 may be formed.
In this case, since the parallel portions can be formed at two places, the breakdown can be further reduced.

Although not shown, the shape of the metal drain electrode 31 may be a combination of FIGS. 5 and 7. In this way, a part of the metal drain electrode, which has been a field plate, is removed so that breakdown occurs there. Further, there is a field plate around the removed part to relax the electric field. Therefore, the breakdown always occurs in the portion parallel to the N ^- offset region.

Therefore, the relaxation of the electric field is insufficient, breakdown does not occur at the C portion or the D portion, and stable characteristics can be obtained. In addition, since the breakdown occurs in the parallel part compared to the conventional one, the breakdown area is larger than that broken down in the point area,
It is possible to obtain a high voltage MOS transistor having a high ESD tolerance.

FIG. 8 is a MOS showing a third embodiment of the present invention.
FIG. 9 is a plan view of the transistor, and FIG. 9 is a sectional view taken along the line HH 'in FIG. Here, the NMOS will be described as an example. In this embodiment, the metal drain electrode 5 is arranged in the same manner as the conventional one, but at least one side portion of the P ⁺ channel stopper region 41 on the N ⁺ drain region 2 side is brought closer to the N ⁻ offset region 8 side. Deploy. The portion 42 of the P ⁺ channel stopper region that has been brought close to is formed in parallel so as to face the N ⁻ offset region 8 side, and is located inside the facing region of the N ⁻ offset region 8.
Assuming that the portion 42 of the P ⁺ channel stopper region 41 brought closer to the N ⁻ offset region 8 is l ₂ and the others are l ₁ ,
Make sure that l ₂ <l ₁ .

When a potential is applied to the metal drain electrode 5, the depletion layer from the N ⁺ drain region 2 extends and N
^- before breakdown at the corners of the offset region 8 (A unit or B unit), N ^- closer to the offset region 8 P ⁺
Since the depletion layer collides with the portion 42 of the channel stopper region 41 and breaks down, concentration of an electric field can be reduced.

In this way, the breakdown occurs in the parallel portion of the portion 42 of the P ⁺ channel stopper region which is close to the N ⁻ offset region 8. Therefore, the second
Similar to the embodiment, by appropriately selecting the portion l _{2 in} which the distance of the P ⁺ channel stopper region 41 is close, the breakdown is not the A and B portions but the N ⁻ offset region 8
The characteristic is stable because it occurs in the parallel portion of the portion 42 of the P ⁺ channel stopper region which is close to.

FIG. 10 is a plan view of a MOS transistor showing a modification of the third embodiment of the present invention. As shown in this figure, the portions 43 and 44 of the P ⁺ channel stopper region may be formed close to the direction parallel to the longitudinal direction of the gate electrode 7. In this case, the part to approach is 2
Since it can be formed at a location, the breakdown can be further reduced.

Although not shown, the shape of the P ⁺ channel stopper region 41 which is a combination of FIGS. 8 and 10 may be formed. Further, in the second embodiment, wiring could not be performed in the direction in which the metal drain electrode was removed, but in the third embodiment, wiring can be performed in the direction in which the metal drain electrode was removed, and there is no restriction on the wiring direction. .

Therefore, it is possible to obtain a high voltage MOS transistor having a high ESD tolerance without any restriction on the wiring direction. 11 is a plan view of a MOS transistor showing a fourth embodiment of the present invention, and FIG. 12 is a sectional view taken along the line JJ 'of FIG. Here, the NMOS will be described as an example. In this embodiment, the metal drain electrode 5 is N ⁻ as in the conventional case.
The polycrystalline silicon electrode 51, which is arranged in the offset region 8 but is different from the layer used for the metal drain electrode 5, for example, a polycrystalline silicon layer used for the gate electrode 7, is provided as an N ⁻ offset region. It is installed so as to cover at least a part of the P type substrate 1 on the outside of the P ⁺ channel stopper region 9 on the outside of 8. That is, the distance l ₂ between the tip of the N ⁻ offset region 8 and the tip of the polycrystalline silicon electrode 51 is smaller than the distance l ₁ from the tip of the N ⁻ offset region 8 to the P ⁺ channel stopper region 9. To place.

Furthermore, the potential of the polycrystalline silicon electrode 51 is
Potential of polycrystalline silicon electrode 51 <metal drain electrode 5
So that the potential becomes. Thus, when a potential lower than that of the metal drain electrode 5, for example, the same potential as the metal source electrode 6, is applied to the polycrystalline silicon electrode 51, N ⁺
The extension of the depletion layer from the drain region 2 is suppressed by the polycrystalline silicon electrode 51, so that the breakdown occurs at a lower voltage than other portions. Therefore, by appropriately selecting the potential and position of the polycrystalline silicon electrode 51, N ⁻
Before the breakdown of the corner portion (A portion or B portion) of the offset region 8, the polycrystalline silicon electrode 51 breaks down in the parallel portion facing the N ⁻ offset region 8.

As described above, since the added polycrystalline silicon electrode 51 is broken down in the parallel portion facing the N ^- offset region 8, as in the third embodiment, the A portion or the B portion is formed. Stable characteristics can be obtained without breaking down at the part. In the fourth embodiment, since the polycrystalline silicon electrode 51, which is a layer different from the metal drain electrode 5, is formed, there is no restriction on the wiring direction as in the third embodiment.

Further, unlike the third embodiment in which the breakdown is determined by the P ⁺ channel stopper region 41, since it is determined by the polycrystalline silicon electrode 51, the breakdown voltage can be restricted by the potential. The breakdown can be lowered only when the ESD tolerance is required, and can be increased otherwise. Although the first to fourth embodiments have been described as applied to the NMOS, the P-type and the N-type are used.
It goes without saying that it can be applied to the PMOS by reversing the types.

Further, in the first to fourth embodiments, the ESD withstand capability is improved only on the drain side where a high voltage is required. However, if the source side also requires the withstand capability, the present invention can be applied to the source side. Needless to say. Further, in the first to fourth embodiment, apart from the N ⁺ source region 3 and the gate unit 4, although the configuration source side there is a breakdown voltage, and N ⁺ source region 3 and the gate 4 is in contact, the source-side Needless to say, the invention can also be applied to the drain side even if it has no withstand voltage.

Needless to say, the first to fourth embodiments can be used in combination. Further, in the first to fourth embodiments, the N ⁺ drain region 2 and the N ⁺ source region 3 are formed in the same layer, but it goes without saying that they may be formed in different layers. Further, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0038]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention of claim 1, the metal drain electrode is covered up to the P ⁺ channel stopper region, and the breakdown is caused to occur in the entire region of the P ⁺ channel stopper region facing the N ⁻ offset region. Stable characteristics can be obtained. Regarding the ESD tolerance, the tolerance per unit area is determined by the material, the structure, and the breakdown voltage. Therefore, the ESD tolerance can be improved by increasing the breakdown area.

(2) According to the second aspect of the present invention, a part of the metal drain electrode which has been the field plate is removed so as to break down there. , The breakdown is N because there is a field plate to relax the electric field.
^- occurs not only in the offset region and the parallel portions. Therefore, electric field relaxation is insufficient, breakdown does not occur in the C portion or D portion, stable characteristics can be obtained, and breakdown occurs in the line region (parallel portion) as compared with the conventional case. Therefore, the breakdown area becomes larger than the breakdown area that was broken down in the dot area.
The withstand amount can be improved.

(3) According to the third aspect of the invention, the breakdown occurs in the parallel portion of the P ⁺ channel stopper region which is close to the N ⁻ offset region. That is, similarly to the second embodiment, N ^- by appropriately selecting the degree of approach the offset region, the breakdown, A part, not the point region of the B section, N ^- P is brought close to the offset region ⁺ The characteristic is stable because it occurs in the parallel portion of the channel stopper region, that is, in the line region.

According to the second aspect of the invention, the wiring could not be formed in the direction in which the metal drain electrode was removed, but this embodiment makes it possible, and the restriction on the wiring direction can be eliminated. . Therefore, it is possible to obtain a high voltage MOS transistor having a high ESD tolerance without any restriction in the wiring direction.

(4) According to the invention of claim 4, since the added polycrystalline silicon electrode is broken down at the parallel portion facing the N ^- offset region, the invention of claim 3 is adopted. Similarly to the above, stable characteristics can be obtained without breaking down in the region of the A portion or the B portion. Further, since it is formed of a polycrystalline silicon electrode which is a layer different from the metal drain electrode, there is no restriction on the wiring direction as in the invention of claim 3. Further, unlike the invention according to claim 3, unlike the case where the breakdown is determined by the P ⁺ channel stopper layer, since it is determined by the polycrystalline silicon electrode, the breakdown voltage can be restricted by the potential, and the ESD resistance can be improved. Breakdowns can be low only when needed and high otherwise.

[Brief description of drawings]

FIG. 1 is a plan view of a MOS transistor showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line FF ′ of FIG.

FIG. 3 is a plan view of a conventional MOS transistor.

FIG. 4 is a sectional view taken along line EE ′ of FIG.

FIG. 5 is a plan view of a MOS transistor showing a second embodiment of the present invention.

6 is a sectional view taken along the line GG ′ of FIG.

FIG. 7 is a plan view of a MOS transistor showing a modification of the second embodiment of the present invention.

FIG. 8 is a plan view of a MOS transistor showing a third embodiment of the present invention.

9 is a cross-sectional view taken along the line HH 'of FIG.

FIG. 10 is a MOS showing a modification of the third embodiment of the present invention.
It is a top view of a transistor.

FIG. 11 is a plan view of a MOS transistor showing a fourth embodiment of the present invention.

12 is a sectional view taken along line JJ ′ of FIG.

[Explanation of symbols]

1 P-type substrate 2 N ⁺ drain region 3 N ⁺ source region 4 gate portion 6 metal source electrode 7 gate electrode 8 N ^- offset region 9,41 P ⁺ channel stopper region 10 field oxide film 11 PSG film 5, 21, 31 metal Drain electrode 32, 33, 34 Removed portion of metal drain electrode 42, 43, 44 Closed portion of P ⁺ channel stopper region 51 Polycrystalline silicon electrode

Claims (4)

[Claims] 1. A source region and a drain region formed in a semiconductor substrate of the first conductivity type and having a second conductivity type opposite to the first conductivity type and spaced apart from each other, the source region and the drain region. A source region, a drain region and a gate region each having an electrode, and a region including at least the periphery of the drain region and a region between the drain region and the gate region. A MOS transistor that has a second conductivity type offset region so as to surround it, and has a first conductivity type channel stopper region that is spaced apart from the offset region and that surrounds the offset region, outside the offset region. In the MOS, the electrode to which a high voltage is applied is arranged so as to at least partially overlap the gate electrode and the channel stopper region. Transistor. 2. A source region and a drain region, which are formed in a semiconductor substrate of the first conductivity type and have a second conductivity type opposite to the first conductivity type and spaced from each other, the source region and the drain region. A source region, a drain region and a gate region each having an electrode, and a region including at least the periphery of the drain region and a region between the drain region and the gate region. A MOS transistor that has a second conductivity type offset region so as to surround it, and has a first conductivity type channel stopper region that is spaced apart from the offset region and that surrounds the offset region, outside the offset region. In, the electrode to which the high voltage is applied is arranged so as to at least partially overlap the gate electrode and the channel stopper region,
A part of the electrode to which the high voltage is applied is removed in parallel so as to face the offset region, and the region to be removed is inside the region facing the offset region, A MOS transistor arranged in a region including the MOS transistor. 3. A source region and a drain region, which are formed in a semiconductor substrate of the first conductivity type and have a second conductivity type opposite to the first conductivity type and spaced apart from each other, the source region and the drain region. A source region, a drain region and a gate region each having an electrode, and a region including at least the periphery of the drain region and a region between the drain region and the gate region. A MOS transistor that has a second conductivity type offset region so as to surround it, and has a first conductivity type channel stopper region that is spaced apart from the offset region and that surrounds the offset region, outside the offset region. In, while forming a portion in which a part of the channel stopper region is close to parallel to face the offset region,
The MOS transistor characterized in that the close portion is arranged inside a region facing the offset region. 4. A source region and a drain region formed in a semiconductor substrate of the first conductivity type and having a second conductivity type opposite to the first conductivity type and spaced apart from each other, the source region and the drain region. A source region, a drain region and a gate region each having an electrode, and a region including at least the periphery of the drain region and a region between the drain region and the gate region. A MOS transistor that has a second conductivity type offset region so as to surround it, and has a first conductivity type channel stopper region that is spaced apart from the offset region and that surrounds the offset region, outside the offset region. In the above, while arranging an electrode in a layer different from an electrode for applying a high voltage inside the channel stopper region outside the offset region, Different electrodes are arranged in parallel so as to face the offset region, are formed inside the region facing the offset region, and the potentials of the different electrodes of the layers are different from those of the electrodes to which a high voltage is applied. A MOS transistor characterized by being set to a voltage lower than a potential.