JP2002270807A - Cmos image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS image sensor having low noises and high accuracy by realizing a structure, in which the substrate bias effect of a transistor for an amplifier is inhibited, in a small region. SOLUTION: In the CMOS image sensor in which a plurality of pixels 120 with photodiodes 9 and MOSFETs 28 for the amplifier for amplifying charges generated by photoelectric conversion in the photodiodes 9 are arrayed linearly or in an array shape, the first high-concentration impurity regions 28S having a reverse conductivity type to wells 124 for the MOSFETs 28 and constituting sources for the MOSFETs 28 and the second high-concentration impurity regions 121 having the same conductivity type as those of the wells 124 are formed in the wells 124, and the first high-concentration impurity regions 28S and the second high-concentration impurity regions 121 are brought into contact and arranged on a boundary section 135.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS image sensor, and more particularly to an element structure of a CMOS image sensor suitable for reducing noise while suppressing an area occupied by an amplifier for amplifying an output of a photodiode constituting a pixel. It is about.

[0002]

2. Description of the Related Art As a solid-state photoelectric conversion element, that is, a semiconductor optical image sensor, a CCD type and a CM are roughly divided.
There are two types of image sensors of the OS sensor type. CC
Although a D-type image sensor (hereinafter, also simply referred to as a CCD) is widely and practically used at present, a photoelectric conversion unit and a driving unit for driving photoelectric conversion (that is, a peripheral circuit unit) have different semiconductor element structures. It is manufactured by separate semiconductor integrated circuit manufacturing steps (processes).

On the other hand, in an image sensor of a CMOS sensor system (hereinafter, also simply referred to as a CMOS image sensor), a photoelectric conversion unit and a driving unit include a normal CMOS-L.
Since it can be manufactured by almost the same process as the SI process, the manufacturing line for CMOS-LSI can be used as it is, and the photoelectric conversion unit and the drive unit can be mixed and manufactured on the same substrate, so that the size is reduced. There is an advantage that an image sensor can be manufactured at low cost.

On the other hand, a CCD is used as a CMOS image sensor.
It is known that there is a problem that fixed pattern noise is large as compared with. On the other hand, a correlated double sampling circuit (Correlate Double Sampli) serving as a noise canceller is used to convert the output signal of the photoelectric conversion unit.
The noise is reduced by passing the signal through an ng circuit (hereinafter, also simply referred to as a CDS circuit).

Hereinafter, a conventional CM will be described with reference to the accompanying drawings.
The OS image sensor will be specifically described. FIG. 1 is a diagram showing a basic configuration of a conventional CMOS image sensor. FIG. 1 shows a CMOS image sensor 1 having a pixel configuration of 2 rows and 2 columns for simplicity of display. Therefore, in practice, for example, in an area sensor, a predetermined number of pixels 100A are arranged vertically and horizontally (that is, a predetermined number of rows and columns of the pixels 100A are formed). Is
A predetermined number of pixels 100A are arranged in one row or one column.

Each pixel 100A includes a row selection transistor 6, a reset transistor 7, an amplifier transistor 8, and a photodiode 9. The P side of the photodiode 9 is grounded, and the N side of the photodiode 9 is connected to the source electrode (also simply referred to as the source) of the reset transistor 7 and the amplifier transistor 8.
(Hereinafter, simply referred to as a gate).

The drain electrode (also simply referred to as the drain) of the reset transistor 7 is connected to the row selection transistor 6.
And the reference voltage supply line 17.
The source of the row selection transistor 6 is connected to the drain of the amplifier transistor 8. Reference voltage supply line 17
Are connected to a reference voltage power supply (not shown), and are supplied with a predetermined voltage. Note that the gate, drain, and source of each transistor, including the transistor described below, are indicated as G, D, and S in the figure, respectively.

Each pixel 100A is driven, and each pixel 100A is driven.
A vertical shift register 5, a load transistor 2, a noise canceller 11, a signal readout transistor 14, and a horizontal shift register 13 are arranged to extract an output signal from (element of) and output the signal to a signal processing circuit (not shown). A predetermined number of row signal output lines 15 and reset signal output lines 16 are connected to the vertical shift register 5. The row signal output line 15 is connected to the row selection transistor 6
Connected to the gate. Reset signal output line 16
Are connected to the gate of the reset transistor 7.

A load transistor 2 is arranged for each pixel column. The drain of the load transistor 2 is connected to a reference voltage supply line 3 connected to a reference voltage power supply (not shown) and supplied with a predetermined reference voltage. The gate of the load transistor 2 is connected to the load transistor drive line 4. The source of the load transistor 2 is connected to the column signal output line 10. The column signal output line 10 is arranged for each pixel column. The column signal output line 10 is connected to the source of each pixel amplifier transistor 8 and is connected to a noise canceller 11 described later.

The signal reading transistor 14 has a drain connected to the noise canceller 11 and a source connected to the signal output line 12.
The gates are connected to the horizontal shift register 13, respectively.

Next, the basic operation of the pixel 100A will be described. First, (1) a voltage Vd of a predetermined level is applied from the vertical shift register 5 to the gate of the reset transistor 7 through the reset signal output line 16 of a certain row, thereby turning on the reset transistor 7. The power supply voltage Vdd is supplied to the reference voltage supply line 17. The row select transistor is off.

Here, assuming that the threshold voltage of the reset transistor 7 is Vthrst, the photodiode 9
A voltage of Vp (= power supply voltage Vdd−threshold voltage Vthrst of the resetting transistor) is applied to the N-type terminal. This voltage becomes the initial voltage of the photodiode 9.

Next, (2) the voltage applied to the reset signal output line 16 is switched to a low level, and the reset transistor 7 is turned off. When light is incident on the photodiode 9 in this state, the photodiode 9 generates a pair of electron holes in proportion to the amount of light due to a photoelectric effect. The hole escapes toward the ground, and electrons go to the N-type of the photodiode 9 and the N-type terminal voltage of the photodiode 9 (ie, the gate voltage of the amplifier transistor 8).
Decreases by Vsig to become (Vp-Vsig).

Thereafter, (3) a predetermined voltage is applied from the vertical shift register 5 to the gate of the row selection transistor 6 through the row signal output line 15 to turn on the row selection transistor 6. As a result, since a voltage is applied to the drain of the row selection transistor 6 through the reference voltage supply line 17, a voltage is applied to the drain of the amplification transistor 8 through the source of the row selection transistor 6, and the amplification transistor 8 is turned on. I do.

Here, the amplifier transistor 8 is a source follower circuit, and the potential V of the column signal output line 10 is
as (= source potential of the amplifier transistor 8)
"Gate potential (= N-type terminal potential of photodiode 9:
Vp-Vsig) -threshold voltage of amplifier transistor 8 (here, the threshold voltage is Vthamp) "
Becomes Potential Vas (= Vp−Vsig−Vtham)
p) is the noise canceller 1 through the column signal output line 10.
1 is stored.

Next, (4) the reset transistor 7 is turned on again. Then, the N-type terminal of the photodiode 9 is reset to the potential Vp and the row selection transistor 6 is turned on.
p). The noise canceller 11 subtracts the previously stored value from this value, extracts Vsig, and outputs it to the signal output line 12. Next, (5) the row selection transistor 6 is turned off, the operation returns to the initial state, and the operation from (2) is repeated, whereby an electric signal corresponding to light is extracted from each pixel 100A.

[0017]

By the way, as described above, when the signal Vsig is obtained from the noise canceller, the threshold voltage of the amplifier transistor does not change. However, in reality, in the source follower circuit, since the voltage of the well of the transistor is constant and the potential of the source changes, the threshold voltage changes due to the substrate bias effect.

The substrate bias effect is expressed by the following equation as a change in the threshold voltage when the potential difference between the source and the well changes. ΔVth = (2εs * q * N * ΔVsb) ^1/2 / (εox / Tox) (1) where ΔVth: threshold change, εs: dielectric constant of silicon, q: electron charge , N: well impurity concentration, Δ
Vsb: change in potential difference between the source and the substrate; Tox: gate oxide film thickness; εox: dielectric constant of the silicon oxide film.

Normally, ΔVsb is fixed at 0 V. However, in the case of a source follower circuit, the source potential fluctuates, so that a substrate bias effect occurs. When there is a substrate bias effect, (1) the amplification factor of an amplifier transistor (hereinafter, also simply referred to as an amplifier) is reduced to about 0.8,
(2) There is a problem that the amplification factor varies for each amplifier of each pixel, and this becomes noise. For example, Tox = 9n
m, N = 1 × 10 ¹⁷ cm ⁻³ , ΔVsb = 1 V, relative permittivity of silicon is 11.8, relative permittivity of silicon oxide film is 3.98, and the effect of substrate bias (source of threshold voltage) Calculating the inter-substrate voltage dependence) is as follows.

[0020]

[Table 1]

The output signal Vsig is 2.5 V to 1.5 V
From the above table, the change ΔVth in the threshold voltage Vth due to the substrate bias effect is 753 mV−5.
84 mV = 151 mV. There is no problem if the amount of change in the threshold voltage of the amplifier transistor due to the substrate bias effect is the same for all the amplifier transistors of all pixels, but in practice this change is due to the same cause as the threshold voltage variation. Minutes vary.

For example, it is considered that a reasonable variation caused by the Tox process is about 1.5%.
Assuming that it varies by 5%, ΔVth is also 1.5%, that is, 1
51 × 0.015 = 2.25 mV varies. This variation acts as noise. Assuming that the dynamic range of the signal is 1.15 V, the noise is 2.25 mV.
, The S / N ratio is 54.1 dB, which is the CC
D becomes lower than the S / N ratio (55 dB to 60 dB).

In order to avoid such a substrate bias effect, the present applicant has disclosed in Japanese Patent Application No. 11-341819 a MOS transistor constituting an amplifier transistor of a pixel.
A method has been disclosed in which the well of the FET is separated from the other elements of the pixel and connected to the source of the amplifier.

Hereinafter, a description will be given as a conventional example in which the outline of the contents is improved. FIG. 2 is a diagram showing a configuration of an improved conventional CMOS image sensor, and FIG. 3 is a cross-sectional configuration diagram showing an element structure of the improved conventional CMOS image sensor. 2, the pixel 100B includes a reset transistor 7, an amplifier transistor 8, a row selection transistor 6, and a photodiode 9. The connection between these terminals is made by the amplifier transistor 8. Except that the source is connected to the well 101, it is the same as the pixel 100A constituting the conventional CMOS image sensor 1.

As shown in FIG. 2, when the well 101 of the amplifier transistor 8 is connected to the source, the potential of the well 101 moves together with the source potential, so that the substrate bias effect does not occur. However, the well 101 of the amplifier transistor 8 needs to be electrically separated from the wells of the other row selection transistors 6 and the reset transistor 7 to be in a floating state.

The floating structure will be described below with reference to FIG. As shown in FIG. 3, a P-type well 103 and a P-type well 104 are formed on an N− type substrate 102 at a distance L from each other. The P-type well 103 includes an N-type terminal (N + diffusion layer) of the photodiode 9 and a grounded P-type terminal (P + diffusion layer), a source (N + diffusion layer) and a drain (N +
+ Diffusion layer) and the source (N + diffusion layer) and drain (N + diffusion layer) of the reset transistor 7.

The P-type well 104 has a high-concentration N + diffusion layer (hereinafter, also simply referred to as a source) 8S serving as a source of the amplifier transistor 8 and a high-concentration N + serving as a drain.
P + diffusion layer 101 for connecting diffusion layer (hereinafter also simply referred to as drain) 8D and source 8S to well 104
Are formed, and the source and the well 104 are wired so as to have the same potential. The source 8S and the well 104 are connected to the column signal output line 10.

Next, details of the well 104 will be described. 4 is a detailed cross-sectional configuration diagram of the periphery of the amplifier transistor shown in FIG. 3, and FIG. 5 is an enlarged cross-sectional view of a portion A shown in FIG. The amplifier well 104 is separated from the other element wells 103 by a distance L by an N-type region (FIG. 3).

On the surface of the amplifier well 104, a drain N + diffusion layer 8D, a source N + diffusion layer 8S, and a P + diffusion layer 101 for connection to the separated amplifier well 104.
Is provided. N + diffusion layer 8D, N + diffusion layer 8S,
Field oxide film 111 is formed around P + diffusion layer 101.
A, 111B, and 111C are formed (the N + diffusion layer 8D, the N + diffusion layer 8S, and the P + diffusion layer 101 are formed using the field oxide films 111A, 111B, and 111C as a self-aligned mask).

A gate electrode 8G is formed above the source 8S and the drain 8D via a gate oxide film 110. P + diffusion layer 101, source 8S, drain 8D, field oxide films 111A, 111B, 111C
The periphery of the gate electrode 8G is covered with the first insulating film 108.

First insulating layer 108 above P + diffusion layer 101, source 8S, drain 8D, and gate electrode 8G
Has a conductive contact 107 and a contact 107
S, a contact 107G, and a contact 107D are formed respectively.
7, the source 8S is connected to the metal wiring 106S via the contact 107S, the gate electrode 8G is connected to the metal wiring 106G via the contact 107G,
The drain 8D is connected to the metal wiring 106D via the contact 107D.

First insulating layer 108 and metal wiring 106
A second insulating layer is formed on S, 106G, and 106D. Here, the distance ΔLco between the contact 107 and the field oxide film 111B,
The distance ΔLco between S and the field oxide film 111B is determined by a margin for preventing a contact from being formed close to the field oxide film 111B due to a displacement of a stepper used when forming the contacts 107 and 107S. .

FIG. 5 is an enlarged view of the portion A of FIG. 4. When the contact 107S is formed close to the field oxide film 111B, the concentration of the source 8S on the field oxide film 111B side is reduced. Since the contact 107S is thin, the portion of the contact 107S is short-circuited with the well 104 at the short portion 112.
This is because a margin of the distance ΔLco is required. This margin is about ΔLco = 0.2 μm in the 0.35 μm rule. In addition, the width of the field oxide film 111B has a minimum width ΔLf that can be formed, and is ruled.
In the 0.35 μm rule, it is about 0.6 μm.

The pixel area of a recent high-definition CMOS image sensor is, for example, 7.5 μm × 7.5.
It is as small as less than μm. As shown in the above-mentioned improved conventional example, the amplifier transistor MO
Although the method of connecting the source of the SFET and the well is effective in improving the amplifier characteristics, the number of contacts is increased, and as a result, the area ratio of the amplifier transistor to the pixel is increased. There is a problem that the area ratio of the diode is reduced and the sensitivity of the CMOS image sensor is reduced. A certain margin is required for the distance between the contact and the field oxide film. Further, a field oxide film is provided between the P + diffusion layer connected to the source and the well, and the area occupied by the amplifier transistor There was a problem that it could not be reduced any more.

Therefore, the present invention solves the above-mentioned problems, and
In an OS image sensor, a structure for suppressing a substrate bias effect of an amplifier transistor forming a pixel can be realized in a small amplifier transistor region,
Accordingly, an object of the present invention is to provide a high-definition CMOS image sensor with less noise.

[0036]

As a means for achieving the above object, a CMOS image sensor according to the present invention comprises a photodiode and an amplifier MOSFE for amplifying a charge generated by photoelectric conversion in the photodiode.
In a CMOS image sensor in which a plurality of pixels having T are arranged in a line or array, a source of the amplifier MOSFET is formed in the well of the amplifier MOSFET with a conductivity type opposite to that of the well. No.
Forming a first high-concentration impurity region and a second high-concentration impurity region having the same conductivity type as the well;
Wherein the high-concentration impurity region and the second high-concentration impurity region are arranged in contact with each other at a boundary portion.

According to a second aspect of the present invention, in the first aspect, a metal wiring contact connected to the source is arranged so as to be in direct contact with the boundary.

[0038]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
For the sake of simplicity, the same components as those of the conventional example are denoted by the same reference numerals, and the description thereof is omitted.

<Embodiment> FIG. 6 shows a CMOS according to the present invention.
FIG. 4 is a cross-sectional view illustrating an example of an element structure of an image sensor. Here, an amplifier formed in an amplifier well 124 according to the present invention is replaced with an amplifier transistor 8 formed in an improved conventional well 104 (hereinafter also simply referred to as a well) 104 shown in FIG. A transistor 28 is shown, and the other element portions of the pixel 120 are the same as those shown in FIG. The equivalent circuit (not shown) of the pixel 120 of the CMOS image sensor according to the present invention is the same as the equivalent circuit of the pixel 100B.

As shown in FIGS. 6 and 3, the well 124 in which the amplifier transistor 28 is formed is
In FIG. 2, it is formed separated from the well 103 where the photodiode 9 and the like are formed by a distance L (see FIG. 3). The P-type well 103 includes an N-type terminal (N + diffusion layer) of the photodiode 9, a P-type terminal (P + diffusion layer) grounded, and a source (N
A + diffusion layer) and a drain (N + diffusion layer), and a source (N + diffusion layer) and a drain (N + diffusion layer) of the resetting transistor 7 are formed (see FIG. 3).

The source 28S (N + diffusion layer) and the drain 28D (N + diffusion layer) of the amplifier transistor 28 and the source 28S are
A region 121 (P + diffusion layer) is formed in contact with the source 28S at the boundary 135 so as to be adjacent to the source 28S, and the source 28S and the well 124 are set to the same potential. The field oxide film 131A is formed in the region 121 and the field oxide film 1 is formed.
31B are formed adjacent to the drains 28D, respectively.

A gate electrode 28G is formed above the source 28S and the drain 28D via a gate oxide film 130. The periphery of the region 121, the source 28S, the drain 28D, the field oxide films 131A and 131B, the gate electrode 28G, and the gate oxide film 130 is the first region.
The region 121 and the source 28 are covered with an insulating layer 128.
The first insulating layer 128 above a part of the S, the drain 28D, and the gate electrode 28G is removed, and conductive contacts 127, 127G, 127D are formed thereon, and the metal wirings 126, 126G, 126D are connected thereto. are doing. A second insulating layer having a predetermined thickness is formed on the metal wirings 126, 126G, 126D and the first insulating layer 128.

The position of the contact 127 is the boundary between the region 121 and the source 28G. Contact 12
7 is connected to the source 28G and the region 121, and the metal wiring 1
26, it is connected to the column signal output line 10. The position of the contact 127G is on the gate electrode 28G, is connected to the gate electrode 28G, and is connected to the N-type terminal of the photodiode 9 through the metal wiring 126G.

The contact 127D is located at the drain 28
D, connected to the drain 28D, and the metal wiring 12
It is connected to the source of the row selection transistor 6 through 6D. Here, the contact 127 and the field oxide film 1
31A (contact 127D and field oxide film 131)
B) is the same as the allowance ΔLco in consideration of the displacement of the stepper, but this can prevent a short circuit between the contact and the well. .

Region 121 (P + diffusion layer) and source 28G
The (N + diffusion layers) are in contact at the boundary 135, which are arsenic as N-type ions, BF ₂ as P-type ions, and partially It is manufactured by ion implantation so as to overlap.
In the production method, the mass so towards the arsenic is large, a peak of the impurity concentration is often come to the substrate surface than the peak of the impurity concentration of BF _2. Therefore, the boundary portion 135 has, for example, a stepped shape as shown in the drawing, and the upper portion becomes N-shaped,
The lower part has a P-type structure. The reason why the region 121 and the source 28S overlap each other at the boundary portion 135 is to ensure that the region 121 and the source 28S are brought into contact with each other. Note that the boundary 135 may have any shape, such as a vertical plane or an oblique plane, as long as the boundary between the region 121 and the source 28S is formed.

As described above, in the CMOS image sensor of the present embodiment, unlike the improved conventional CMOS image sensor, the P + diffusion layer serving as an area for well connection with the N + diffusion layer serving as a source for an amplifying transistor. Since the layers are in contact with each other, a field oxide film for separating the N + diffusion layer and the P + diffusion layer is not required, and the region can be formed in a region smaller by the field oxide film ΔLf and the margin ΔLco on both sides thereof. N + diffusion layer in contact with P
+ Diffusion layer with the length of the contact 127 and the margin ΔLco
In this case, the area may be twice as long as.

The P + diffusion layer and the N + diffusion layer are brought into contact with each other.
Then, a PN junction is formed. PN junction is forward biased (P-type
Current> N-type potential), current flows,
Almost no current flows. But increase the reverse bias
When this happens, a breakdown occurs and current flows.
You. As the concentration of the P-type diffusion layer and the N-type diffusion layer is increased,
This breakdown voltage decreases, and P +, N
Concentration 10 called + ²⁰cm^-3Almost no concentration above
It becomes 0V. This is shown in FIG.

FIG. 7 is a graph showing current-voltage characteristics of a P + diffusion layer / N + diffusion layer (PN junction) in a CMOS image sensor according to the present invention. For the measurement, a semiconductor parameter analyzer 4145A manufactured by Hewlett-Packard (currently Agilent Technologies) was used.
In FIG. 7, the horizontal axis represents the voltage applied to the PN junction, the vertical axis represents the current at that time, and the concentration of the P-type diffusion layer and the N-type diffusion layer is 1 × 10 ²⁰ cm ⁻³ , It can be seen that the breakdown voltage is almost 0V.

As described above, by bringing the P + diffusion layer and the N + diffusion layer into contact with each other, the source of the amplifier transistor and the amplifier well can be electrically connected without passing through the metal wiring connected to each other, and the potentials are made the same. be able to. Therefore, the substrate bias effect can be suppressed, noise can be reduced,
If the contact area is formed at the boundary between the P + diffusion layer and the N + diffusion layer, the contact can be conducted to both the P + diffusion layer and the N + diffusion layer. The source and the well can be set to the same potential.

[0050]

As described above, according to the CMOS of the present invention,
The image sensor according to claim 1, wherein a first high-concentration impurity region having a conductivity type opposite to that of the well and constituting a source of the amplifier MOSFET is provided in a well of the amplifier MOSFET. Forming a second high-concentration impurity region having the same conductivity type as the well, and arranging the first high-concentration impurity region and the second high-concentration impurity region in contact with each other at a boundary portion. A structure that suppresses a substrate bias effect of an amplifier transistor constituting a pixel can be realized in a small amplifier transistor region, thereby achieving a high-definition CMOS with less noise.
There is an effect that an image sensor can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a conventional CMOS image sensor.

FIG. 2 is a diagram showing a configuration of an improved conventional CMOS image sensor.

FIG. 3 is a cross-sectional configuration diagram showing an element structure of an improved conventional CMOS image sensor.

4 is a detailed cross-sectional configuration diagram around the amplifier transistor shown in FIG. 3;

FIG. 5 is an enlarged sectional view of a portion A shown in FIG.

FIG. 6 is a sectional view showing an embodiment of an element structure of a CMOS image sensor according to the present invention.

FIG. 7 is a graph showing current-voltage characteristics of a P + diffusion layer / N + diffusion layer in a CMOS image sensor according to the present invention.

[Explanation of symbols]

1. CMOS image sensor 2. Load transistor
3: Reference voltage supply line, 4: Load transistor drive line, 5
... vertical shift register, 6 ... row selection transistor, 7 ...
Reset transistor, 8 ... amplifier transistor,
8D: N + diffusion layer (drain), 8G: gate electrode, 8
S: N + diffusion layer (source), 9: photodiode, 1
0 ... column signal output line, 11 ... noise canceller, 12 ... signal output line, 13 ... horizontal shift register, 14 ... signal reading transistor, 15 ... row signal output line, 16 ... reset signal output line, 17 ... reference voltage supply line , 28... Amplifier transistor, 28 D... N + diffusion layer, 28 G... Gate electrode, 28 S. N + diffusion layer, 100 A, 100 B.
101 ... P + diffusion layer, 102 ... N-substrate, 103 ... P-
Well, 104 ... (for amplifier) P-well, 105 ... N
Mold layer, 106D, 106G, 106S: metal wiring, 1
07, 107D, 107G, 107S ... contact, 1
08: first insulating film, 109: second insulating film, 110: gate oxide film, 111, 111A, 111B, 111C: field oxide film, 112: short part, 120: pixel, 121: P + well, 122: N- Substrate, 124 ...
(For amplifier) P-well, 126, 126D, 106G
... Metal wiring, 127, 127D, 127G ... Contact, 128 ... First insulating film, 129 ... Second insulating film, 130
... gate oxide films, 131A and 131B ... field oxide films, 135 ... boundary portions.

Claims (2)

[Claims] A CMOS image sensor in which a plurality of pixels each having a photodiode and an amplifier MOSFET for amplifying an electric charge generated by photoelectric conversion in the photodiode are arranged in a line or array. A first high-concentration impurity region having a conductivity type opposite to that of the well and constituting the source of the amplifier MOSFET, and a second high-concentration impurity region having the same conductivity type as the well are formed in the well. Forming
A CMOS image sensor, wherein the first high-concentration impurity region and the second high-concentration impurity region are arranged so as to be in contact with each other at a boundary. 2. The CMOS image sensor according to claim 1, wherein a metal wiring contact connected to said source is arranged so as to directly contact said boundary.