JP2001160619A - Cmos image sensor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS image sensor which is almost kept free from noises by a method wherein amplifying transistors which serve as pixels are restrained from varying in threshold value due to a substrate bias effect. SOLUTION: A CMOS image sensor is composed of pixels which are each equipped with a photodiode and an amplifying MOSFET that amplifies charge generated by the photodiode through photoelectric conversion and arranged in lines or an array, where the well of the amplifying MOSFET is electrically isolated from that of the other device contained in the pixel, and the source and well of the amplifying MOSFET are kept at the same potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CMOS image sensor, and more particularly to a device structure of a CMOS image sensor suitable for reducing noise and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a solid-state photoelectric conversion element, that is, a semiconductor optical image sensor, a CCD type and a CM are roughly divided.
There are two types of image sensors of the OS sensor type. CC
Although a D-type image sensor (hereinafter, also simply referred to as a CCD) is widely and practically used at present, a photoelectric conversion unit and a driving unit for driving photoelectric conversion (that is, a peripheral circuit unit) have different semiconductor element structures. It is manufactured by separate semiconductor integrated circuit manufacturing steps (processes).

On the other hand, in an image sensor of a CMOS sensor system (hereinafter, also simply referred to as a CMOS image sensor), a photoelectric conversion unit and a driving unit include a normal CMOS-L.
Since it can be manufactured by almost the same process as the SI process, the manufacturing line for CMOS-LSI can be used as it is, and the photoelectric conversion unit and the drive unit can be mixed and manufactured on the same substrate, so that the size is reduced. There is an advantage that an image sensor can be manufactured at low cost.

On the other hand, it is known that a CMOS sensor has a problem that fixed pattern noise is larger than that of a CCD. On the other hand, the output signal of the photoelectric conversion unit is converted into a correlated double sampling circuit (Co) which is a noise canceller.
The noise is reduced by passing the signal through a relay double sampling circuit (hereinafter, also simply referred to as a CDS circuit).

Hereinafter, a conventional CM will be described with reference to the accompanying drawings.
The OS image sensor will be specifically described. FIG. 1 is a diagram showing a basic configuration of a conventional CMOS image sensor. FIG. 1 shows a CMOS image sensor 1 having a pixel configuration of 2 rows and 2 columns for simplicity of display. Therefore, in practice, for example, in an area sensor, a predetermined number of pixels are arranged vertically and horizontally (that is, a predetermined number of rows and columns of pixels are formed). For example, in a line sensor, The predetermined number of pixels is 1
Only one row or one column is arranged.

Each pixel is composed of a row selection transistor 6, a reset transistor 7, an amplifier transistor 8, and a photodiode 9. The P side of the photodiode 9 is grounded, and the N side of the photodiode 9 is connected to the source electrode (simply referred to as the source) of the reset transistor 7 and the gate electrode (simply referred to as the gate) of the amplifier transistor 8. It is connected. The drain electrode (also simply referred to as the drain) of the reset transistor 7 is connected to the drain of the row selection transistor 6 and the reference voltage supply line 17. Reference voltage supply line 17
Are connected to a reference voltage power supply (not shown), and are supplied with a predetermined voltage. The source of the row selection transistor 6 is connected to the drain of the amplifier transistor 8. Note that the gate, drain, and source of each transistor, including the transistor described below, are indicated as G, D, and S in the figure, respectively.

The vertical shift register 5, the load transistor 2, the noise canceller 11, and the signal readout transistor 14 are driven to drive each pixel, take out an output signal from (a device of) each pixel, and output the output signal to a signal processing circuit (not shown). And a horizontal shift register 13.
The vertical shift register 5 has a predetermined number of row signal output lines 1.
5 and the reset signal output line 16 are connected. The row signal output line 15 is connected to the gate of the row selection transistor 6. The reset signal output line 16 is connected to the gate of the reset transistor 7.

[0008] A load transistor 2 is arranged for each pixel column. The drain of the load transistor 2 is connected to a reference voltage supply line 3 connected to a reference voltage power supply (not shown) and supplied with a predetermined reference voltage. The gate of the load transistor 2 is connected to the load transistor drive line 4. The source of the load transistor 2 is connected to the column signal output line 10. The column signal output line 10 is arranged for each pixel column. The column signal output line 10 is connected to the source of each pixel amplifier transistor 8 and to a noise canceller described later.

The signal reading transistor 14 has a drain connected to the noise canceller 11 and a source connected to the signal output line 12.
The gates are connected to the horizontal shift register 13, respectively.

Next, the basic operation of the pixel section will be described. First, a certain voltage, for example, 3.6 V is applied from the vertical shift register 5 to the gate of the reset transistor 7 through the reset signal output line 16 of a certain row, whereby the reset transistor 7 is turned on.

Here, assuming that the threshold voltage of the resetting transistor 7 is 0.6 V, the N
A voltage of 3V (= 3.6V-0.6V) is applied to the mold terminal. This voltage becomes the initial voltage of the photodiode 9.

Next, the voltage applied to the reset signal output line 16 switches to a low level, and the reset transistor 7 is turned off. When light is incident on the photodiode 9 in this state, the photodiode 9 generates a pair of electron holes in proportion to the amount of light due to a photoelectric effect. The hole escapes toward the ground, and electrons go to the N-type of the photodiode 9, and the N-type terminal voltage of the photodiode 9 (that is, the gate voltage of the amplifier transistor 8) drops to, for example, 2V.

Thereafter, a predetermined voltage is applied from the vertical shift register 5 through the row signal output line 15 to the gate of the row selection transistor 6 to turn on the row selection transistor 6, and as a result, the reference voltage supply line 17 Since a voltage is applied to the drain of the row selection transistor 6, a voltage is applied to the drain of the amplification transistor 8 through the source of the row selection transistor 6, and the amplification transistor 8 is turned on.

Here, the amplifier transistor 8 is a source follower circuit, and the potential V of the column signal output line 10 is
The charge is amplified so that as (= source potential of the amplifier transistor 8) becomes “gate potential (= N-type terminal potential of the photodiode 9) −threshold voltage of the amplifier transistor 8”. For example, if the threshold voltage is 0.6 V, the potential of the column signal output line 10 becomes 1.4 V.

By the way, as described above, the column signal output line 1
The potential Va applied to 0 is affected by the threshold voltage of the amplifier transistor 8. If the threshold voltage of the amplifier transistor 8 of each pixel does not change, there is no problem.
The threshold voltage of ET usually varies about 30 mV in a chip. The variation in the threshold voltage directly results in the variation in the output voltage (that is, the output signal) of the column signal output line 10, that is, noise. The signal variation of 30 mV is very large with respect to the output 1 V of the photodiode 9. This variation in threshold voltage accounts for a significant proportion of fixed pattern noise in CMOS image sensors.

Therefore, a correlated double sampling circuit (also simply referred to as a CDS circuit) is provided in order to remove noise caused by the above-mentioned variation in threshold voltage. Various methods have been proposed, and examples of the CDS circuit will be described below.

FIG. 2 shows a correlated double sampling circuit (CD).
FIG. 3 is a circuit configuration diagram illustrating an example of an (S circuit). The input is input through the signal output line 10. The signal output line 10 has a capacity of 2
The terminal C2a of the capacitor 22 is connected to one end a of the switch 32 and one end b of the switch 31. One end b of the switch 32 is connected to a reference voltage supply line 23 connected to a reference voltage source (not shown). One end a of the switch 31 is connected to the terminal C1b of the capacitor 21 and the switch 33.
Is connected to one end b. The other terminal of the capacitor 21 is grounded. The terminal a of the switch 33 is connected to the drain of the signal reading transistor 14, and an output is taken out.

When the reset transistor 7 is turned on and the N-type terminal of the photodiode 9 is reset at the initial voltage of 3.0 V, the row selection transistor 6 is also turned on and the initial signal without light signal is applied to the column signal. Output to the output line 10. At this time, the output Vas of the column signal output line 10 is
From 3.0 V, the threshold voltage of the amplifier transistor is set to 0.
It becomes 2.4V which subtracted 6V.

At this time, the switches 31 and 32 of the CDS circuit are closed and the switch 33 is open. The reference voltage supply line 23 has a reference voltage Vr of, for example, 3.0 V.
ef is supplied. Therefore, in this state, the terminal C
Since the potential of 2a is 3.0 V and the column signal line output line 10 is 2.4 V, a potential difference of 0.6 V is applied to the capacitor C2. Since the potential of the terminal C1b is the reference voltage Vref of 3.0 V, the capacitor 21 has a potential of 3.0 V between the ground.
It takes.

Next, the reset transistor 7 and the row selection transistor 6 are turned off, and the charge is stored by the photodiode 9. After the charge accumulation, the row selection transistor 6 is turned on again, whereby the amplifier transistor 8 is turned on, and the output voltage is taken out from the source of the amplifier transistor 6. At this time, the switch 32 in the CDS circuit
Open and off, switch 31 on, switch 33
Leave off. As described above, assuming that the potential at the N-type terminal of the photodiode 9 drops by 1 V to 2.0 V, the output to the column signal output line 10 is equal to the threshold voltage of the amplifier transistor 8 of 0.6 V. 1.4V
Becomes

The change in the potential of the capacitor 22 on the column signal output line 10 side is 2.4 V-1.4 V = 1.0 V, which is equal to the change in the potential of the photodiode 9. At this time, the amount of change in the terminal C1b of the capacitor 21 (this is the same as the change in the terminal C2a of the capacitor 22) is the change in the potential of the column signal output line 10 ((the capacitance C2 of the capacitor 22) /
((Capacity C1 of capacity 21) + (Capacity C2 of capacity 22))
Double. For example, if C1 = C2 = 1pF, the change is 0.5V.

Therefore, the potential of the terminal C1b at this time is 3.0-0.5 = 2.5V. Since only the value proportional to the change in the N-type terminal of the photodiode 9 is output, the threshold component of the amplifier MOSFET is removed. Next, the switch 31 is turned off and the switch 33 is turned on (the switch 32 remains off), and a signal from which noise is canceled is output to the source of the signal reading transistor 14.

As described above, the signal after passing through the CDS circuit is only a component proportional to the change of the phototransistor, and the threshold voltage and thermal noise of the amplifier transistor are removed. Noise is suppressed.

[0024]

The above description has been made on the assumption that the threshold voltage of the amplifier transistor does not change when noise is canceled by the CDS circuit. However, in reality, in the source follower circuit, since the voltage of the well of the transistor is constant and the potential of the source changes, the threshold voltage changes due to the substrate bias effect. The substrate bias effect is expressed by the following equation as a change in threshold voltage when the potential difference between the source and the well changes.

ΔVth = (2εs * q * N * ΔVsb) ^1/2 / (εox / Tox) (1) where ΔVth: threshold change, εs: dielectric constant of silicon, q: electron charge , N: well impurity concentration, Δ
Vsb: change in potential difference between the source and the substrate; Tox: gate oxide film thickness; εox: dielectric constant of the silicon oxide film. Tox = 9 nm, N = 1 × 10 ¹⁷ cm ⁻³ , ΔV
Assuming that sb = 1V, the relative permittivity of silicon is 11.8, and the relative permittivity of the silicon oxide film is 3.98, the effect of the substrate bias (the dependence of the threshold voltage on the source-substrate voltage) is as follows. Become like

[0026]

[Table 1]

When the output signal changes from 2.5V to 1.5V, the above table shows that the change in threshold voltage due to the substrate bias effect is 753mV-584mV = 151mV. There is no problem if the change in the threshold voltage of the amplifier transistor due to the substrate bias effect is the same for the amplifier transistors of all pixels.However, in practice, this change is also caused by the same variation in the threshold voltage. Vary.

For example, it is considered that a reasonable variation caused by the Tox process is about 1.5%.
Assuming that it varies by 5%, ΔVth is also 1.5%, that is, 1
51 × 0.015 = 2.26 mV varies. This variation acts as noise. At this time, the S / N ratio on the column signal output line is 52.9 dB because the signal is 1000 mV and the noise is 2.26 mV. This is the S / N ratio (55 to 60) of the CCD image sensor.
And dB), which is a low value, and this improvement was a problem.

Therefore, the present invention solves the above-mentioned problems, and
It is an object of the present invention to provide a CMOS image sensor with less noise in an OS image sensor, which suppresses a change in threshold value due to a substrate bias effect of an amplifier transistor included in a pixel, and a method of manufacturing the CMOS image sensor.

[0030]

As a means for achieving the above object, a CMOS image sensor according to the present invention comprises a photodiode and a MOSFE for an amplifier for amplifying a charge generated by photoelectric conversion in the photodiode.
In a CMOS image sensor in which a plurality of pixels having T are arranged in a line or array, a well of the amplifier MOSFET is electrically separated from a well of another element included in the pixel, and MOSF
It is an object of the present invention to provide a CMOS image sensor characterized in that the source of the ET and the well of the MOSFET for the amplifier have the same potential.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. Here, the present invention has been made based on the following considerations. That is, CM
A transistor for an amplifier constituting a pixel of an OS image sensor (the transistor described below is a MOSFE
It is composed of T. The substrate bias effect is caused by a difference in threshold voltage ΔVth due to a potential difference between the source and the well. Therefore, if the potential difference between the source of the amplifier transistor and the well can always be made the same, the occurrence of the substrate bias effect can be prevented. Most stably, it is preferable to connect the source of the amplifier transistor to the well and set the potential difference to zero.

FIG. 3 is a diagram showing a configuration of one pixel for explaining a basic configuration of a CMOS image sensor according to the present invention. The CMOS image sensor of the present invention differs from the conventional CMOS image sensor only in the pixel portion, and the principle of signal extraction and the contents of the driving circuit are the same as those described in FIG. 1 as the conventional example. Therefore, the description is omitted to avoid complication.

Referring to FIG. 3, the pixel includes a reset transistor 7, an amplifier transistor 8, a row selection transistor 6, and a photodiode 9. The connection between these terminals is such that the source of the amplifier transistor 8 is a well 101. Except that it is connected to a conventional CMOS.
The pixels are the same as those constituting the image sensor 1.

In the CMOS image sensor according to the present invention, since the source and the well of the amplifier transistor constituting the pixel are connected, the output signal does not include the substrate bias effect, and a signal output is obtained through the CDS circuit. Therefore, the threshold voltage is canceled and MO
It is possible to extract a pure signal that does not include the structural characteristics of the SFET in the signal.

As shown in FIG. 3, when the well 101 of the amplifier transistor 8 is connected to the source, the potential of the well 101 moves together with the source potential, so that the well 101 of the amplifier transistor 8 is connected to another row selection transistor. 6 and the well of the reset transistor 7 must be electrically floating. That requires a special method. Hereinafter, the details of connecting the source of the amplifier transistor 8 and the well 101 to form a floating structure will be described in detail.

Embodiment 1 FIG. 4 shows a CMO according to the present invention.
FIG. 2 is a cross-sectional view illustrating a first embodiment of the element structure of the S image sensor. As shown in FIG. 4, the N− type substrate 102 includes:
A P-type well 103 and a P-type well 104 are separately formed by a distance L.

In the P-type well 103, the N-type terminal (N +) of the photodiode 9 and the P-type terminal (P
+), The source (N +) and drain (N +) of the row selection transistor 6, and the source (N +) and drain (N +) of the reset transistor 7 are formed. The source (N +) and the drain (N +) of the amplifier transistor 8 and the source
A region (P +) for connecting to the source 04 is formed, and the source and the well 104 are wired so as to have the same potential.
The source and well 104 are connected to the column signal output line 10.

The specific numerical values of each part are as shown below. The N-substrate concentration is about 5 × 10 ¹⁵ cm ⁻³ .
The P-wells 103 and 104 have a concentration of 1 × 10 ¹⁷ c
m ⁻³ and a depth of 3 μm. N + has a concentration of 1 × 10 ²⁰
cm ^-3 and a depth of 0.2 μm. P + has a concentration of 1 ×
It is 10 ²⁰ cm ^-3 and the depth is 0.2 μm. The size of each transistor is such that the gate length of the amplifier transistor 8 is 0.5 μm and the gate width is 3 μm, and the gate length of the reset transistor 7 is 0.5 μm and the gate width is 1 μm. The row selection transistor 6 has a gate length of 0.5 μm and a gate width of 1 μm.

P well 103 having photodiode 9, resetting transistor 7 and row selecting transistor 6
And the P well 104 where the amplifier transistor 8 is located,
Although separated by a distance L, the value of L is 2 μm.
On the surface thereof, an N region which is higher than the substrate can be provided to narrow the separation width. The concentration is 1 × 10 ¹⁷ cm ^-3 and the depth is 0.5 μm.

(Example 2) A method for separating wells is described in Example 1.
In such a case, the distance L between the P-wells needs to be sufficiently long, which is disadvantageous when attention is paid to miniaturization, and the following structure is preferable from the viewpoint of miniaturization.

FIG. 5 is a sectional view showing a second embodiment of the device structure of the CMOS image sensor according to the present invention. FIG.
Will be described together with its manufacturing method. First, N
Forming a nitride film on the entire surface of the substrate 102, and then removing a portion of the nitride film where the field oxide film 103 is to be formed; The nitride film in the well formation portion is left.

Next, a field oxide film 113 is formed by wet oxidation at 1000 ° C. Field oxide film 113
Is, for example, 0.35 μm. At this time, the lower half of the field oxide film, 0.175 μm, is formed in the substrate, and the upper half, 0.175 μm, is formed floating above the substrate 102. Thereafter, the nitride film is removed.

Next, on the surface of the region where the P-well 112 for the amplifier transistor is formed, boron as a donor impurity,
Phosphorus as an acceptor impurity is implanted into a deep region by an ion implantation apparatus. At this time, the implantation is performed under the field oxide film 113 (the portion where the N-type layer 111 is formed) so that the acceptor is deeper than the donor. The injection conditions are
For example, boron is performed at 100 KeV, and phosphorus is performed at 400 KeV. The concentration is set to about 1 × 10 ¹⁷ cm ⁻³ for the P well and about 2 × 10 ¹⁷ cm ⁻³ for the N-type layer 111 as an isolation region.

Similarly, a reset transistor, a row selection transistor, and a P-well 103 for a photodiode are used.
Is formed by ion implantation of boron. The injection voltage is 200 keV and the concentration is 1 × 10 ¹⁷ cm ⁻³ . At this time, for example, the depth of the normal P well of the reset transistor is about 1 μm. Thereafter, first, a gate electrode is formed, and then regions such as a source and a drain necessary for these wells 112 and 103 are formed. The source of the amplifier transistor and the well 112 are connected. FIG. 5 shows only the state of separation of the wells.

In this embodiment, each of the donor and the acceptor is formed by one injection, but the P-well 112 and the N-type layer 111 (which is an isolation region) of the amplifier transistor are implanted twice or more to obtain the concentration. A distribution may be provided. For example, the N-type layer 111 has a concentration of 1 × 10 ¹⁷ cm ⁻³ below the P-well 112 and is about the same as that of the P-well. By setting it to 2 × 10 ¹⁷ cm ⁻³ , the separation characteristics in the horizontal direction can be better than those in the vertical direction.

By manufacturing in this manner, the well 112 has a shape that bulges inward as much as the field oxide film has disappeared in the active region, and the depth D2 is the field oxide based on the substrate surface. About three times the film depth D1,
Even if it estimates many, it will be four times or less. Since the depth of the well 112 becomes shallower as the amount of deep phosphorus implanted is increased, the depth of the well 112 is set to the depth D1 of the field oxide film.
Can be set to an arbitrary depth of 4 times or less.

Further, since it is formed by ion implantation, there is no lateral spread as compared with the method using thermal oxidation, and a floating well suitable for miniaturization becomes possible. The features of the structure of the present embodiment are as follows. (1) LOCOS (Local Oxidizatio
n of Silicon) separation,
(2) Under the P well where the amplifier transistor is formed, an N-type region which is denser than the surrounding N-type is formed to perform vertical separation. As a result, the depth of the P well where the amplifier transistor is formed is smaller than that of the wells for other transistors and the like, and the depth is within four times the depth of the field oxide film.

(Embodiment 3) In the device structure shown in the above-mentioned embodiment 2, the required lateral separation width tends to be large due to bird's beak or the like in the lateral separation by the field oxide film. Therefore, as a structure suitable for further miniaturization, STI (Shallow Trend) is used as an element isolation method capable of miniaturization more than isolation by field oxidation.
Ch Isolation) is preferable.

FIG. 6 is a sectional view showing a third embodiment of the device structure of the CMOS image sensor according to the present invention. FIG.
As shown in FIG. 2, a P-well 121 for forming an amplifier transistor and a P-well 103 for other elements such as a reset transistor are formed in an N-substrate 102. P
Below the well 121, an N-type separation layer 122 for separating the P well 121 and the P well 103 is formed. At the boundary between P well 121 and P well 103, a trench 120 in which a silicon oxide film is formed is arranged to separate P wells 103 and 121.

In the P well 103 and the P well 121,
The amplifier transistor shown in the first embodiment and other reset transistors are formed. The source and the well of the amplifier transistor are connected. In FIG. 6, the wells 121, 103
Only the state of separation between them is illustrated.

The features of this structure are (1) STI is used, (2) the depth of the P well 121 is smaller than the depth of the trench 120, (3) the P well 121 and the N
That is, N-type impurities that are denser than the substrate are arranged in the N-type region 122 at the PN junction of the mold substrate 102, and vertical separation is also performed.

Here, the isolation width of the trench 120 is 0.2
μm and the depth is 0.6 μm. The trench 120 is filled with a silicon oxide film. The depth of the P well 121 is 0.5 μm, which is shallower than the depth of the trench 120, the concentration is 1 × 10 ¹⁷ cm ^-3 , and the lateral direction is completely separated. At a deeper position, there is an N-type separation layer 122 of, for example, 2 × 10 ¹⁷ cm ⁻³ , which is darker than the substrate 102, and performs vertical separation. The impurities are introduced by ion implantation, for example, 100 KeV of boron and 400 KeV of phosphorus.
It is formed by implantation with V.

In the above embodiments, the P-well is formed on the N-substrate. However, it is needless to say that the same effect can be obtained when the N-well is formed on the P-substrate. Absent.

[0054]

As described above, according to the CMOS of the present invention,
An image sensor is a CMOS image sensor in which a plurality of pixels each having a photodiode and an amplifier MOSFET for amplifying electric charges generated by photoelectric conversion in the photodiode are arranged in a line or array, and the well of the amplifier MOSFET is provided. Is electrically separated from the wells of other elements included in the pixel, and
The source of the amplifier MOSFET and the amplifier M
By setting the well of the OSFET to the same potential,
CMOS with low noise by suppressing fluctuation of the threshold value due to the substrate bias effect of the amplifier transistor constituting the pixel
There is an effect that an image sensor can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a conventional CMOS image sensor.

FIG. 2 is a circuit diagram illustrating an example of a double correlation sampling circuit.

FIG. 3 is a diagram showing a configuration of one pixel for describing a basic configuration of a CMOS image sensor according to the present invention.

FIG. 4 is a sectional view showing a first embodiment of a device structure of a CMOS image sensor according to the present invention.

FIG. 5 is a sectional view showing a second embodiment of the device structure of the CMOS image sensor according to the present invention.

FIG. 6 is a sectional view showing a third embodiment of the device structure of the CMOS image sensor according to the present invention.

[Explanation of symbols]

1-CMOS image sensor, 2-load transistor,
3-reference voltage supply line, 4-load transistor drive line, 5
A vertical shift register, a 6-row selection transistor, 7-
Reset transistor, 8-amplifier transistor,
9-photodiode, 10-column signal output line, 11-noise canceller, 12-signal output line, 13-horizontal shift register, 14-signal read transistor, 15-
Row signal output line, 16-reset signal output line, 17-reference voltage supply line, 20-CDS circuit, 21-capacity 1, 22-
Capacity 2, 23-reference voltage supply line, 31-switch 1, 3
2-switch 2, 33-switch 3, 100-pixel, 1
01-well P +, 102-substrate N-, 103-well P-, 104-well P-, 105-N-type layer, 111-
N-type layer, 112-well, 113-field oxide,
120-trench, 121-well, 122-N-type isolation layer.

Claims (5)

[Claims] 1. A CMOS image sensor in which a plurality of pixels each having a photodiode and an amplifier MOSFET for amplifying electric charges generated by photoelectric conversion in the photodiode are arranged in a line or array. A well is electrically separated from a well of another element included in the pixel, and a source of the amplifier MOSFET and a MOSFE for the amplifier are separated from each other.
CM having the same potential as that of the T well.
OS image sensor. 2. The amplifier MOSFE obtained when the gate electrode of the amplifier MOSFET is set at a predetermined potential.
By taking the difference between the output signal of T and the output signal when the gate potential of the amplifier MOSFET changes due to the charge generated by the photodiode,
2. The CMOS image sensor according to claim 1, further comprising a circuit that outputs a signal from which a threshold voltage component of the amplifier MOSFET is removed. 3. The method according to claim 1, wherein the amplifier MOSFET and the other element are electrically separated from each other by using a field oxide film.
2. The CMOS image sensor according to claim 1, wherein the depth of the well of the OSFET is four times or less the depth of the field oxide film. 4. The amplifier MOSFET and the other element are electrically separated by using STI, and the amplifier MO
The CFET according to claim 1, wherein the depth of the well of the SFET is smaller than the depth of the trench of the STI.
MOS image sensor. 5. A CMOS image sensor in which a plurality of pixels each having a photodiode formed on a substrate and an amplifier MOSFET for amplifying a charge generated by photoelectric conversion in the photodiode are arranged in a line or array. In the manufacturing method, after forming a field oxide film on the substrate, a well of the amplifier MOSFET is formed by implanting a donor and an acceptor one or more times by ion implantation. Production method.