JPS6151962A - Cmos semiconductor device - Google Patents

Abstract

PURPOSE:To enable latch-up to be prevented without the need of expensive epitaxial wafers by a method wherein, excluding at least one source, drain, and channel of a MOS transistor, and the neighborhood of the drain, the titled device is provided with a semiconductor layer with the same conductive type as that of the semiconductor substrate or the island and higher concentration. CONSTITUTION:A P<+> type layer 11 is subjected to ion implantation of high concentration except an N<-> island 3, an N-channel transistor source (N<+> diffused layer 4), drain (N<+> diffused layer 4'), and channel (part under a polycrystalline Si layer 7) and the neighborhood of the drain, thus changing the surface into the P<+> layer 11. Providing the surface of the P<-> substrate 10 with a P<+> layer 11 of low resistance in such a manner stabilizes the substrate 10 at a VSS potentential and makes the base potential of a parasitic N-P-N bi-polar transistor Tr1 difficult to increase; accordingly, latch-up can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a constant CMO3 dedicated system which prevents latch amplifiers.

[Prior art]

Conventionally, as this type of CMOS semiconductor device, for example,
A P channel is formed on the N substrate, and a KN channel MOS) is formed within this P layer, while a KP channel MOS) is formed on the N substrate.
MOS semiconductor devices are used.

However, in the above CMOS structure, the launch 7' knob phenomenon is more likely to occur due to the parasitic silicon risk operation, and this has become a serious problem as integrated circuits become finer.

This problem is solved by the conventional C
There is a MOS semiconductor device shown in FIG.

In the 10th, 1 digit P+ substrate, 2 is P- epitaxial 1 times, 3 is N- island, 4.4', 4' is N++
5.5', Da is a P+ diffusion layer, 6 is a gate oxide film, 7 is a polycrystalline silicon layer serving as a gate, 8 is a field oxide film, and 9 is an electrode wiring. In addition, N++ diffused layer 4'
and a P+ diffused die common contact, which is provided in order to stabilize the potential of the F-L- region.

In the case of this configuration, as shown in FIG. 2(a)K, the NPN bipolar transistor T
R1 and PNP bipolar transistor Tr2 are combined into 5 as shown. Note that R1 and R2 are collector resistances, and the collector resistance R3 has a low resistance because it is a P+ substrate 1. This equivalent circuit is shown in FIG. 2(b).

As shown in this equivalent circuit, in order to lower the converter resistance R2ya' of the KPNP bipolar transistor Tr2, the voltage between the emitter and the paste of the parasitic NPN bipolar transistor Tr1 is prevented from increasing and launch amplification is prevented.

However, the conventional CMO3 semiconductor device shown in FIG. 1 is an expensive epitaxial wafer. There is a drawback that the price of the final product used increases.

[Summary of the invention]

The present invention is designed to be similar to the above-mentioned T'L rC method, and is provided without using an expensive epitaxial quencher.

This invention will be explained below. In addition, here P-
I will explain about the various types of CMO3K that I use on the board.

[Embodiments of the invention]

FIG. 3 is a sectional view showing an embodiment of the present invention, and FIG. 4 is a plan view of the main parts thereof. Reference numerals 2 to 9 are the same as in FIG. 1, and reference numeral 10 indicates that the P-based substrate 11 is a P layer, which is indicated by diagonal lines in FIG. This P+ layer 1 N- island 3. High-concentration ion implantation 7 is performed on the source (N+ diffusion layer 4), drain (N+ diffusion W44' island) of the N-channel transistor, except for the channel (lower part of the polycrystalline silicon layer 7) and the vicinity of the drain to change the surface area. .In this way, the low resistance layer P+ layer 11YP− substrate 10
By providing a parasitic NPN bipolar transistor Tr on the surface of the P-substrate 10 is stabilized at the vss potential.
The base potential of i rises to K<<, and lunch amplifier can be prevented.

In the above embodiment, the substrate potential on the N-channel transistor side is stabilized, but the potential on the N-island 3 on the reverse KP channel transistor side may also be stabilized. In that case, the source, drain, gate, and vicinity of the drain of the P-channel transistor are replaced with an N+ layer. Also,
The same applies to P-fel type CMO8K fittings.

〔Effect of the invention〕

As explained above, this invention is based on the semiconductor substrate except for the source, drain, channel, and vicinity of the drain of at least one of the two MOS transistors provided on the semiconductor substrate with a low density. Moreover, since a semiconductor layer with a higher concentration than that is provided, it is possible to prevent lantern pumping without using an expensive epitaxy wafer, so it is possible to eliminate the latch 7 panel without increasing the price of the final product. There are advantages that CMO3 semiconductor devices can provide.

[Brief explanation of the drawing]

Figure 1 shows a conventional CMO using an epitaxy crystal wafer.
8 Cross-sectional view showing an example of a semiconductor device, FIGS. 2(a) and (b)
) is an explanatory diagram of a launch amplifier and its equivalent circuit diagram, and FIGS. 3 and 4 are a sectional view and a plan view of essential parts showing an embodiment of the present invention. In the figure, 1 is a P+ substrate, 2 is an IP-evidential layer, and 3 is a
is N-Island, 4. 4', 4' are N+ diffusion layers, 5.5', 5' are P+ diffusion layers, 6 is gate oxide film, 7
tt poly-M silicon layer, 8 is a field oxide film,! 1 is an electrode wiring, 10 is a P-based substrate 11 is a P layer. Note that the same reference numerals in the figures indicate corresponding parts. Agent: Masuo Ookimi (2 others) Figure 1 (a) Figure 3 procedural amendment (voluntary) Showa year, month, day 1, case description Patent Application No. 176085-1985 2,
Title of the invention CMO3 semiconductor device 3, relationship to the amended case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Jinhachibe Katayama 4, Attorney Address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Detailed explanation of the invention in the specification to be amended and Drawing 6, Contents of the amendment (1) [N-wafer system j on page 4, line 4 of the description is amended to read "N-well system". (2) Similarly, replace “2-9” on page 4, line 8 with “3-9.”
” he corrected. (3) Similarly, on page 5, lines 16-17, "latch amplifier without increasing price" is corrected to "latch up without increasing price." (4) Amend Figure 2(n) of the drawings as shown in the attached sheet. that's all

Claims (1)

[Claims] A MOS transistor is formed by providing impurity diffusion regions serving as a source and a drain from the surface of a lightly doped semiconductor substrate, and an island having a conductivity type opposite to that of the semiconductor substrate is formed from the surface of the semiconductor substrate. An impurity diffusion region serving as a source and a drain is provided from the MOS transistor to form a MOS transistor with a channel different from that of the MOS transistor, and further, the semiconductor except for the source, drain, channel of at least one of the two MOS transistors and the vicinity of the drain is provided. A CMOS semiconductor device characterized by providing a semiconductor layer of the same conductivity type as a substrate or an island, but with a higher concentration.