JPS61135150A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the generation of a latch-up phenomenon by forming the same conduction type high-concentration buried layer into the well side, shaping a diffusion layer in the same concentration connected to the high-concentration buried layer while surrounding a source and a drain in the MOS transistor and applying potential to the diffusion layer. CONSTITUTION:The same conduction type high-concentration P<+> type buried layer 12 is formed the P type well side, and an N<+> type source diffusion layer 7 and an N<+> type drain diffusion layer 8 in an N channel MOS transistor are surrounded and connected to the high-concentration buried layer 12. On a CMOS transistor, the value of a resistance component R2 between a base and an emitter5 in a parasitic vertical NPN transistor, a TR2, is reduced extremely by the high-concentration buried layer 12, and the value of said resistance component R2 is brought to the value or less of an emitter resistance component R4, thus theoretically preventing the ON Of the TR2. Accordingly, the TR2 is not turned ON even when another lateral PNP transistor TR1 is brought to an ON state, thus inhibiting the latch-up phenomenon of a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a CMO9 semiconductor integrated circuit device that takes measures to prevent rough stubble.

[Conventional technology]

A schematic configuration of a conventional semiconductor integrated circuit device of this type, in this case a common cMOS transistor, and its equivalent circuit are shown in FIGS. 5 and 6. That is, in each of these figures, reference numeral 1 represents an N-type semiconductor substrate, and reference numeral 2 represents a P-type semiconductor layer formed on this substrate. 3 and 4 are these semiconductor substrate l and semiconductor layer 2.
5 and B are N type and P type diffusion layers for supplying a potential to the P channel MOS transistor.
7 and 8 indicate the N-type source and drain diffusion layers of the N-channel MOS transistor; 3 and 10 indicate the P-channel and N-channel MOS transistor;
1 is an insulating oxide film for isolation between each element. Furthermore, TR1
ii and TR2 are the respective parasitic thyristors, R1 and R2 are the substrate resistance components of the P-channel and N-channel MOS transistors, R3 and R4 are the diffusion resistance components of the N-type and P-type source diffusion layers, and VDD and GN
D are a power supply terminal and a ground terminal, respectively.

[Problem that the invention seeks to solve]

That is, in the semiconductor integrated circuit device according to the conventional example described above, in the silicon semiconductor substrate l of the N- shadow region, there is an opposite conductive shadow region called a well, in this case P.
- a shadow area is provided, N- a P channel MOS in the shadow area;
An N-channel MOS transistor is configured in each of the transistors and the P-shaded region, so that structurally parasitic bipolar transistors are shown in FIG.
It will be configured as shown by TR2.

Here, TR1 is a lateral PNP transistor in which the source of the P-channel MOS transistor is the emitter, the N-substrate is the base, and the P-type well is the collector. -Based on shaped well.

It is a vertical NPN transistor whose collector is an N-substrate.

Therefore, in this conventional configuration, a parasitic thyristor circuit as shown in Fig. 6 is generated, so this parasitic thyristor is switched by external noise, etc., and an excessive current flows between the power supply and ground. CMOS tends to easily cause up phenomenon, and device configurations are destroyed by excessive current in this rough tube, especially for vertical NPN transistors.
Because it is based on a unique low concentration P-type well,
・It has a large current amplification factor, which is the main cause of generating a parasitic thyristor with a high latch-up rate due to external noise, etc., and has various structural problems.

In view of these problems in conventional devices, the present invention has been developed to reduce the latch-up phenomenon by reducing the resistance value between the emitter and base of a bipolar transistor in a parasitic thyristor structure in a MOS transistor circuit. It is an object of the present invention to provide a device configuration that is easy to use.

[Means for solving problems]

The semiconductor integrated circuit device according to the present invention has a circuit configuration of a CMOS transistor, in which a high concentration buried layer of the same conductivity type as that of the well side is formed, and the MOS
A diffusion layer of the same concentration is formed surrounding the source and drain of the transistor and connected to the high concentration buried layer, and a potential is applied to this diffusion layer.

[For production]

Therefore, in the case of the circuit and structure according to the present invention, the impurity concentration in the portion corresponding to the base region of the bipolar transistor parasitic to the CMOS transistor is increased, and the resistance value between the base and emitter is lowered. By preventing the parasitic thyristor from turning on, the latch-up phenomenon can be effectively suppressed.

〔Example〕

Embodiments of the semiconductor integrated circuit device according to the present invention will be described in detail below with reference to FIGS. 1 to 4.

These FIGS. 1 to 4 show schematic cross-sections of the device configuration to which different embodiments are applied, and in each figure of the device of these embodiments, the same reference numerals as those of the conventional device shown in FIG. 5 are the same or the same. A considerable portion is shown.

First, in the device of the first embodiment shown in FIG. 1, which has the same structure as the conventional device shown in FIG. High concentration of P
A buried layer 12 is formed, and N in the semiconductor layer 2 is
A P+ type diffusion layer 13 of the same conductivity type and the same concentration surrounds the N type source diffusion layer 7 and the N type drain diffusion layer 8 of the channel OS transistor from the outside and is connected to the high concentration buried layer 12. is formed in place of the P swelling diffusion layer 4 for supplying the electric potential, and this P swelling diffusion layer 1
3 so that an electric potential can be applied to it.

Therefore, in the device configuration of this first embodiment, a parasitic thyristor circuit is basically formed in the same manner as in the device configuration of the conventional example, and a similar equivalent circuit is established.
In the case of a transistor (C to O8) in the embodiment, by the high-concentration embedded calendar 12.

Parasitic vertical NPN transistor, that is, D2
The value of the resistance component R2 between the base and emitter of the transistor becomes extremely small, and if the value of the resistance component R2 is set to be less than the value of the emitter resistance component R4, theoretically, this TR2 will be difficult to turn on. Therefore, the other lateral P
Even if the transistor TR1 (NP) is turned on, the transistor TR2 is not turned on, thereby suppressing the latch-up phenomenon of the circuit.

Further, the first embodiment is a case of an N-type substrate and a P-type well, but as in the second embodiment shown in FIG.
The present invention can be similarly applied to a type substrate and an N-type well, and the same functions and effects can be obtained.

Furthermore, FIGS. 3 and 4 show a similar high-concentration buried layer 14 and a connection thereto on the semiconductor substrate 1 side in addition to the semiconductor layer 2 side in each case where the conductivity types are different. The apparatus configurations according to the third and fourth embodiments are shown in which diffusion layers 15 of the same conductivity type and the same concentration are formed, and in each of these configurations, the functions of the first and second embodiments are In addition, since each of the resistance components Rt and R3 can be made small, the latch-up phenomenon can be suppressed even more effectively.

〔Effect of the invention〕

As detailed above, according to the present invention, in the circuit configuration of a cMOS transistor, a buried layer is provided on the semiconductor layer (well) side, and a diffusion layer that surrounds the source and drain of the MOS transistor from the outside and is connected to the buried layer. Since it is possible to form the thyristor and apply a potential to it, it is possible to prevent the parasitic thyristor from turning on, and it can exhibit the excellent feature of effectively suppressing the ruff-up phenomenon in the circuit.

[Brief explanation of drawings]

1 to 4 are cross-sectional views showing the schematic structure of different embodiments of the semiconductor integrated circuit device according to the present invention, and FIG. 5 shows the schematic structure of the conventional semiconductor integrated circuit device. The sectional view shown in FIG. 6 is an equivalent circuit diagram. 1... Semiconductor substrate, 2... Semiconductor layer (well) formed in the substrate, 3.4... Diffusion layer for potential supply, 5.7... Source diffusion layer, 8, 8...
- Drain diffusion layer, 9, 10... gate section, 12.
14... High concentration buried layer, 13.15... Diffusion layer surrounding the source and drain and supplying potential to the high concentration buried layer. Agent Masuo Oiwa Procedural amendment (voluntary) Showa 6 5, 20 EI 2. Name of the invention Semiconductor integrated circuit device 3. Relationship to the person making the amendment Case Patent applicant address 2-2 Marunouchi, Chiyoda-ku, Tokyo No. 3 Name Title (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent 6, Contents of the amendment (11 FIA specifications, page 3, lines 2-3, “parasitic thyristor” is corrected to “parasitic bipolar 2 transistor”) (2) "Same conductivity type" on page 5, line 7 of the same book is corrected to "same conductivity type."

Claims (2)

[Claims] (1) A CMOS having a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type formed on this semiconductor substrate, each of which has a MOS transistor configured therein.
In a semiconductor integrated circuit device, a high concentration buried layer of the same conductivity type is formed on the side of the semiconductor layer, and a buried layer of the same concentration surrounds the source and drain of a MOS transistor in the semiconductor layer and is connected to the high concentration buried layer. 1. A semiconductor integrated circuit device comprising a diffusion layer formed therein and configured to be able to apply a potential to the diffusion layer. (2) A high concentration buried layer of the same conductivity type is formed on the semiconductor substrate side, and a diffusion layer of the same concentration is formed surrounding the source and drain of the MOS transistor in the semiconductor substrate and connected to the same high concentration buried layer. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured such that a potential can be applied to the diffusion layer.