JPS60211868A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of a latch-up by completely separating grounding lines for a bipolar element and an MOS element and connecting the grounding line for the bipolar element to an isolating layer. CONSTITUTION:A P type silicon substrate 1 as an emitter in a parasitic P-N-P transistor 21 has the same potential as a grounding line 18 for a bipolar element through an isolating layer 4. The P type silicon substrate 1 as an emitter in a parasitic P-N-P transistor 23 has the same potential as the grounding line 18 for the bipolar element through the isolating layer 4 while potential on the plus side of a power supply is applied to an N type silicon epitaxial layer 3 as a base through a power supply line 20 and an N<+> diffusion layer 15. That is, the parasitic P-N-P transistor 23 is brought to a reverse bias state-for example, the transistor 23 is not turned ON even when the potential of the grounding line for the bipolar transistor varies more or less, thus eliminating a latch-up.

Description

[Detailed description of the invention] [Technical field of invention] It is about stabilization.

(Prior art) Conventionally, there was a structure of this type of circuit as shown in Fig. 1. In Fig. 1, 1 is a P-type silicon substrate, 2 and 3 are N-type silicon epitaxial layers, and 4 is a bipolar element and a CMOS. It is a separation layer for separating the elements. 5.6
．． 7 are the base (P10 diffusion layer), emitter (N+10 diffusion layer), and collector (N+10 diffusion layer) of the NPN transistor, respectively. 8, 9, 10. 11 are the N channel (Nch) MOS) runs, respectively. Island of Risk (
12, 13.14 are the gate electrode and source (of the PchMOS transistor), respectively.
(P10 diffusion layer), and the drain (P10 diffusion layer). 15 is an N+ diffusion layer, which connects the N-type silicon emitter N3, which serves as the substrate for the PchMO3) run risk, and the power supply line 20.
This is for making ohmic contact. 16
1 is an oxide film, and 17 is an aluminum wiring. 1B, 19.20
are the ground line for the bipolar element, the ground line for the CMO3 element, and the power supply line, respectively.

Figures 2 and 3 are P-type silicon substrate 1-NPN, respectively.
) Between the range metal 22, P-type silicon substrate 1-NchM
21 and 22 in FIG. 2 are parasitic PNP transistors, N, and PN transistors, respectively. 23 in Figure 3 is a parasitic PNP) orchid risk.

24 and 25 indicate parasitic NPN transistors. In these figures, the same parts as in FIG. 1 are designated by the same reference numerals.

In this way, in the 1-MO3 integrated circuit, between the P-type silicon substrate 1-NPN') rungis 222.

Parasitic silicon risks as shown in FIGS. 2 and 3 exist between the P-type silicon substrate 1 and the NchMOS transistor, respectively.

Here, the ground line 19 for the 0MO8 element is connected to the separation layer 4 and is completely insulated from the ground line 18 for the bipolar element. Therefore, the potential of the 0MO3 element earth line 19 is applied to the P-type silicon substrate 1 through the isolation N4.

At this time, the resiliency risk between the P-type silicon 1 and NchMOS transistors is not turned on for the following reason. This is because the emitter of the parasitic PNP run risk 23, that is, the P-type silicon substrate 1, is at the same potential as the earth line 19 for the 0MO3 element, whereas the base, that is, the N-type silicon epitaxial layer 3, has an N-dozen scattered layer 15. This is because the positive voltage of the power supply is applied through the transistor, and therefore the parasitic PNP transistor 23 is not turned on.

However, the P-type silicon substrate 1 and the NPN drain disk 22
The si-risk in between turns on under the following conditions and causes the launch amplifier. That is, assuming that the NPN transistor 22 is turned on or off by a circuit signal applied to the base 5, when it is on, the parasitic PNP
) P-type silicon substrate 1 which is the emitter of run risk 21
The potential of the base, that is, the N-type silicon epitaxial layer 2
When the potential becomes higher than the potential of this parasitic PNP transistor 21
turns on, and from now on, the NPN transistor 22 has a base 5
It is related to the circuit signal applied to the circuit (it will continue to turn on).

In this way, in the conventional Bi-CMO8 integrated circuit having two ground lines, one for bipolar elements and one for CMO3 elements, the NPN) run risk 22 operates in a saturated state, and the potential of the P-type silicon substrate 1, that is, the 0 MO3 element When the potential of the ground line 19 rises, the parasitic silicon risk is turned on and launch-up occurs.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it completely separates the ground lines for bipolar elements and MO3 elements, and connects the ground line for bipolar elements to the separation layer. It is an object of the present invention to provide a semiconductor integrated circuit that can prevent the occurrence of launch amplifiers.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fourth
In the figure, 1 is a P-type silicon substrate, 2.3 is an N-type silicon epitaxial layer, and 4 is a bipolar element and CMO3.
This is a separation layer for separating the elements. 5 and 6.7 are respectively NPN) run risk base (P dozen scattered layer), emitter (N + ten dozen scattered layer), collector (N + ten dozen scattered layer. 8, 9゜10.11 are respectively NchMO3) run risk island (P-diffused layer), gate electrode, source (N 10-odd scattered l1i), drain (N 10-odd scattered layer), and 12, 13, 14 are the gate electrode of PchMO3) run risk, respectively. , source (P tens of N), drain (
P+diffusion N). Reference numeral 15 denotes an N-doped scattering layer, which is used to establish ohmic contact between the aluminum wiring and the N-type silicon epitaxial layer N3, which serves as the substrate for the PchMO3) run risk. 16 is an oxide film, and 17 is an aluminum wiring. 1B and 19.20 are a bipolar element ground line, a CMO3 element ground line, and a power supply line, respectively.

Further, in this embodiment, between the P-type silicon substrate 1-NPN) run disk 22, the P-type silicon group Fj, 1-NchMO
3) The parasitic parasitic risks that exist between the land disks are the same as those shown in conventional figures 2 and 3.

Next, the effects will be explained.

As mentioned above, the Bi-CMO3 integrated circuit of this embodiment also has a parasitic thyristor as in the conventional one, but the parasitic thyristor existing between the P-type silicon substrate 1 and the NPN) rungis 222 shown in FIG. Cyrisk does not work due to the following reasons: That is, the P-type silicon substrate 1, which is the emitter of the parasitic PNP run risk 21, has the same potential as the bipolar element earth line 18 through the isolation N4. However, this bipolar element ground line 18 is NPN.
It is connected to the emitter 6 of the transistor 22.

Under these conditions, the parasitic thyristor shown in FIG. 2 does not turn on.

Next, as shown in FIG. 3, there is a parasitic thyristor placed between the P-type silicon substrate 1 and the NchMOS transistor. 18, while the base N-type silicon epitaxial layer 1if3 has a power supply line 20. N
A potential on the positive side of the power supply is applied through the 15 wires.

In other words, the parasitic PNP run risk 23 is in a reverse bias state and will not turn on even if the potential of the ground line for the bipolar element changes somewhat. Therefore, the parasitic silicon risk shown in FIG. 3 does not turn on like the one shown in FIG. 2, and the latch-up that occurs in the conventional circuit can be eliminated.

In the above embodiment, a Bi-CMO3 integrated circuit has been described, but this may also be a Bi-MO3 integrated circuit, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor integrated circuit in which bipolar elements and MO3 elements are formed on the same semiconductor substrate, the ground lines for bipolar elements and MOS elements are completely separated, and the ground lines for bipolar elements and MO3 elements are completely separated. Since the ground line is connected to the separation layer, it is possible to prevent latch-up from occurring.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional Bi-CMO3 integrated circuit;
3 is a diagram showing the parasitic risk of B i-CMO3 integrated circuit, and FIG.
FIG. 2 is a cross-sectional view of an i-CMO3 integrated circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 4... Separation layer, 18... No1
Earth line for Ipolar element, 19...Earth line for CMO3 element, 22...NPN) Run risk. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa 2 Figure 3 Procedural amendment (voluntary) Showa 5 Ru August 22 2 Name of the invention Semiconductor integrated circuit 3 Person making the amendment Representative Hitoshi Katayama Dept. 4 Agent 5 Amendment Column 6 of the detailed description of the invention in the subject specification, Contents of amendment +11 "Nono Ibora MO3 (hereinafter referred to as Bi-MO3)" on page 1, lines 13-14 of the specification is changed to "Nono Ibora CMO3 (hereinafter referred to as Bi-MO3)" (hereinafter referred to as Bi-CMO5)". (2) On the 2nd page, lines 11-12, ``1 silicon emitter layer'' is corrected to ``silicon epitaxial layer''. (3) rB 1-M03J on page 3, line 6 of [Bi-
Corrected to CMO3J. -H

Claims (1)

[Claims] (1) A bipolar element and an MO3 element are formed on the same semiconductor substrate and separated by a separation layer, the ground terminals for each of the elements are provided insulated from each other, and the ground terminal for the bipolar element is provided on the separated layer. A semiconductor integrated circuit characterized by being connected in layers.