GB2045526A - Integrated circuit capacitors - Google Patents
Integrated circuit capacitors Download PDFInfo
- Publication number
- GB2045526A GB2045526A GB8010299A GB8010299A GB2045526A GB 2045526 A GB2045526 A GB 2045526A GB 8010299 A GB8010299 A GB 8010299A GB 8010299 A GB8010299 A GB 8010299A GB 2045526 A GB2045526 A GB 2045526A
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuit
- substrate
- semiconductor integrated
- layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000002245 particle Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 abstract description 26
- 239000002344 surface layer Substances 0.000 abstract description 2
- LBDSXVIYZYSRII-IGMARMGPSA-N alpha-particle Chemical compound [4He+2] LBDSXVIYZYSRII-IGMARMGPSA-N 0.000 description 5
- 239000002800 charge carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
- G11C19/186—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor integrated circuit includes storage capacitors (C1,C2) which, in order to minimise the incidence of soft errors caused by alpha particle bombardment, do not form depletion layers with the substrate (4). Each capacitor comprises two electrode layers (2, 2'; 3) separated by a dielectric layer (1). The lower electrode (3) is deposited on an insulating surface layer (13) on the substrate (4) and is connected either to the substrate or to a source of potential. <IMAGE>
Description
SPECIFICATION
Integrated circuit
This invention relates to techniques for preventing soft errors in integrated circuits and to integrated circuits employing said techniques.
In the course of investigating the susceptibility of e.g. dynamic RAMs to alpha particles which, in particular types of storage structures, are likely to cause so-called soft faults there have been recognized the electric fields of the electron/hole pairs forming the depletion layers in the substrate in N-channel technology. Without the charge separation by these fields, the electron/hole pairs produced within a narrow channel around the track of the alpha particles, recombine and thus prevent charge-sensitive structures from recharging. Per alpha particle stroke it has been possible to ascertain 1,5 . 106 electron/hole pairs.
By the term "soft fault" there is understood a statistically non-permanent and mobile fault.
According to the invention there is provided a semiconductor integrated circuit containing integrated storage capacitors which are charged or discharged across electronic switches, wherein for the purpose of avoiding information storage faults caused by alpha particles, there are used integrated capacitors which do not form depletion layers with the substrate.
The technique is applicable to various devices, e.g. dynamic RAMs or other chargecontrolled switching circuits, such as bucketbrigade circuits, especially such ones with reduced circuit dimensions where the number of charge carriers required for storing the information, becomes always smaller as the dimensions become smaller, so that the probability of a soft fault being produced by an ionizing alpha particle increases as the integration density increases.
The invention will now be explained with reference to Figs. 1 to 6 of the accompanying drawings, in which:
Figures 1 and 2 demonstrate the soft-fault effect upon a bit line shown in a partly sectional representation, applied to a floating potential,
Figures 3 and 4 are used to explain the involved soft-fault effect upon a storage capacitor shown in a corresponding partly sectional representation,
Figure 5, in a corresponding partly sectional representation, shows the storage capacitor of a storage (memory) cell, and
Figure 6, in a partly sectional representation, shows a preferred type of structure of a bit line of a storage (memory) cell.
Figs. 1 and 2 illustrate the effect of alpha particles upon a non-charged storage capacitor having a depletion layer 9 and which, in
Fig. 1, is shown at the moment of being struck by an alpha particle, while Fig. 2 shows the charged capacitor after the alpha particle has struck. The storage capacitor is usually designed in accordance with the known MlS-technology, with the electrode 7 consisting of either a metal layer or of a layer of polycrystalline silicon deposited on a thin oxide layer 8, being arranged on the surface of the substrate 4. The charge-carrier pairs shown on both sides of the track 11 of the alpha-particle stroke are moved in accordance with their polarity within the field of the depletion layer 9 in the direction as indicated by the arrows attached to the mobile charge carriers.Following the alpha-particle stroke, and owing to a developing surface charge, there is formed the inversion layer 9' as shown in Fig. 2, causing a substrate current 1 0 to flow.
Semiconductor integrated circuits of the type described herein use bit lines which, by forming a pn-junction, are diffused in a stripshaped manner into the semiconductor substrate 4 and which, together with the drain regions of the field-effect transistors, are combined to form one region, while the source regions are each applied to one storage electrode. One such semiconductor storage (memory) cell is shown partly in a sectional representation and vertically in relation to a drainbit line, in Figs. 3 and 4, with Fig. 3 showing the state at the moment of the alpha-particle stroke 11, while Fig. 4 shows the state thereafter. Below the drain-bit line 12 there is formed the depletion layer 9, with per alphaparticle stroke a discharge of the bit line of about 300 mV having been measured. After the alpha particle has struck, the substrate current 10 flows again.
Accordingly, this substrate current 10 is caused by the carrier separation through the depletion layer, because substantially a recombination can no longer take place. Hence, in designing a semiconductor circuit of the kind involved, and in accordance with the teaching of the invention, depletion layers are possibly to be avoided completely, or are to be reduced to a minimum surface area.
Fig. 5, in a cross sectional view, shows the storage capacitor of a semiconductor integrated circuit in which the formation of a depletion layer in the semi-conductor substrate 4 is avoided completely. The storage capacitance as shown in Fig. 5 consists of two electrode layers 2, 2'; 3, of which the upper one may be divided in the way as shown in
Fig. 5. Between the two electrode layers there is arranged one dielectric layer 1. The lower electrode layer 3 is deposited on an insulating surface layer 13 of the substrate 4 and, for the purpose of avoiding the formation of a depletion layer, is either connected to the substrate 4 or applied to a corresponding potential.
The electrode layers 2, 2', 3 may consist either of a polycrystalline silicon or of a metal while the dielectric layer 1 may be designed to have the shape of a thin oxide layer.
Fig. 6, partly in a cross-sectional view, shows the possible structure of a bit line in a semiconductor integrated circuit. The bit line 5 which is either of metal or of polysilicon, is deposited on a thick oxide layer 6 and contacts the drain region 14 of an insulated-gate field-effect transistor whose source region is outside the drawing plane and connected to an electrode of a storage capacitor. The thickness of the thick oxide layer 6 is to be chosen thus as to be prevented from from depletion layers with the substrate 4 at maximum voltages. The injunction of the drain region 14 is to be dimensioned to have a small as possible surface area so as to keep the probability of an alpha-particle stroke as small as possible. The word line is connected to the gate electrode of the insulated-gate field-effect transistor.
From the foregoing it should be clear that the lowest sensitivity of an integrated circuit according to the invention will be obtained when both of the measures described with reference to Figs. 5 and 6 are taken.
Claims (4)
1. A semiconductor integrated circuit containing integrated storage capacitors which are charged or discharged across electronic switches, wherein for the purpose of avoiding information storage faults caused by alpha particles, there are used integrated capacitors which do not form depletion layers with the substrate.
2. A semiconductor integrated circuit as claimed in claim 1, wherein at least one integrated storage capacitor provided with electrode layers of which one electrode layer is arranged in an insulated manner on said substrate, and of which another electrode layer is arranged on a dielectric layer in register with the one electrode layer.
3. A semiconductor integrated circuit as claimed in claims 1 or 2, and provided with bit lines which are in connection with said substrate via a thick oxide layer.
4. A semiconductor integrated circuit substantially as described herein with reference to
Figs. 5 and 6 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19792912439 DE2912439A1 (en) | 1979-03-29 | 1979-03-29 | INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2045526A true GB2045526A (en) | 1980-10-29 |
Family
ID=6066777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8010299A Withdrawn GB2045526A (en) | 1979-03-29 | 1980-03-27 | Integrated circuit capacitors |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS55146958A (en) |
| DE (1) | DE2912439A1 (en) |
| FR (1) | FR2452790A1 (en) |
| GB (1) | GB2045526A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0033159A2 (en) * | 1980-01-29 | 1981-08-05 | Nec Corporation | Semiconductor device |
| EP0070026A2 (en) * | 1981-07-15 | 1983-01-19 | Siemens Aktiengesellschaft | Device for the reduction of alpha-radiation sensibility of integrated semiconductor memories |
| FR2526225A1 (en) * | 1982-04-30 | 1983-11-04 | Radiotechnique Compelec | METHOD FOR PRODUCING AN INTEGRATED CAPACITOR AND DEVICE THUS OBTAINED |
| FR2530077A1 (en) * | 1982-07-09 | 1984-01-13 | Radiotechnique Compelec | METHOD FOR PRODUCING INTEGRATED CAPACITORS IN A MICROELECTRONIC STRUCTURE |
| US5508881A (en) * | 1994-02-01 | 1996-04-16 | Quality Microcircuits Corporation | Capacitors and interconnect lines for use with integrated circuits |
| EP0893831A1 (en) * | 1997-07-23 | 1999-01-27 | STMicroelectronics S.r.l. | High voltage capacitor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797682A (en) * | 1980-12-10 | 1982-06-17 | Clarion Co Ltd | Variable capacitance device |
-
1979
- 1979-03-29 DE DE19792912439 patent/DE2912439A1/en not_active Withdrawn
-
1980
- 1980-03-27 GB GB8010299A patent/GB2045526A/en not_active Withdrawn
- 1980-03-28 JP JP3912580A patent/JPS55146958A/en active Pending
- 1980-03-28 FR FR8006953A patent/FR2452790A1/en active Granted
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0033159A2 (en) * | 1980-01-29 | 1981-08-05 | Nec Corporation | Semiconductor device |
| EP0033159A3 (en) * | 1980-01-29 | 1981-08-19 | Nec Corporation | Semiconductor device |
| EP0070026A2 (en) * | 1981-07-15 | 1983-01-19 | Siemens Aktiengesellschaft | Device for the reduction of alpha-radiation sensibility of integrated semiconductor memories |
| EP0070026A3 (en) * | 1981-07-15 | 1985-07-03 | Siemens Aktiengesellschaft | Device for the reduction of alpha-radiation sensibility of integrated semiconductor memories |
| FR2526225A1 (en) * | 1982-04-30 | 1983-11-04 | Radiotechnique Compelec | METHOD FOR PRODUCING AN INTEGRATED CAPACITOR AND DEVICE THUS OBTAINED |
| FR2530077A1 (en) * | 1982-07-09 | 1984-01-13 | Radiotechnique Compelec | METHOD FOR PRODUCING INTEGRATED CAPACITORS IN A MICROELECTRONIC STRUCTURE |
| EP0098671A1 (en) * | 1982-07-09 | 1984-01-18 | R.T.C. LA RADIOTECHNIQUE-COMPELEC Société anonyme dite: | Process for interinsulating metallic parts by anodic oxidation, and device obtained by this method |
| US5508881A (en) * | 1994-02-01 | 1996-04-16 | Quality Microcircuits Corporation | Capacitors and interconnect lines for use with integrated circuits |
| EP0893831A1 (en) * | 1997-07-23 | 1999-01-27 | STMicroelectronics S.r.l. | High voltage capacitor |
| US6188121B1 (en) | 1997-07-23 | 2001-02-13 | Sgs-Thomson Microelectronics S.R.L. | High voltage capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2452790B3 (en) | 1981-12-31 |
| FR2452790A1 (en) | 1980-10-24 |
| DE2912439A1 (en) | 1980-10-16 |
| JPS55146958A (en) | 1980-11-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |