US6188121B1 - High voltage capacitor - Google Patents
High voltage capacitor Download PDFInfo
- Publication number
- US6188121B1 US6188121B1 US09/119,115 US11911598A US6188121B1 US 6188121 B1 US6188121 B1 US 6188121B1 US 11911598 A US11911598 A US 11911598A US 6188121 B1 US6188121 B1 US 6188121B1
- Authority
- US
- United States
- Prior art keywords
- layer
- capacitor
- high voltage
- polycrystalline silicon
- voltage capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 68
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 11
- 230000015654 memory Effects 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Definitions
- This invention relates to a high voltage capacitor.
- the invention relates to a high voltage capacitor adapted to be integrated monolithically on a semiconductor substrate accommodating a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer.
- EPROMs, EEPROMs and FLASH EEPROMs all require high (12V) programming voltages that such thin oxides cannot withstand.
- a second and thicker (e.g. 20 to 30 nm) oxide has become necessary for high voltage transistors.
- These programming voltages must, in the instance of EEPROMs and FLASH EEPROMs, be generated internally from the external supply voltage by means of suitable circuits, known as voltage multipliers or charge pumps and based on the use of capacitors, which must be capable of withstanding the high voltages involved in the final stages of the circuit.
- capacitors can be formed between the polycrystalline silicon and a diffusion provided in the substrate, using the high voltage oxide as a dielectric.
- they have certain disadvantages, as follows:
- the diffusion which forms one of the capacitor electrodes is part of the standard processing flow for EEPROMs, but involves an additional masking step for FLASH EEPROM memories;
- one of the capacitor electrodes is connected to the substrate via a diode, which introduces limitations on the supply polarities.
- non-volatile memories of the EPROM, FLASH EEPROM and EEPROM types include two levels of polycrystalline silicon, separated by a dielectric, which lend themselves ideally for forming a capacitor with both electrodes floating.
- a limiting factor to the use, in integrated circuits of this kind, of capacitors formed between two levels of polysilicon is represented by the maximum voltage that the interpoly oxide can withstand.
- This oxide is usually quite thin (within the range of 15 to 20 nm), since it has to be used in memory cells.
- the efficiency of the memory cell is critically dependent on the coupling coefficient between the control gate and the floating gate, which is the better the thinner the interpoly dielectric, whose lower limit is only set by problems of faulty construction.
- forming thick and thin interpoly dielectrics simultaneously in the same device is a fairly complicated operation involving at least one masking step.
- the underlying technical problem of this invention is to enable the formation of a high voltage capacitor in a double polysilicon level, monolithically integratable on a semiconductor substrate without the addition of technological steps to the manufacturing process of the device to which the capacitor is integrated, thereby overcoming the aforementioned limitations of the prior art.
- Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.
- FIG. 1 shows a cross-section through a capacitor, integrated to a double polysilicon level structure, according to this invention.
- FIG. 2 is an equivalent electric diagram of the capacitor shown in FIG. 1 .
- FIG. 3 shows a cross-section through a second embodiment of an integrated capacitor, according to this invention.
- FIG. 4 shows a cross-section through a third embodiment of an integrated capacitor, according to this invention.
- FIG. 5 shows a cross-section through a fourth embodiment of an integrated capacitor, according to this invention.
- FIG. 6 is an equivalent electric diagram of the capacitor shown in FIG. 5 .
- the structure 1 comprises a semiconductor substrate 7 having a certain type of dopant, e.g., of the P type, and on which an isolation layer 2 of field oxide has been grown. It would also be possible to use a semiconductor substrate 7 of the N type.
- the isolation layer 2 alternatively could be a gate oxide, preferably the same as that used for the high voltage transistors.
- a first layer of polycrystalline silicon POLY 1 is deposited over the isolation layer 2 which has a portion 3 provided therein to form an intermediate plate of the capacitor 1 .
- a layer of interpoly dielectric 6 overlaid by a second layer of polycrystalline silicon POLY 2 .
- the interpoly dielectric may be a thermally grown oxide, or preferably a stack of thermal oxide, silicon nitride deposited by chemical vapor deposition (“CVD”) and an either thermal or deposited oxide known as an Oxide-Nitride-Oxide (“O.N.O.”) stack.
- CVD chemical vapor deposition
- O.N.O. Oxide-Nitride-Oxide
- the second layer POLY 2 comprises first 4 and second 5 portions which are structurally independent of and separated from each other.
- the first portion 4 includes a first contact terminal A
- the second portion 5 includes a second contact terminal B.
- These contact terminals are formed conventionally by appropriate metallizations carried out directly onto said second polysilicon layer.
- the contact area may be located within or without the capacitor.
- the contact metallizations can be provided by contact techniques using metals or alloys such as Al, Al—Si, Al—Si—Cu, but also by barrier or plug techniques, as are known to the skilled persons in the art.
- the integrated structure 1 has the features of a dual capacitor comprising a first C 1 and a second C 2 elementary capacitor.
- a first elementary capacitor C 1 defined by the first portion 4 of the layer POLY 2 and the portion 3 of the layer POLY 1 , which form the conductive plates, and by the interpoly oxide layer 6 forming the dielectric between these plates.
- a second elementary capacitor C 2 can be recognized which is defined by the second portion 5 of the layer POLY 2 and the portion 3 of the layer POLY 1 , which form the plates, with the interpoly oxide layer 6 providing the dielectric layer.
- the portion 3 of the layer POLY 2 is, therefore, a single plate shared by both elementary capacitors, C 1 and C 2 .
- FIG. 2 shows the equivalent circuit of the high voltage capacitor 1 shown in FIG. 1 . It can be seen that the elementary capacitors C 1 and C 2 are connected in series between the contact terminals A and B.
- FIG. 2 shows a first plate 4 contacted by the terminal A, the common plate 3 , and a second plate 5 contacted by the terminal B.
- the highest voltage that the resultant capacitor 1 can withstand is, therefore, given by the sum of the maximum voltages that the dielectric layers of the elementary capacitors C 1 and C 2 can withstand. Since both capacitors use, for a dielectric, the same layer of interpoly oxide 6 , the highest voltage that the oxide can withstand is practically double, since the electric field applied is split to the series of the two capacitors.
- C will be one half the capacitance of an individual elementary capacitor.
- C will be one half the capacitance of an individual elementary capacitor.
- Different designs of the capacitor structure, either with rectangular plates or concentric plates, are possible.
- the contacts on the two plates can be formed above the capacitor dielectric as shown in FIG. 1, it would also be possible to continue the two electrodes A and B onto the field oxide, outside the electrode of Poly 1 , and provide the contacts in this region.
- the capacitor 1 may also be formed, as shown in the example of FIG. 3, by reversing the two levels of polysilicon.
- the structure 1 of FIG. 3 comprises a semiconductor substrate 7 having a certain type of dopant, e.g., of the P type, on which an isolation layer of field oxide 2 has been grown.
- a first layer of polycrystalline silicon POLY 1 having first 4 and second 5 portions formed therein which are structurally independent of and isolated from each other.
- the first portion 4 includes a first contact terminal A
- the second portion 5 includes a second contact terminal B.
- a dielectric layer of interpoly 6 is deposited onto the first layer of polycrystalline silicon POLY 1 and overlaid by a second layer of polycrystalline silicon POLY 2 .
- the interpoly dielectric may be a thermally grown oxide or, preferably, a stack of thermal oxide, silicon nitride deposited by CVD and an either thermal or deposited oxide known as O.N.O.. Other combinations of thermal oxide, or CVD and nitride, are also viable.
- the second layer POLY 2 includes a portion 3 which forms an intermediate plate of the capacitor 1 .
- the integrated structure 1 is in the form of a double capacitor comprising first C 1 and second C 2 elementary capacitors.
- first elementary capacitor C 1 formed by the first portion 4 of the layer POLY 1 and the portion 3 of the layer POLY 2 , providing the conductive plates, and by the interpoly oxide layer 6 providing the dielectric between these plates.
- a second elementary capacitor C 2 is also identifiable which is formed by the second portion 5 of the layer POLY 1 and the portion 3 of the layer POLY 2 , both providing its plates, with the dielectric layer being provided by the interpoly oxide layer 6 .
- the portion 3 of the layer POLY 2 is, therefore, a plate shared by both elementary capacitors C 1 and C 2 .
- the portions 4 and 5 may be contacted in the Poly 1 directly or through contact areas in Poly 2 .
- the configuration of FIG. 3 has the advantage that the terminating electrodes, formed from the portions 4 , 5 and respective contacts A, B, are shielded from noise caused by any overlying metals.
- a further embodiment of the invention whereby the capacitive coupling of the two terminals A and B can be improved, consists of forming the capacitor 1 , with the common plate in Poly 2 , above a gate oxide area 9 , preferably at a high voltage, overlying a diffusion 8 of the opposite type from the substrate, as shown in FIG. 4.
- a condition is that the gate oxide 9 should have a comparable thickness to that of the interpoly dielectric 6 , or at least adequate to withstand one half of the total voltage applied to the capacitor.
- the diffusion 8 in the substrate functions as a further capacitor plate, thereby doubling the capacitance per unit area.
- FIG. 5 A further embodiment of the invention is shown in FIG. 5 .
- This embodiment can be of advantage where the specific capacitance of the capacitors formed between the polysilicon and the diffusion is to be increased using an interpoly dielectric which cannot withstand the full voltage.
- the capacitor is formed with the floating gate in POLY 2 , over a high voltage gate oxide 9 , itself overlying a diffusion that is here connected electrically to one 5 of the two plates 4 , 5 formed in POLY 1 .
- the overall capacitance will, therefore, result from the parallel of one capacitance POLY 1 -diffusion and the series of two capacitances between POLY 1 and POLY 2 , as illustrated by the equivalent electric diagram of FIG. 6 .
- this high voltage capacitor can be formed by any of the processes which provide for a double level of polysilicon, such as the CMOS processes for fabricating non-volatile memories. In such devices, high voltages must be handled for programming and erasing the memory cells.
- Such a capacitor can be integrated to all those devices which require the servicing of relatively high voltages with respect to the voltage supply to the devices.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97830384A EP0893831A1 (en) | 1997-07-23 | 1997-07-23 | High voltage capacitor |
EP97830384 | 1997-07-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
US6188121B1 true US6188121B1 (en) | 2001-02-13 |
Family
ID=8230730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/119,115 Expired - Lifetime US6188121B1 (en) | 1997-07-23 | 1998-07-20 | High voltage capacitor |
Country Status (2)
Country | Link |
---|---|
US (1) | US6188121B1 (en) |
EP (1) | EP0893831A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6597562B1 (en) * | 2002-07-11 | 2003-07-22 | Acer Laboratories, Inc. | Electrically polar integrated capacitor and method of making same |
US20050280060A1 (en) * | 2004-06-22 | 2005-12-22 | Werner Juengling | Concentric or nested container capacitor structure for integrated cicuits |
US20130270675A1 (en) * | 2011-10-01 | 2013-10-17 | Michael A. Childs | On-chip capacitors and methods of assembling same |
CN107799519A (en) * | 2017-11-20 | 2018-03-13 | 荣湃半导体(上海)有限公司 | A kind of high_voltage isolation circuit |
US20190206981A1 (en) * | 2017-12-29 | 2019-07-04 | Texas Instruments Incorporated | High voltage isolation structure and method |
US20190252331A1 (en) * | 2018-02-13 | 2019-08-15 | Voltron Microelectronics Corp. | High-voltage capacitor structure and digital isolation apparatus |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2189627B1 (en) * | 2001-02-22 | 2004-10-16 | Prototal, S.L. | ELECTRICAL CONDENSER |
DE10222764B4 (en) * | 2002-05-15 | 2011-06-01 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Semiconductor varactor and thus constructed oscillator |
CN104425486A (en) * | 2013-08-30 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Double-spliced capacitor and manufacturing method thereof |
EP4120377A1 (en) * | 2021-07-16 | 2023-01-18 | Murata Manufacturing Co., Ltd. | Diamond-based capacitor structure |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2341177A1 (en) | 1976-02-12 | 1977-09-09 | Philips Nv | SEMICONDUCTOR DEVICE, USED FOR STORING AND READING INFORMATION |
JPS5440043A (en) * | 1977-09-05 | 1979-03-28 | Toshiba Corp | Semiconductor memory |
GB2045526A (en) | 1979-03-29 | 1980-10-29 | Itt | Integrated circuit capacitors |
US4314265A (en) * | 1979-01-24 | 1982-02-02 | Xicor, Inc. | Dense nonvolatile electrically-alterable memory devices with four layer electrodes |
JPS58209165A (en) * | 1982-05-31 | 1983-12-06 | Toshiba Corp | Nonvolatile semiconductor memory storage |
US4527180A (en) * | 1983-01-31 | 1985-07-02 | Intel Corporation | MOS Voltage divider structure suitable for higher potential feedback regulation |
JPS6173367A (en) * | 1984-09-19 | 1986-04-15 | Hitachi Ltd | Semiconductor device |
US4768080A (en) * | 1984-12-07 | 1988-08-30 | Kabushiki Kaisha Toshiba | Semiconductor device having floating and control gates |
JPH02213159A (en) * | 1989-02-13 | 1990-08-24 | Mitsubishi Electric Corp | Capacitor |
US5111430A (en) * | 1989-06-22 | 1992-05-05 | Nippon Telegraph And Telephone Corporation | Non-volatile memory with hot carriers transmitted to floating gate through control gate |
JPH04164364A (en) * | 1990-10-29 | 1992-06-10 | Toshiba Corp | Semiconductor device |
US5166858A (en) | 1991-10-30 | 1992-11-24 | Xilinx, Inc. | Capacitor formed in three conductive layers |
GB2300969A (en) | 1995-05-16 | 1996-11-20 | Hyundai Electronics Ind | Flash EEPROM cell |
US5852311A (en) * | 1996-06-07 | 1998-12-22 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including capping layer contact holes |
-
1997
- 1997-07-23 EP EP97830384A patent/EP0893831A1/en not_active Withdrawn
-
1998
- 1998-07-20 US US09/119,115 patent/US6188121B1/en not_active Expired - Lifetime
Patent Citations (14)
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FR2341177A1 (en) | 1976-02-12 | 1977-09-09 | Philips Nv | SEMICONDUCTOR DEVICE, USED FOR STORING AND READING INFORMATION |
JPS5440043A (en) * | 1977-09-05 | 1979-03-28 | Toshiba Corp | Semiconductor memory |
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US4527180A (en) * | 1983-01-31 | 1985-07-02 | Intel Corporation | MOS Voltage divider structure suitable for higher potential feedback regulation |
JPS6173367A (en) * | 1984-09-19 | 1986-04-15 | Hitachi Ltd | Semiconductor device |
US4768080A (en) * | 1984-12-07 | 1988-08-30 | Kabushiki Kaisha Toshiba | Semiconductor device having floating and control gates |
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US5111430A (en) * | 1989-06-22 | 1992-05-05 | Nippon Telegraph And Telephone Corporation | Non-volatile memory with hot carriers transmitted to floating gate through control gate |
JPH04164364A (en) * | 1990-10-29 | 1992-06-10 | Toshiba Corp | Semiconductor device |
US5166858A (en) | 1991-10-30 | 1992-11-24 | Xilinx, Inc. | Capacitor formed in three conductive layers |
GB2300969A (en) | 1995-05-16 | 1996-11-20 | Hyundai Electronics Ind | Flash EEPROM cell |
US5852311A (en) * | 1996-06-07 | 1998-12-22 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including capping layer contact holes |
Non-Patent Citations (1)
Title |
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Nondestructive Readout 3 Dimensional Dual Insulator Memory, IBM Technical Disclosure Bulletin, vol. 17, No. 1, pp. 28-29, Jun. 1974. |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6597562B1 (en) * | 2002-07-11 | 2003-07-22 | Acer Laboratories, Inc. | Electrically polar integrated capacitor and method of making same |
US8017985B2 (en) | 2004-06-22 | 2011-09-13 | Micron Technology, Inc. | Concentric or nested container capacitor structure for integrated circuits |
US20060226465A1 (en) * | 2004-06-22 | 2006-10-12 | Werner Juengling | Concentric or nested container capacitor structure for integrated circuits |
US20060226496A1 (en) * | 2004-06-22 | 2006-10-12 | Werner Juengling | Concentric or nested container capacitor structure for integrated circuits |
US7807541B2 (en) | 2004-06-22 | 2010-10-05 | Micron Technology, Inc. | Concentric or nested container capacitor structure for integrated circuits |
US20100327336A1 (en) * | 2004-06-22 | 2010-12-30 | Micron Technology, Inc. | Concentric or Nested Container Capacitor Structure for Integrated Circuits |
US20050280060A1 (en) * | 2004-06-22 | 2005-12-22 | Werner Juengling | Concentric or nested container capacitor structure for integrated cicuits |
US8482046B2 (en) | 2004-06-22 | 2013-07-09 | Micron Technology, Inc. | Concentric or nested container capacitor structure for integrated circuits |
US20130270675A1 (en) * | 2011-10-01 | 2013-10-17 | Michael A. Childs | On-chip capacitors and methods of assembling same |
US9627312B2 (en) * | 2011-10-01 | 2017-04-18 | Intel Corporation | On-chip capacitors and methods of assembling same |
CN107799519A (en) * | 2017-11-20 | 2018-03-13 | 荣湃半导体(上海)有限公司 | A kind of high_voltage isolation circuit |
US20190206981A1 (en) * | 2017-12-29 | 2019-07-04 | Texas Instruments Incorporated | High voltage isolation structure and method |
US11222945B2 (en) * | 2017-12-29 | 2022-01-11 | Texas Instruments Incorporated | High voltage isolation structure and method |
US20190252331A1 (en) * | 2018-02-13 | 2019-08-15 | Voltron Microelectronics Corp. | High-voltage capacitor structure and digital isolation apparatus |
CN110164849A (en) * | 2018-02-13 | 2019-08-23 | 富创微电子有限公司 | High-voltage capacitor structure and digital isolating device |
Also Published As
Publication number | Publication date |
---|---|
EP0893831A1 (en) | 1999-01-27 |
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