CN107799519A - A kind of high_voltage isolation circuit - Google Patents

A kind of high_voltage isolation circuit Download PDF

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Publication number
CN107799519A
CN107799519A CN201711160626.9A CN201711160626A CN107799519A CN 107799519 A CN107799519 A CN 107799519A CN 201711160626 A CN201711160626 A CN 201711160626A CN 107799519 A CN107799519 A CN 107799519A
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Prior art keywords
sub
isolation
substrate
voltage
transformer
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CN201711160626.9A
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Chinese (zh)
Inventor
董志伟
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Rong Pai Semiconductor (shanghai) Co Ltd
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Rong Pai Semiconductor (shanghai) Co Ltd
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Priority to CN201711160626.9A priority Critical patent/CN107799519A/en
Publication of CN107799519A publication Critical patent/CN107799519A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The present invention provides a kind of high_voltage isolation electric capacity, wherein the high_voltage isolation electric capacity includes：The sub- isolation capacitance of N number of series connection, each sub- isolation capacitance includes positive pole and negative pole, and each sub- isolation capacitance is set over the substrate by the pole in its positive pole and negative pole, and another extremely away from the substrate in the positive pole and negative pole, wherein, N is the natural number more than 1.Isolation capacitance provided by the invention can significantly decrease the thickness of isolation capacitance, and higher isolation voltage can be realized by using existing maturation process.

Description

A kind of high_voltage isolation circuit
Technical field
The present invention relates to electronic applications, more particularly, to the setting of semiconductor chip mesohigh isolation circuit.
Background technology
In isolating chip, increase isolation voltage in general method is to increase the thickness of spacer medium (such as isolation capacitance) Degree, such as the ISO7720 of Texas Instruments (TI).In order to reach certain isolation voltage, the thickness of separation layer medium is normal Advise integrated circuit technology several times.And the increase of dielectric thickness can bring Railway Project：
1st, integrated circuit technology difficulty increase, unconventional integrated circuit technology, the exploitation week of integrated circuit technology are become Phase increases, R＆D costs increase；
2nd, the stress of medium, which can increase, causes defect increase in medium, reduces the life-span of medium, that is, the longevity of chip Life, also reduce the reliability of chip.
And if the thickness of electric capacity is too thin, then under high-pressure situations, circuit is easily breakdown, so as to influence the life-span of circuit And safety.
Thus, it is desirable to one kind can carry out solution to the problems described above with maturation process.
The content of the invention
It is present invention aim to address isolation capacitance thickness in the prior art thicker and can not be entered with existing maturation process The defects of row manufacture.
According to the first aspect of the invention, there is provided a kind of high_voltage isolation electric capacity, including：The sub- isolation capacitance of N number of series connection, often The individual sub- isolation capacitance includes positive pole and negative pole, and each sub- isolation capacitance is set by the pole in its positive pole and negative pole Over the substrate, it is another extremely away from the substrate in the positive pole and negative pole, wherein, N is the natural number more than 1.
According to an embodiment of the invention, wherein, there is specific range between each adjacent sub- isolation capacitance, to keep away Exempt to puncture between adjacent sub- isolation capacitance.
According to an embodiment of the invention, wherein, the positive pole and negative polarity of adjacent sub- isolation capacitance are alternately set Put over the substrate.
According to an embodiment of the invention, wherein, the positive pole and negative polarity of adjacent sub- isolation capacitance are set in the same manner Put over the substrate.
According to an embodiment of the invention, wherein, N is odd number.
According to an embodiment of the invention, wherein, N is even number.
According to an embodiment of the invention, wherein, N is 2-6.
According to an embodiment of the invention, wherein, the voltage of N number of sub- isolation capacitance is equal.
According to an embodiment of the invention, wherein, the substrate is SiO2, or growth is on a semiconductor substrate SiO2。
According to a second aspect of the present invention, there is provided a kind of high voltage isolating transformer, including：The sub- transformer of N number of series connection, each Sub- transformer includes inductive primary and inductive secondary, each sub- transformer by its inductive primary and time An inductance coil in level inductance coil is set over the substrate, and in the inductive primary and inductive secondary Another inductance coil away from the substrate, wherein, N is natural number more than 1.
According to an embodiment of the invention, wherein, there is specific range between each adjacent sub- transformer, to avoid Puncture between adjacent sub- transformer.
According to an embodiment of the invention, wherein, the inductive primary and secondary inductance line of adjacent sub- transformer Circle is alternately located on the substrate.
According to an embodiment of the invention, wherein, one in the inductive primary and inductive secondary Inductance coil is set over the substrate by two parallel metal levels.
According to an embodiment of the invention, wherein, it is another in the inductive primary and inductive secondary Individual inductance coil is arranged far from two parallel metal layers of the substrate.
According to an embodiment of the invention, wherein, N is odd number.
According to an embodiment of the invention, wherein, N is even number.
According to an embodiment of the invention, wherein, N 2-6.
According to an embodiment of the invention, wherein, the isolation voltage phase of the transformer of N number of sub- isolation capacitance Deng.
According to an embodiment of the invention, wherein, the substrate is SiO2, or growth is on a semiconductor substrate SiO2。
Isolation circuit provided by the invention can significantly decrease the thickness of isolation circuit, and can be by using existing Maturation process realize higher isolation voltage.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 shows the schematic diagram of the high_voltage isolation electric capacity according to one embodiment of the present invention；
Fig. 2 shows the schematic diagram of the high_voltage isolation electric capacity according to another embodiment of the invention；
Fig. 3 shows the situation that sub- isolation capacitance is even number (2)；
Fig. 4 shows the schematic diagram of the high_voltage isolation electric capacity according to another embodiment of the invention；
Fig. 5 shows the side view of the high voltage isolating transformer according to another embodiment of the invention；
Fig. 6 shows the side view of the high voltage isolating transformer according to further embodiment of the present invention；
Fig. 7 shows the schematic diagram of the exemplary inductance coil according to one embodiment of the present invention；And
Fig. 8 shows the set-up mode of the inductance coil according to one embodiment of the present invention.
Embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although the disclosure is shown in accompanying drawing Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here Limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure Completely it is communicated to those skilled in the art.
Fig. 1 shows the schematic diagram of the high_voltage isolation electric capacity according to one embodiment of the present invention.
As shown in figure 1, high_voltage isolation circuit provided by the invention includes the sub- isolation capacitance of 3 series connection, i.e., such as Fig. 1 institutes The first sub- isolation capacitance, the second sub- isolation capacitance and the 3rd sub- isolation capacitance shown；Each sub- isolation capacitance includes positive pole (+) and negative pole (-), every sub- isolation capacitance are set over the substrate by the pole in its positive pole and negative pole, and it is described just It is another extremely away from the substrate in pole and negative pole.
It is to be appreciated that although showing 3 sub- isolation capacitances in Fig. 1, the positive pole and negative pole of adjacent sub- isolation capacitance Set over the substrate alternating polarity.But it is to be appreciated that this is only an example, the present invention can be any amount Sub- isolation capacitance, such as 2,4,5,6 etc..
In Fig. 1, using total isolation voltage as 9kV, using 3 sub- isolation capacitances, the isolation electricity of every sub- isolation capacitance Press to be described exemplified by 3kV.As shown in figure 1, the negative or positive electrode in 3 sub- isolation capacitances is located on sub- substrate, first Positive pole (+) connection 9kV high pressures of sub- isolation capacitance, its negative pole (-) are connected to the positive pole (+) of the second sub- isolation capacitance, thus, warp Cross after the first sub- isolation capacitance, the negative pole (-) of the negative pole (-) of the first sub- isolation capacitance and the second sub- isolation capacitance is 6kV. Further, the negative pole (-) of the second sub- isolation capacitance is connected with the positive pole (+) of the 3rd sub- isolation capacitance, thus, by the second son After isolation capacitance, the negative pole (-) of the second sub- isolation capacitance and the positive pole (+) of the 3rd sub- isolation capacitance are 3kV.And by the After three sub- isolation capacitances, negative pole (-) voltage of the 3rd sub- isolation capacitance is 0kV.
In traditional technical scheme, if to carry out same voltage isolation (such as 9kV), then need it is larger every It is together in series in an overlapping fashion from electric capacity or by some less isolation capacitances, for example, it is desired to the isolation with three times thickness Medium is realized.And this can not be realized with existing ripe technique.Further, this mode also will inevitably be led The thickness of chip is caused to increase severely.And in the present invention, all sub- isolation capacitances are attached to by a pole (positive pole or negative pole) note Substrate surface, the increase of chip thickness will not be caused, therefore can be implemented using existing ripe technique, so as to significantly reduce Cost, improve system reliability.
Further, as can be seen that the positive pole (+) and second of the first sub- isolation capacitance from the isolation capacitance shown in Fig. 1 About 6kV voltage difference between the negative pole (-) of sub- isolation capacitance be present, therefore, if the first sub- isolation capacitance is isolated with the second son The distance between electric capacity is too small, then therebetween may be breakdown, it is therefore preferred that between each adjacent sub- isolation capacitance With specific range, to avoid puncturing between adjacent sub- isolation capacitance.The distance generally depends on adjacent sub- isolation capacitance Between maximum voltage difference, higher voltage, then need bigger distance, thus can increase needed for substrate area.For 6kV Voltage difference, based on specific integrated circuit technology, the distance can be 100 microns.
Fig. 2 shows the schematic diagram of the high_voltage isolation electric capacity according to another embodiment of the invention.
According to an embodiment of the invention, more sub- isolation capacitances set can also with the difference shown in Fig. 1, and It is that adjacent sub- isolation capacitance can be uniformly set on substrate with polarity.For example, as shown in Fig. 2 first and second can make it that Upward, negative pole is towards substrate direction for the sub- equal positive pole of isolation capacitance.In the case, the first sub- isolation capacitance isolates electricity with the second son The connection of appearance needs line to be upwardly extended from substrate surface, and this causes the complexity of line to increase.But on the other hand, it is such a Set-up mode make it that smaller (such as the voltage difference between adjacent sub- isolating capacitor is the voltage difference between adjacent sub- isolation capacitance 3kV) therefore the distance between adjacent sub- isolation capacitance can be reduced, for example, distance can be reduced to original half, (50 is micro- Rice).
Therefore, as described above as can be seen that according to the embodiment of the present invention, the positive pole of adjacent sub- isolation capacitance and Negative pole can be arranged on substrate with opposite polarity.For example, when sub- isolation capacitance positive pole upward, negative pole (direction down Substrate) when, for positive pole down, negative pole is upward for its adjacent sub- isolation capacitance.Thus the wiring for circuit board produces larger It is convenient, but chip area may increase.According to another embodiment of the invention, the positive pole and negative pole of adjacent sub- isolation capacitance can It is uniformly set with polarity on substrate.For example, when sub- isolation capacitance positive pole upward, negative pole is down (towards substrate) When, its adjacent sub- isolation capacitance also for positive pole upward, negative pole is down.Although thus the wiring for circuit board is inconvenient, But it can effectively reduce chip area.
For the quantity of sub- isolating capacitor, there may be two kinds of situations of odd and even number, figures 1 and 2 show that son every From the situation that electric capacity is odd number, the situation that sub- isolation capacitance is even number is described below.
Fig. 3 shows the situation that sub- isolation capacitance is even number (2).As shown in Fig. 2 for 9kV voltage, when setting two During individual sub- isolation capacitance, every sub- isolation capacitance is required for 4.5kV isolation voltage, therefore adjacent two sub- isolation capacitances are most Big voltage difference reaches 9kV.As described above, in order to avoid it is breakdown between two sub- isolation capacitances, it is necessary to increase two sons every From the distance between electric capacity, this obviously increases the area needed for substrate.
On the other hand, it is thicker relative to the sub- isolation capacitance that isolation voltage is 3kV, 4.5kV isolation capacitance needs Spacer medium and more preferable manufacturing process.
Area when laying electric capacity to reduce needed for substrate, can be by the way of as shown in Figure 2, i.e. so that adjacent The polarity of sub- isolation capacitance is laid on substrate in the same manner.
Fig. 4 shows the schematic diagram of the high_voltage isolation electric capacity according to another embodiment of the invention.
As shown in figure 4, for 9kV voltage, when setting two sub- isolation capacitances, every sub- isolation capacitance is required for 4.5kV isolation voltage, unlike Fig. 3, the setting shown in Fig. 4 causes the maximum voltage of the sub- isolation capacitance of adjacent two Difference is 4.5kV.Set-up mode compared to Fig. 3, this can significantly decrease the distance between adjacent sub- isolating capacitor, but generation Valency is complex connection mode.
Certainly, for 4 sub- isolation capacitances, the isolation voltage needed for every sub- isolation capacitance will substantially reduce (drop Low is 2.25kV), the voltage difference between adjacent two sub- isolation capacitances is 4.5kV, accordingly, with respect to 3 sub- isolation capacitances It has advantage for device.
It is therefore preferred that the present invention uses 3,4 or 5 sub- isolation capacitances.It is to be appreciated that although from principle The quantity of upper sub- isolation capacitance can infinitely increase, and corresponding ceiling voltage (9kV as shown in Figure 1) can infinitely increase Add, but the increase of highest isolation voltage certainly will need to cause the increase of the thickness of substrate, because higher isolation voltage even has The substrate may be punctured.To those skilled in the art, can synthetically consider to connect up difficulty, chip area, sub- isolation Capacitors count etc., so as to design required chip.
According to an embodiment of the invention, although fig 1 illustrate that the isolation voltage of every sub- isolation capacitance is 3kV, But the isolation voltage of every sub- isolation capacitance can also be different, for example, for 9kV total isolation voltage, three sons The isolation voltage of isolation capacitance can be respectively 2kV, 4kV and 3kV.But go out from the angle of batch micro operations and the stability of a system Hair, the isolation voltage of every sub- isolation capacitance is preferably equal.
The substrate is SiO2, or the SiO of growth on a semiconductor substrate2, or the lining of any other suitable material Bottom.
The situation of electric capacity is the foregoing described, describes the situation of inductance below.
Fig. 5 shows the side view of the high voltage isolating transformer according to another embodiment of the invention.
As shown in figure 5, the high voltage isolating transformer includes：The sub- transformer of 2 series connection, i.e., the first sub- transformer and second Sub- transformer, every sub- transformer include inductive primary and inductive secondary, and every sub- transformer passes through its primary electrical The inductance coil felt in coil and inductive secondary is set over the substrate, and the inductive primary and secondary Another inductance coil in inductance coil is away from the substrate.In Figure 5, the inductive secondary of the first sub- transformer is set On substrate, and the inductive primary of the first sub- transformer is away from the substrate, in the primary inductance line of the first sub- transformer The first isolation voltage (being, for example, 3kV) is formed between circle and inductive secondary；The inductive primary of second sub- transformer is set Put on substrate, and the inductive secondary of the second sub- transformer is away from the substrate, in the primary inductance of the second sub- transformer The second isolation voltage (being, for example, 3kV) is formed between coil and inductive secondary；So as to which total isolation voltage is the first isolation Voltage and the second isolation voltage sum (being, for example, 6kV).
The situation of two sub- transformers is schematically illustrated in Fig. 5, it will be appreciated by those skilled in the art that can With using more sub- transformers, such as 3-6.
From figure 5 it can be seen that multiple transformers are set to make it possible to produce using relatively thin thickness along substrate surface Raw higher isolation voltage, so as to reduce chip volume, lift integrated level.
As capacitance kind, there is specific range between each adjacent sub- transformer, to avoid between adjacent sub- transformer Puncture.Distance can be adjusted according to the voltage of reality.In case of shown in Fig. 5, adjacent sub- transformer it Between maximum voltage difference be 6kV, thus, it is desirable to have corresponding distance to ensure under 6kV voltage difference, adjacent sub- transformer it Between will not puncture.
Although two sub- transformers are shown in Fig. 5, and the inductive primary and secondary inductance of adjacent sub- transformer Coil is alternately located on substrate, it will be appreciated by those skilled in the art that the quantity of sub- transformer can also be it He, and the inductive primary of adjacent sub- transformer and inductive secondary are uniformly set over the substrate.
Fig. 6 shows the side view of the high voltage isolating transformer according to further embodiment of the present invention.
As shown in fig. 6, the inductive secondary of the first sub- transformer and the inductive secondary of the second sub- transformer are all provided with Put on substrate, and the inductive primary of the first sub- transformer and the inductive primary of the second sub- transformer are away from the lining Bottom is set.Therefore, in order to the inductive secondary of the first sub- transformer is connected with the inductive primary of the second sub- transformer Get up, it is necessary to using complex line, i.e. the line can not be laid along substrate, so as to the complexity of increased line Degree.But in the embodiment shown in fig. 6, the voltage difference between adjacent sub- transformer is smaller, such as compared with Fig. 5, the electricity Pressure difference narrows down to 3kV from 6kV.Because the voltage told somebody what one's real intentions are is less susceptible to puncture, thus can reduce adjacent sub- transformer it Between distance, so as to reduce chip area.
Fig. 7 shows the schematic diagram of the exemplary inductance coil according to one embodiment of the present invention.
As shown in fig. 7, coil employs spiral canoe, the coil of this mode is substantially at a plane It is interior, so as to reduce the thickness of coil, and further reduce the demand to chip space.
Inductance coil shown in Fig. 7 can have two taps, i.e. the tap in hub of a spool and in coil outermost Tap, tap can connect the positive pole and negative pole of power supply, so as to produce electric current.
It is to be appreciated that although spiral shape shown in Fig. 7 is round screw thread structure but it is also possible to be other shapes, example Such as rectangle, ellipse or any other rule or irregular shape.
Fig. 8 shows the set-up mode of the inductance coil according to one embodiment of the present invention.
As shown in figure 8, coil is arranged between two parallel metal levels (the first metal layer and second metal layer), as above Described, there are two taps in coil, such as the first tap and the second tap, the first tap are for example connected to the first metal layer, the Two taps are for example connected to second metal layer.Coil shown in Fig. 8 can be primary coil or secondary coil, line Circle can be arranged in second metal layer as shown in Figure 8, can also be set on the first metal layer, or can also be arranged on the One and second metal layer on.The coil can be arranged on substrate by the first and second metal levels, can also be arranged far from Substrate this first and/or second metal layer on.
The connection terminal being connected with external circuit or pin (pad) can be formed at metal level and the tie point of tap, with The convenient connection with external electrical device.
It is to be appreciated that although the inductance coil shown in Fig. 7 and Fig. 8 and the first metal layer and/or second metal layer It is independent, but the inductance coil in Fig. 7 and Fig. 8 is not meant to inductance coil merely for the sake of explanation and the purpose of example It is inevitable to be entwined independently of the first metal layer and/or second metal layer.In practice, can by the first metal layer and/ Or second metal layer is etched and obtains the inductance coil.
For the facilities of the sub- transformer of other quantity, the set-up mode for being referred to Fig. 5 and Fig. 6 is extended, Therefore will not be described in further detail here.
The quantity of high voltage isolating transformer can be odd number or even number, and this will be required and actual situation according to specific Selected.For example, situations such as being arranged according to the isolation voltage of the area of chip, total voltage, every sub- transformer come The quantity of specifically chosen required sub- transformer.
Further, in the case of using more sub- transformers, the isolation voltage of every sub- transformer is preferably Equal, but this is not construed as limiting to technical scheme, and those skilled in the art can also adopt according to the actual requirements With the different sub- transformer of isolation voltage.
Similarly, the substrate above for high voltage isolating transformer can be SiO2, or it is grown in semiconductor lining SiO on bottom2, or the substrate of any other suitable material.
It should be noted that the present invention will be described rather than limits the invention for above-described embodiment, and ability Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims, Any reference symbol between bracket should not be configured to limitations on claims.Word "comprising" does not exclude the presence of not Element or step listed in the claims.Word "a" or "an" before element does not exclude the presence of multiple such Element.The present invention can be by means of including the hardware of some different elements and being come by means of properly programmed computer real It is existing.In if the unit claim of equipment for drying is listed, several in these devices can be by same hardware branch To embody.The use of word first, second, and third does not indicate that any order.

Claims (19)

1. a kind of high_voltage isolation electric capacity, including：The sub- isolation capacitance of N number of series connection, each sub- isolation capacitance include positive pole and Negative pole, each sub- isolation capacitance are set over the substrate by the pole in its positive pole and negative pole, and the positive pole and It is another extremely away from the substrate in negative pole, wherein, N is the natural number more than 1.
2. high_voltage isolation electric capacity according to claim 1, wherein, have between each adjacent sub- isolation capacitance it is specific away from From to avoid puncturing between adjacent sub- isolation capacitance.
3. high_voltage isolation electric capacity according to claim 1, wherein, positive pole and the negative polarity alternating of adjacent sub- isolation capacitance Ground is set over the substrate.
4. high_voltage isolation electric capacity according to claim 1, wherein, the positive pole of adjacent sub- isolation capacitance is identical with negative polarity Ground is set over the substrate.
5. high_voltage isolation electric capacity according to claim 1, wherein, N is odd number.
6. high_voltage isolation electric capacity according to claim 1, wherein, N is even number.
7. high_voltage isolation electric capacity according to claim 1, wherein, N is 2-6.
8. high_voltage isolation electric capacity according to claim 1, wherein, the voltage of N number of sub- isolation capacitance is equal.
9. high_voltage isolation electric capacity according to claim 1, wherein, the substrate is SiO2, or it is grown in semiconductor lining SiO on bottom2。
10. a kind of high voltage isolating transformer, including：The sub- transformer of N number of series connection, every sub- transformer include inductive primary And inductive secondary, each sub- transformer pass through an inductor wire in its inductive primary and inductive secondary Circle is set over the substrate, and another inductance coil in the inductive primary and inductive secondary is away from described Substrate, wherein, N is the natural number more than 1.
11. high voltage isolating transformer according to claim 10, wherein, have between each adjacent sub- transformer it is specific away from From to avoid puncturing between adjacent sub- transformer.
12. high voltage isolating transformer according to claim 10, wherein, the inductive primary of adjacent sub- transformer and time Level inductance coil is alternately located on the substrate.
13. high voltage isolating transformer according to claim 10, wherein, the inductive primary and inductive secondary In an inductance coil set over the substrate by two parallel metal levels.
14. high voltage isolating transformer according to claim 10, wherein, the inductive primary and inductive secondary In another inductance coil be arranged far from two parallel metal layers of the substrate.
15. high voltage isolating transformer according to claim 10, wherein, N is odd number.
16. high voltage isolating transformer according to claim 10, wherein, N is even number.
17. high voltage isolating transformer according to claim 10, wherein, N 2-6.
18. high voltage isolating transformer according to claim 10, wherein, the transformer of N number of sub- isolation capacitance every Ionization voltage is equal.
19. high voltage isolating transformer according to claim 10, wherein, the substrate is SiO2, or be grown in and partly lead SiO on body substrate2。
CN201711160626.9A 2017-11-20 2017-11-20 A kind of high_voltage isolation circuit Pending CN107799519A (en)

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