DE2912439A1 - INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY - Google Patents

INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY

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Publication number
DE2912439A1
DE2912439A1 DE19792912439 DE2912439A DE2912439A1 DE 2912439 A1 DE2912439 A1 DE 2912439A1 DE 19792912439 DE19792912439 DE 19792912439 DE 2912439 A DE2912439 A DE 2912439A DE 2912439 A1 DE2912439 A1 DE 2912439A1
Authority
DE
Germany
Prior art keywords
integrated
semiconductor circuit
substrate
storage capacity
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19792912439
Other languages
German (de)
Inventor
Hans Prof Dipl Phys Reiner
Dieter Dipl Phys Dr Stroehle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Original Assignee
Standard Elektrik Lorenz AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Elektrik Lorenz AG filed Critical Standard Elektrik Lorenz AG
Priority to DE19792912439 priority Critical patent/DE2912439A1/en
Priority to GB8010299A priority patent/GB2045526A/en
Priority to FR8006953A priority patent/FR2452790A1/en
Priority to JP3912580A priority patent/JPS55146958A/en
Publication of DE2912439A1 publication Critical patent/DE2912439A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G11C19/186—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

H.Reiner et al 34-1 Fl 997H. Reiner et al 34-1 Fl 997

Integrierter Halbleiterschaltkreis mit integriertenIntegrated semiconductor circuit with integrated

SpeicherkapazitätenStorage capacities

Bei der Untersuchung der Empfindlichkeit von dynamischen 16 K RAMs gegen Alpha-Teilchen.welche in besonderen Strukturen der Speicher sogenannte Softfehler erzeugen können, wurden die die Verarmungsschichten (bei N-Kanaltechnologie) im Substrat bildenden elektrischen Felder der Elektron/Loch-Paare erkannt. Ohne die Ladungstrennung durch diese Felder rekombinieren die in einem engen Kanal um die Spur der Alpha-Teilchen erzeugten Elektron/Loch-Paare und es kann keine Umladung von ladungsempfindlichen Strukturen erfolgen. Pro Alpha-Teilchen-Einschlag konnten 1,5 · 10 Elektron/Loch-Paare ermittelt werden.When investigating the sensitivity of dynamic 16K RAMs to alpha particles. Which in particular Structures of the memory can generate so-called soft errors, the depletion layers (with N-channel technology) detected in the substrate forming electric fields of the electron / hole pairs. Without the charge separation through these fields, they recombine into one narrow channel around the track of the alpha particles generated electron / hole pairs and there can be no charge reversal charge-sensitive structures take place. Per alpha particle impact 1.5 · 10 6 electron / hole pairs could be determined.

Unter einem Softfehler wird ein statistisch nichtbleibender und nicht ortsgebundener Fehler verstanden.A soft error is understood to be a statistically non-permanent and non-location-related error.

Die Erfindung betrifft einen integrierten Halbleiterschaltkreis mit integrierten Speicherkapazitäten gemäß dem Oberbegriff des Anspruchs 1.The invention relates to an integrated semiconductor circuit with integrated storage capacitances according to the preamble of claim 1.

Aufgabe der Erfindung ist die Verhinderung von Softfehlern der genannten Art in einem Halbleiterschaltkreis mit integrierten Speicherkapazitäten, welche über elektronische Schalter gealden und entladen werden, beispielsweise wie dynamische RAMs oder anderen ladungsgesteuerten Schaltkreisen wie Eimerkettenschaltungen, insbesondere in solchen mit verkleinerten Schaltungsdimensionen, da dort die Zahl der zur Informationspeicherung notwendigenLadungsträger mit kleiner werdenden AbmessungenThe object of the invention is to prevent soft errors of the type mentioned in a semiconductor circuit with integrated Storage capacities that are balanced and discharged via electronic switches, for example such as dynamic RAMs or other charge controlled circuits such as bucket chain circuits, in particular in those with reduced circuit dimensions, since there the number of charge carriers necessary for information storage with diminishing dimensions

030042/0079030042/0079

H.Reiner et al 34-1 Fl 997H. Reiner et al 34-1 Fl 997

immer kleiner wird, so daß die Wahrscheinlichkeit der Erzeugung eines Softfehlers durch ein ionisierendes Alpha-Teilchen mit zunehmender Integrationsdichte ansteigt.
5becomes smaller and smaller, so that the probability of the generation of a soft error by an ionizing alpha particle increases with increasing integration density.
5

Diese Aufgabe wird durch die im kennzeichnenden Teil des Anspruchs 1 genannte Ausbildung gelöst.This object is achieved by the training mentioned in the characterizing part of claim 1.

Die Erfindung wird im folgenden anhand der Zeichnungen 10 erläutert,The invention is explained below with reference to the drawings 10,

deren Fig. 1 undtheir Fig. 1 and

zur Erläuterung des betroffenen Softeffektes auf eine in Teilschnittansicht dargestellte Bitleitung an schwebendem Potential dienen,to explain the affected soft effect on a partial sectional view bit line shown serve at floating potential,

deren Fig. 3 undtheir Fig. 3 and

zur Erläuterung des betroffenen Softeffektes auf einen in entsprechender Teilschnittansicht gezeigten Speicherkondensator herangezogen wird,to explain the affected soft effect to a corresponding Partial sectional view shown storage capacitor is used,

deren Fig.whose fig.

deren Fig.whose fig.

in entsprechender Teilschnittansicht eine gemäß dem Erfindungsgedanken ausgebildete Speicherkapazität einer Speicherzelle zeigt undin a corresponding partial sectional view, a storage capacity designed according to the concept of the invention a memory cell shows and

in Teilschnittansicht einen bevorzugten Aufbau einer Bitleitung einer Speicherzelle nach der Erfindung betrifft.a partial sectional view of a preferred construction of a bit line relates to a memory cell according to the invention.

030042/0079030042/0079

- 5 H.Reiner et al 34-1 Fl 997- 5 H. Reiner et al 34-1 Fl 997

Die Fig. 1 und 2 veranschaulichen den Effekt von Alpha-Teilchen auf einen ungeladenen Speicherkondendator mit einer Verarmungsschicht 9, der in Fig. 1 zur Zeit des Einschlags eines Alpha-Teilchens dargestellt ist, während die Fig. 2 den geladenen Kondensator nach dem Alpha-Teilchen-Einschlag zeigt. Der Speichertransistor wird üblicherweise als MIS-Kapazität ausgebildet mit der Elektrode 7 aus einer Metallschicht oder aus einer Schicht aus polykristallinem Silicium auf einer Dünnoxidschicht 8 auf der Oberfläche des Substrats 4. Die neben der Bahn 11 des Alpha-Teilchen-Einschlags dargestellten Ladungsträgerpaare werden entsprechend ihrer Polarität in Richtung der an die beweglichen Ladungsträger angebrachten Pfeile im Feld der Verarmungsschicht 9 bewegt. Nach dem Alpha-Teilchen-Einschlag bildet sich aufgrund einer sich ausbildenden Oberflächenladung die Inversionsschicht 91 gemäß der Fig. 2 aus, wobei ein Substratstrom 10 fließt.1 and 2 illustrate the effect of alpha particles on an uncharged storage capacitor with a depletion layer 9, which is shown in FIG. 1 at the time of the impact of an alpha particle, while FIG. 2 shows the charged capacitor after the alpha Shows particle impact. The memory transistor is usually designed as an MIS capacitance with the electrode 7 made of a metal layer or a layer of polycrystalline silicon on a thin oxide layer 8 on the surface of the substrate 4 Polarity moved in the direction of the arrows attached to the movable charge carriers in the field of the depletion layer 9. After the alpha particle impact, the inversion layer 9 1 according to FIG. 2 is formed due to a surface charge that forms, with a substrate current 10 flowing.

Bei dem integrierten Halbleiterschalikreis der von der Erfindung betroffenen Art werden oft Bitleitungen verwendet, welche streifenförmig unter Bildung eines pn-Obergangs in das Halbleitersubstrat 4 eindiffundiert werden und welche mit den Drain-Zonen der Feldeffekttransistoren zu einer Zone zusammengefaßt worden sind, während die Source-Zonenan je einer Speicherelektrode liegen. Eine solche Halbleiterspeicherzelle zeigen ausschnittweise im Schnitt senkrecht zum Verlauf einer Drain-Bit-Leitung die Fig. 3 und 4, wobei die Fig. 3 den Zustand zur Zeit des Alpha-Teilchen-Einschlags 11 und die Fig. 4 den Zustand danach veranschaulichen. Unter der Drain-Bit-Leitung 12 bildet sich die Verarmungsschicht 9 aus, wobei pro Alpha-Teilchen-Einschlag eine Entladung der Bitleitung von etwa 300 mV gemessenIn the case of the integrated semiconductor circuit of the In accordance with the invention, bit lines are often used, which are strip-shaped to form a pn junction are diffused into the semiconductor substrate 4 and which with the drain zones of the field effect transistors have been combined to form a zone, while the source zones each have a storage electrode lie. Show such a semiconductor memory cell FIGS. 3 and 4 partially in section perpendicular to the course of a drain bit line, FIG. 3 the state at the time of the alpha particle impact 11 and Fig. 4 illustrates the state thereafter. The depletion layer is formed under the drain bit line 12 9, with a bit line discharge of about 300 mV measured per alpha particle impact

030042/0079030042/0079

- 6 H.Reiner et al 34-1 Fl 997- 6 H. Reiner et al 34-1 Fl 997

wurde. Wiederum fließt nach Einschlag des Alpha-Teilchens der Substratstrom 10.became. The substrate current 10 flows again after the alpha particle has impacted.

Dieser Substratstrom 10 wird somit von der Ladungsträgertrennung durch die Verarmungsschicht verursacht, da im Wesentlichen keine Rekombination mehr stattfinden kann. Bei der Auslegung eines Halbleiterschaltkreises der betroffenen Art sind nach der Lehre der Erfindung also Verarmungsschichten möglichst gänzlich zu vermeiden, bzw. auf ein Flächenminimum zu bringen.This substrate current 10 is thus caused by the charge carrier separation caused by the depletion layer, since essentially no more recombination takes place can. When designing a semiconductor circuit of the type concerned are according to the teaching of Invention, therefore, to avoid depletion layers as completely as possible, or to bring them to a minimum area.

Die Fig. 5 zeigt nun in Querschnittsansicht die Speicherkapazität eines integrierten Halbleiterschaltkreises nach der Erfindung, bei der gänzlich die Ausbildung einer Verarmungsschicht im Halbeitersubstrat 4 vermieden ist. Die Speicherkapazität gemäß der Fig. 5 besteht aus zwei Elektrodenschichten 2, 2'; 3, wovon die obere gemäß der Fig. 5 aufgeteilt werden kann. Zwischen den beiden Elektrodenschichten befindet sich eine dielektrische Schicht 1. Die untere Elektrodenschicht 3 ist auf einer isolierenden Oberflächenschicht 13 des Substrats 4 aufgebracht und wird zur Verhinderung einer Verarmungsschicht mit dem Substrat 4 verbunden, oder auf ein entsprechendes Potential gelegt.FIG. 5 now shows, in a cross-sectional view, the storage capacity of an integrated semiconductor circuit according to the invention, in which the formation of a depletion layer in the semiconductor substrate 4 is completely avoided is. The storage capacity according to FIG. 5 consists of two electrode layers 2, 2 '; 3, of which the upper one can be divided according to FIG. 5. There is a dielectric layer between the two electrode layers Layer 1. The lower electrode layer 3 is on an insulating surface layer 13 of the Substrate 4 is applied and is connected to the substrate 4 to prevent a depletion layer, or placed on a corresponding potential.

Die Elektrodenschichten 2, 2', 3 können aus polykristallinem Silicium oder aus einem Metall bestehen, während die dielektrische Schicht 1 als Dünnoxidschicht ausgebildet werden kann.The electrode layers 2, 2 ', 3 can consist of polycrystalline silicon or of a metal, while the dielectric layer 1 can be formed as a thin oxide layer.

Die Fig. 6 veranschaulicht ausschnittweise in Querschnittsansicht den möglichen Aufbau einer Bitleitung in einem integrierten Halbleiterschaltkreis nach der Erfindung.' Die Bitleitung 5 aus einem Metall oder ausFIG. 6 illustrates a detail in a cross-sectional view of the possible structure of a bit line in a semiconductor integrated circuit according to the invention. ' The bit line 5 made of a metal or made of

030042/0079030042/0079

mm *1 mmmm * 1 mm

H.Reiner et al 34-1 Fl 997H. Reiner et al 34-1 Fl 997

Poly-Silicium ist auf einer Dickoxidschicht 6 aufgebracht und kontaktiert die Drain-Zone 14 eines Isolierschicht-Feldeffekttransistors, dessen Source-Zone nicht in der Zeichenebene liegt und mit einer Elektrode einer Speicherkapazxtät verbunden ist. Die Dicke der Dickoxidschicht 6 ist so zu wählen, daß sie mit dem Substrat 4 bei maximalen Spannungen keine Verarmungsschichten bilden kann. Der pn-übergang der Drain-Zone ist möglichst kleinflächig zu bemessen, damit die Wahrscheinlichkeit eines Alpha-Teilchen-Einschlags möglichst gering ist. Die Wortleitung wird mit der Gate-Elektrode des Isolier-Feldeffekt-Transistors verbunden.Poly-silicon is applied to a thick oxide layer 6 and contacts the drain zone 14 of an insulated gate field effect transistor, whose source zone is not in the plane of the drawing and with one electrode Storage capacity is connected. The thickness of the thick oxide layer 6 is to be chosen so that they with the Substrate 4 no depletion layers at maximum voltages can form. The pn junction of the drain zone should be dimensioned as small as possible, so that the probability of an alpha particle impact is as small as possible. The word line connects to the gate electrode of the isolation field effect transistor connected.

15Nach den vorhergehenden Ausführungen dürfte klar sein, daß die geringste Empfindlichkeit eines integrierten Schaltkreises nach der Erfindung dann erhalten werden, wenn beide anhand der Fig. 5 und 6 beschriebenen Maßnahmen ergriffen werden.15Following the foregoing, it should be clear that that the least sensitivity of an integrated circuit according to the invention are obtained when both measures described with reference to FIGS. 5 and 6 be seized.

Ein noch nicht erwähnter Vorteil des integrierten Schaltkreises nach der Erfindung besteht in der Einsparung von Bauelementkosten, da die bei Verwendung von herkömmlichen Schaltkreisen notwendige redundante Aus- An advantage of the integrated circuit not yet mentioned According to the invention, there is a saving in component costs, since the redundant configuration required when using conventional circuits

25legung der Systeme unterbleiben kann.25 system can be omitted.

2 Blatt Zeichnung mit 6 Figuren2 sheets of drawing with 6 figures

030042/0079030042/0079

Claims (3)

STANDARD ELEKTRIK LORENZSTANDARD ELECTRICS LORENZ AKTIENGESELLSCHAFTSHARED COMPANY STUTTGARTSTUTTGART H.Reiner et al 34-1 Fl 997H. Reiner et al 34-1 Fl 997 PatentansprücheClaims Integrierter Halbleiterschaltkreis mit integrierten Speicherkapazitäten, welche über elektronische Schalter geladen oder entladen werden, dadurch gekennzeichnet,Integrated semiconductor circuit with integrated storage capacities, which are controlled by electronic switches loaded or unloaded, characterized in that daß zur Verhinderung von durch Alpha-Teilchen bewirkten Störungen der Informationsspeicherung integrierte Kapazitäten verwendet werden, welche mit dem Substrat (4) keine Verarmungsschichten bilden.that to prevent interference caused by alpha particles in the information storage integrated Capacities are used which do not form any depletion layers with the substrate (4). 2. Integrierter Halbleiterschaltkreis nach Anspruch 1, gekennzeichnet durch mindestens eine integrierte Speicherkapazität mit Elektrodenschichten, yon denen eine Elektrodenschicht (3) isoliert auf dem Substrat (4) und eine andere Elektrodenschicht (2, 2') abseitig vom Substrat (4) auf der dielektrischen Schicht (1) angeordnet ist.2. Integrated semiconductor circuit according to claim 1, characterized by at least one integrated Storage capacity with electrode layers, one of which is an electrode layer (3) insulated on the substrate (4) and another electrode layer (2, 2 ') away from the substrate (4) on the dielectric layer (1) is arranged. 030042/0079030042/0079 _ ο —_ ο - H.Reiner et al 34-1 FlH. Reiner et al 34-1 Fl 3. Integrierter Halbleiterschaltkreis nach Anspruch oder 2, gekennzeichnet durch Bitleitungen (5) welche über eine Dickoxidschicht (6) mit dem Substrat (4) verbunden sind.3. Integrated semiconductor circuit according to claim or 2, characterized by bit lines (5) which are connected to the substrate (4) via a thick oxide layer (6). 030042/0079030042/0079
DE19792912439 1979-03-29 1979-03-29 INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY Withdrawn DE2912439A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19792912439 DE2912439A1 (en) 1979-03-29 1979-03-29 INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY
GB8010299A GB2045526A (en) 1979-03-29 1980-03-27 Integrated circuit capacitors
FR8006953A FR2452790A1 (en) 1979-03-29 1980-03-28 INTEGRATED SEMICONDUCTOR CIRCUIT COMPRISING INTEGRATED MEMORY CAPACITORS
JP3912580A JPS55146958A (en) 1979-03-29 1980-03-28 Semiconductor integrated circuit integrated with storage capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19792912439 DE2912439A1 (en) 1979-03-29 1979-03-29 INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY

Publications (1)

Publication Number Publication Date
DE2912439A1 true DE2912439A1 (en) 1980-10-16

Family

ID=6066777

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792912439 Withdrawn DE2912439A1 (en) 1979-03-29 1979-03-29 INTEGRATED SEMICONDUCTOR CIRCUIT WITH INTEGRATED STORAGE CAPACITY

Country Status (4)

Country Link
JP (1) JPS55146958A (en)
DE (1) DE2912439A1 (en)
FR (1) FR2452790A1 (en)
GB (1) GB2045526A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3148968A1 (en) * 1980-12-10 1982-07-01 Clarion Co., Ltd., Tokyo CAPACITOR WITH CHANGEABLE CAPACITY

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3163340D1 (en) * 1980-01-29 1984-06-07 Nec Corp Semiconductor device
DE3128014A1 (en) * 1981-07-15 1983-02-03 Siemens AG, 1000 Berlin und 8000 München ARRANGEMENT FOR REDUCING THE SENSITIVITY OF INTEGRATED SEMICONDUCTOR MEMORY AGAINST ALPHA RADIATION
FR2526225B1 (en) * 1982-04-30 1985-11-08 Radiotechnique Compelec METHOD FOR PRODUCING AN INTEGRATED CAPACITOR, AND DEVICE THUS OBTAINED
FR2530077A1 (en) * 1982-07-09 1984-01-13 Radiotechnique Compelec METHOD FOR PRODUCING INTEGRATED CAPACITORS IN A MICROELECTRONIC STRUCTURE
US5508881A (en) * 1994-02-01 1996-04-16 Quality Microcircuits Corporation Capacitors and interconnect lines for use with integrated circuits
EP0893831A1 (en) 1997-07-23 1999-01-27 STMicroelectronics S.r.l. High voltage capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3148968A1 (en) * 1980-12-10 1982-07-01 Clarion Co., Ltd., Tokyo CAPACITOR WITH CHANGEABLE CAPACITY

Also Published As

Publication number Publication date
FR2452790B3 (en) 1981-12-31
JPS55146958A (en) 1980-11-15
GB2045526A (en) 1980-10-29
FR2452790A1 (en) 1980-10-24

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