JPS6273748A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6273748A
JPS6273748A JP60212533A JP21253385A JPS6273748A JP S6273748 A JPS6273748 A JP S6273748A JP 60212533 A JP60212533 A JP 60212533A JP 21253385 A JP21253385 A JP 21253385A JP S6273748 A JPS6273748 A JP S6273748A
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
view
sealed
functions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60212533A
Other languages
English (en)
Inventor
Hiroyuki Goto
浩之 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60212533A priority Critical patent/JPS6273748A/ja
Publication of JPS6273748A publication Critical patent/JPS6273748A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 し発明の技術分野〕 本発明は半導体装置に関するもので、特に樹脂封止型平
導体装置に使用されるものである。
〔発明の技術的背景と七の問題点〕
従来の樹脂封止した半導体装置の構成を第４図、第５図
に示す。第４図は正面図、第５図は側面図で、１はテラ
！、２はチッｆ１をマウントシたフレ・−ム（リードフ
レーム）、３はゲンテ“イングワイヤ、４は樹脂封止を
行なうモールド樹脂である。
しかし？：（１ものＫ　ｌ−ｔ　ｔでは、ぎンｖ１イン
グを終えたフレーム２を、１層のみモールド樹１］！　
４によシ封止したもので６．たため、単位面積当シのテ
ップの機能性に限界があった。
〔発明の目的〕
本発明は上記実情に鑑みてなされたもので。
フレームを多層構造にすることによシ、１つのＩＣ（集
積回路）で数多くの機能をもたせた半導体装置を提供し
ようとするものである。
〔発明の概要〕
従来は１つのＩＣに１つのチップが封止されているが、
１つのチップは機能的に限界があるため、モールド樹脂
にてチップを封止する際、フレームを多層にして封止す
ることによシ％１つのＩＱに多機能をもたせたものでち
る。
〔発明の実施例〕
以下図面を参照して本発明の一実施例を説明する。第１
図は同実施例の正面図、第２図は同側面図であるが、こ
れは前記従来例のものに対応させた場合の例であるから
、対応個所には同一符号を用い、かつ０れに層数に応じ
た添字を付しておく。図中ｌＮｍ１Ｍはそれぞれ１層目
。
２ｍ層目のテツｆ、電８，２．はチップ’Ｉ　　ｐ１＊
ｔそれぞれマウントしたフレーム（リードフレーム）、
３１ｔ３ｔはそれぞれ１層目、２層目のデンディングワ
イヤ、４は一体に樹脂封止を行なうモールド樹脂である
。上記フレーム２、と２８の間はモールド樹脂４で絶縁
する。
多層にするに従がい、モールド樹脂４の厚さも技術的に
必要な厚さにする。
第３図は本発明を３層構造の半導体装置にした場合の例
である。この装置のつく夛方は、従来と同様に各層でマ
ウント、Ｉンディング工程を行ない、多層構造に配置し
てモールド樹脂４で一体化の封止を行なえばよい。
上記の如くフレームを２層、３層、４層、・・・とする
ことによシ、１つのＩＣ（半導体装置）の機能を増大さ
せることができる。しかも従来のマセンブリ工程と比べ
て工程数が増えることがなく、面積的にも有利となる。
〔発明の効果〕
以上説明した如く本発明によれば、１つのＩＣの機能を
増大させることができ、工程が簡単でしかも面積的にも
有利な半導体装置が提供できるものである。
【図面の簡単な説明】
第１図は本発明の一実施例の正面面、第２図は同側面図
、第３図は本発明の曲の実施例の正面図、第４図は従来
装置の正面図％第５図は同側面図である。 １１〜１墨・・・ｔツブ、２．〜２．・・・フｔ／−ム
。 ３ｔ〜３烏・・・ノンディングワイヤ、４・・・毛−ル
ド樹脂。

Claims (1)

    【特許請求の範囲】
  1. リードフレームに半導体チップをマウントしてなるもの
    を多数重ねて多重構造とし、これをモールド樹脂で一体
    化したことを特徴とする半導体装置。
JP60212533A 1985-09-27 1985-09-27 半導体装置 Pending JPS6273748A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60212533A JPS6273748A (ja) 1985-09-27 1985-09-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60212533A JPS6273748A (ja) 1985-09-27 1985-09-27 半導体装置

Publications (1)

Publication Number Publication Date
JPS6273748A true JPS6273748A (ja) 1987-04-04

Family

ID=16624247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60212533A Pending JPS6273748A (ja) 1985-09-27 1985-09-27 半導体装置

Country Status (1)

Country Link
JP (1) JPS6273748A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105450A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体装置
US5530292A (en) * 1990-03-15 1996-06-25 Fujitsu Limited Semiconductor device having a plurality of chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105450A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体装置
US5530292A (en) * 1990-03-15 1996-06-25 Fujitsu Limited Semiconductor device having a plurality of chips

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