JPS6261527U - - Google Patents
Info
- Publication number
- JPS6261527U JPS6261527U JP15266385U JP15266385U JPS6261527U JP S6261527 U JPS6261527 U JP S6261527U JP 15266385 U JP15266385 U JP 15266385U JP 15266385 U JP15266385 U JP 15266385U JP S6261527 U JPS6261527 U JP S6261527U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current
- base
- resistance element
- input current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の第１の実施例を示す回路図、
第２図は本考案の第２の実施例を示す回路図、第
３図及び第４図はそれぞれ従来のカレント・ミラ
ー回路の第１及び第２の例を示す回路図である。
１……入力端子、２，３……出力端子、Ｉ１…
…入力電流、Ｉ０１，Ｉ０２……出力電流、Ｑ１
，Ｑ２，Ｑ１１，Ｑ１２，Ｑ１３，Ｑ２１，Ｑ２
３……トランジスタ、Ｒ１，Ｒ２……抵抗素子。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams showing first and second examples of conventional current mirror circuits, respectively. 1...Input terminal, 2,3...Output terminal, I1 ...
...Input current, I 01 , I 02 ...Output current, Q 1
, Q 2 , Q 11 , Q 12 , Q 13 , Q 21 , Q 2
3 ...transistor, R1 , R2 ...resistance element.
Claims (1)
第１のトランジスタと、ベースが入力電流の入力
端子に接続したＮＰＮ（またはＰＮＰ）型の第２
のトランジスタと、前記第１のトランジスタのエ
ミツタと前記第２のトランジスタのベースとの間
に接続された第１の抵抗素子と、前記第２のトラ
ンジスタのエミツタと前記第１のトランジスタの
ベースとの間に接続された第２の抵抗素子と、前
記第１のトランジスタのコレクタに接続され前記
入力電流と同位相で大きさが等しい電流を出力す
る第１の出力端子と、前記第２のトランジスタの
コレクタに接続され前記入力電流と逆位相で絶対
値の比が前記第２の抵抗素子の抵抗値に対する前
記第１の抵抗素子の抵抗値の比に等しい電流を出
力する第２の出力端子とを有することを特徴とす
るカレント・ミラー回路。 A first transistor of PNP (or NPN) type whose base is grounded, and a second transistor of NPN (or PNP) type whose base is connected to an input terminal for input current.
a first resistance element connected between the emitter of the first transistor and the base of the second transistor; and the emitter of the second transistor and the base of the first transistor. a first output terminal connected to the collector of the first transistor and outputting a current having the same phase and magnitude as the input current; a second output terminal connected to the collector and outputting a current having an opposite phase to the input current and having an absolute value ratio equal to the ratio of the resistance value of the first resistance element to the resistance value of the second resistance element; A current mirror circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15266385U JPS6261527U (en) | 1985-10-04 | 1985-10-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15266385U JPS6261527U (en) | 1985-10-04 | 1985-10-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6261527U true JPS6261527U (en) | 1987-04-16 |
Family
ID=31070845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15266385U Pending JPS6261527U (en) | 1985-10-04 | 1985-10-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6261527U (en) |
-
1985
- 1985-10-04 JP JP15266385U patent/JPS6261527U/ja active Pending
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