JPS6252487B2 - - Google Patents
Info
- Publication number
- JPS6252487B2 JPS6252487B2 JP57219962A JP21996282A JPS6252487B2 JP S6252487 B2 JPS6252487 B2 JP S6252487B2 JP 57219962 A JP57219962 A JP 57219962A JP 21996282 A JP21996282 A JP 21996282A JP S6252487 B2 JPS6252487 B2 JP S6252487B2
- Authority
- JP
- Japan
- Prior art keywords
- npn
- emitter
- base
- current
- npn transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/34—DC amplifiers in which all stages are DC-coupled
- H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は電流源回路に係り、特に集積回路技法
に適する電流源回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to current source circuits, and more particularly to current source circuits suitable for integrated circuit technology.
従来の電流源回路の一例を第１図に示し説明す
ると、図において、１，２はそれぞれベースおよ
びエミツタを共通接続したNPNトランジスタ
で、これらは前記の電流ミラー回路を構成し、そ
のNPNトランジスタ２の形状はNPNトランジス
タ１のｎ倍である。また、３，４はそれぞれベー
スおよびエミツタを共通接続したNPNトランジ
スタで、これらは後段の電流ミラー回路を構成
し、そのNPNトランジスタ４の形状はNPNトラ
ンジスタ３のｍ倍である。そして、１１は基準入
力電流端子、１２は入力電流端子、１３は出力電
流端子（電流源出力端子）である。 An example of a conventional current source circuit is shown in FIG. 1. In the figure, 1 and 2 are NPN transistors whose bases and emitters are commonly connected, and these constitute the aforementioned current mirror circuit. The shape of is n times that of NPN transistor 1. Further, 3 and 4 are NPN transistors whose bases and emitters are commonly connected, and these constitute a current mirror circuit in the subsequent stage, and the shape of the NPN transistor 4 is m times that of the NPN transistor 3. 11 is a reference input current terminal, 12 is an input current terminal, and 13 is an output current terminal (current source output terminal).
このように構成された回路において、基準入力
電流端子１１に流す電流をI0とし、NPNトランジ
スタ１のコレクタに流れる電流をI1とし、以下、
NPNトランジスタ２，３，４のそれぞれのコレ
クタに流れる電流をI2，I3，I4とし、出力電流端
子（電流源出力端子）に流れる電流をI4とする。 In the circuit configured in this way, the current flowing through the reference input current terminal 11 is I0 , the current flowing through the collector of the NPN transistor 1 is I1 , and below,
The currents flowing through the collectors of the NPN transistors 2, 3, and 4 are I 2 , I 3 , and I 4 , and the current flowing through the output current terminal (current source output terminal) is I 4 .
そして、いま、Ａ点に流れる電流をＩ1 Now, the current flowing at point A is I 1
Claims (1)
スとエミツタをそれぞれ共通接続し、第１の
NPNトランジスタのコレクタとベースを接続し
てこの接続点を基準入力電流端子として第１の電
流ミラー回路を構成し、第３および第４のNPN
トランジスタのベースとエミツタをそれぞれ共通
接続しこの第３のNPNトランジスタのコレクタ
を前記第１および第２のNPNトランジスタのエ
ミツタ共通接続点に接続し第４のNPNトランジ
スタのコレクタを電流源出力端子として第２の電
流ミラー回路を構成し、前記第１の電流ミラー回
路を構成する第１および第２のNPNトランジス
タのベースと前記第２の電流ミラー回路を構成す
る第３および第４のNPNトランジスタのベース
との間に第５のNPNトランジスタのベースとエ
ミツタをそれぞれ接続するようにしたことを特徴
とする電流源回路。1 Connect the bases and emitters of the first and second NPN transistors in common, and
A first current mirror circuit is configured by connecting the collector and base of the NPN transistor and using this connection point as a reference input current terminal, and the third and fourth NPN
The base and emitter of the transistor are connected in common, the collector of the third NPN transistor is connected to the emitter common connection point of the first and second NPN transistors, and the collector of the fourth NPN transistor is used as a current source output terminal. 2, the bases of first and second NPN transistors forming the first current mirror circuit and the bases of the third and fourth NPN transistors forming the second current mirror circuit; A current source circuit characterized in that the base and emitter of a fifth NPN transistor are respectively connected between the base and the emitter of the fifth NPN transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57219962A JPS59108411A (en) | 1982-12-13 | 1982-12-13 | Current source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57219962A JPS59108411A (en) | 1982-12-13 | 1982-12-13 | Current source circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59108411A JPS59108411A (en) | 1984-06-22 |
| JPS6252487B2 true JPS6252487B2 (en) | 1987-11-05 |
Family
ID=16743760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57219962A Granted JPS59108411A (en) | 1982-12-13 | 1982-12-13 | Current source circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59108411A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3603799A1 (en) * | 1986-02-07 | 1987-08-13 | Philips Patentverwaltung | CURRENT MIRROR SWITCHING |
| CH702061A1 (en) | 2009-10-26 | 2011-04-29 | Thi Technologies Horlogeres Ind S A | Stretch bracelet clasp. |
| CH704335B1 (en) | 2011-01-13 | 2015-06-30 | Thi Technologies Horlogères Ind S A | extensible clasp for a bracelet including a watch. |
| CH705149B1 (en) | 2011-06-30 | 2016-02-29 | Thi Technologies Horlogères Ind S A | extensible clasp for a bracelet including a watch. |
-
1982
- 1982-12-13 JP JP57219962A patent/JPS59108411A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59108411A (en) | 1984-06-22 |
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