JPS60102004A - Emitter follower circuit - Google Patents

Abstract

PURPOSE:To obtain a large output current even when an input bias current is small, and to reduce chip area by constituting a circuit whose input bias current is small by using a current mirror circuit. CONSTITUTION:The current amplification factors of transistors TR 9 and 10 are both set to beta equally and the input and output currents of the mirror circuit consisting of TRs 11 and 12 are set to IB10 equally. Then, an input bias current IB and output current I0 at an input terminal 1 and an output terminal 2 are in relation I0=beta<2>.IB, so the input bias current is one over the integral of the current amplification factor of the TRs 9 and 10 and becomes less than the input current. Further, only one base emitter voltage of a TR is necessary between the input terminal 1 and output terminal 2, and even if the potential at the input terminal 1 drops, an output waveform is hard to distort. Furthermore, the TRs 9 and 10 of an output stage are NPN type TRs, so the chip area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a seven-emitter lowerer circuit in which the input bias current is reduced to sq':f.

Conventionally, the circuit shown in the summary is widely used as an emitter follower circuit designed to reduce the input bias current. That is, the first transistor 4 and the second transistor 5 are all connected in Darlington, the pace of the first transistor 4 is set as the input terminal 1, the emitter of the second transistor 5 is set as the output terminal 2, and the output terminal 2 A load 6f: is connected between the transistor 4 and the common potential.
, 5 are commonly connected to form the power supply terminal 3, and the transistors 4 and 5 of the first and WI2 are both NPN transistors.

In the conventional circuit shown in FIG. 1, the input bias current iB is. Here, s'O is the output 'FM flowing to load 6,
(tit is 6.0, β is the current amplification factor of the transistor, V.

β! , βri are the first and second transistors 4., respectively.
The current amplification factor is 5.

Thus, in the conventional circuit shown in FIG.

The human bias current IB is approximately the output current l. Against.

The transistor's ゛ is the square of the current amplification factor -,
An emitter follower circuit with a small manual bias current was realized.

However, in the circuit shown in Figure $1, the base-emitter voltage VBB of the transistor is present between the input terminal l and the output terminal 20.
It takes k2 minutes, that is, a voltage of about 1.4V is required. Therefore, when the potential of input terminal 1 is low to 1%, the base-emitter voltage VB of the first and second transistors is
Bk cannot be secured, the first and second transistors are cut off, and the output waveform is distorted.

A circuit shown in FIG. 2 has been used as a conventional circuit that has improved the above drawbacks. In the conventional circuit shown in Figure 2,
NPN type third transistor 7 and PNP type fourth transistor
The transistor 8 is used. The collector current of the third transistor 7 is connected to the base of the fourth transistor 8, and the emitter of the third transistor 7 is connected to the collector of the transistor 8 of @4, forming a so-called inverted Darlington connection. The base of the third transistor 7 is connected to the input terminal 1, and the emitter of the fourth transistor 8 is connected to the power supply terminal 3vc.

A connection point between the emitter of the third transistor 7 and the collector of the fourth transistor 8 is connected to the output terminal 2.

Output": A load 6 is connected between the Ili element 2 and the common potential.

In the conventional circuit of FIG. 2, the fourth transistor 8
Since the base 1L current of 1L becomes the collector current of the third transistor 7, the manual bias N current: IB' becomes. Here, β3 is the current amplification factor of the third transistor 7, and β4t is the current amplification factor of the fourth transistor 8.

That is, even in the conventional circuit shown in Fig. 2, the input bias [6iE is approximately equal to the square of the current amplification factor of the transistor with respect to the output current, so that an emitter 7-lower circuit with a small input bias current is realized. ing. Moreover,
A third transistor 7 is connected between the input terminal l and the output terminal 2.
Only the base-emitter voltage of
．． Since only 7 V is required, even when the potential of the input terminal 1 decreases, improved characteristics can be obtained compared to the conventional circuit shown in FIG. 1 (VCm).

However, if the conventional circuit shown in FIG. 2 were to be made into an all-semiconductor integrated circuit, most of the large output current would be supplied from the PNP-type fourth transistor. A PNP transistor for obtaining a relatively large collector current has an area t-i that is about 10 times that of a case where all NPN transistors are used. As a result, the area of the semiconductor integrated circuit chip increases, resulting in a large economic loss.

The object of non-invention is to
The present invention provides an emitter follower circuit that has a small voltage and input bias current, and can obtain a large output current while occupying a relatively small area. An emitter seven-lower circuit according to the present invention is shown in FIG.

In the circuit shown in FIG. 3, the base of the NPN type fifth transistor 9 is used as the input terminal 1.

The emitter is used as an output terminal 2, and a load 6 is connected between the output terminal 2 and a common potential. The emitter of a sixth N P N type transistor 10 is connected to the collector of the transistor 81!5, and the collector is connected to the power supply terminal 3. Furthermore, the sixth transistor 10
0 pace, PNP type seventh transistor 11 and eighth transistor
The input terminal of a current mirror circuit constituted by a transistor 12 is connected to the current mirror circuit, and the output terminal of this current mirror circuit is connected to the input terminal lvcw.

In this circuit configuration, the output current I. is given as the emitter current of the fifth transistor 9.

The base current of the fifth transistor 9: lns is where β5t is the current amplification factor of the transistor 9ONIL. Further, the collector current tcs of the fifth transistor 9 is as follows.

On the other hand, since the same current as the collector current IC5 of the fifth transistor 9 flows through the emitter of the sixth transistor 10, the base current of the sixth transistor 1°: IB6
Hato becomes. Here, β6 is the current amplification factor of the sixth transistor 10.

When the circuit in Figure 3 is made into a half-layer integrated circuit, the fifth and sixth
The current amplification factors β5 and β6 of the transistors 9 and 10 are almost equal.If this is β, then β=β5=β6 ・
......(6). Therefore, using equation (6), equation (5) becomes. sixth transistor 10
The base 't4ffltLB6 is supplied to the input terminal 1 through a current mirror circuit including the seventh and eighth transistors 11 and 121t. When the ratio of the input terminal and output current of the current mirror circuit is set to 1 = 1, the output current of the current mirror circuit is supplied as a current through the transistor 90 base bus (7 bus), so the manual bias supplied from input terminal 1 ゛l1lD1t IB"is 1B"=lB5
-IB6 O -β2 "-°゛°-(8) In other words, the 5-force bias current is the integral of the current amplification factors of transistors 9 and 10 relative to the output current, and as shown in Fig. 1 and As with the conventional circuit shown in Fig. 2, the manual bias current is small.Moreover, input terminal 1 and output ?j
Only one voltage VBl+ between the base and emitter of the transistor is required between the terminal A and terminal 20, which is approximately 0.7μ, so even if the potential of input terminal 1 decreases, there is no distortion in the output waveform. is less likely to occur. Furthermore, fifth and sixth transistors 9. through which a large output current flows. lO are both NPN
A collection of semiconductors consisting of transistors
When circuitized, the area of the semiconductor chip can be reduced.

In the uninvented circuit shown in FIG.
) Using a transistor, the emitters and bases of the seventh and eighth transistors 11 and 12 are all connected in common, the collector and base of the seventh transistor 11 are connected as an input terminal, and the emitters and bases of the seventh transistor 11 and the base are connected in common. A current mirror circuit configured as the collector full output terminal was used, but
In view of the spirit of non-invention, the non-invention can also be realized by using other known current mirror circuits, and in FIG. 3, the 7L source end of the current mirror circuit.

That is, the common emitters of the seventh and eighth transistors 11 and 12 are connected to the power supply terminal 3 as an emitter follower circuit, but this means that the power supply terminal of the current mirror circuit is There is no problem when connecting to.

[Brief explanation of the drawing]

Figures 1, 2 and 2 are circuit diagrams showing conventional emitter follower circuits, and Figure 3 is a circuit diagram showing a conventional emitter follower circuit.
It is a circuit diagram showing an Olowa circuit basin. 1...Input terminal, 2...Output terminal, 3
・・・・・・ft,：Ryo terminal, 6・・・・・・Load, 4
．． 5.7,8,9,10°11.12...transistor. X7 Figure Z Figure Z 3 ton I

Claims (1)

[Claims] The current mirror circuit includes first and second transistors connected in series, and a current mirror circuit whose input end is connected to the pace of the second transistor and whose output end is connected to the pace of the first transistor. An emitter 7-lower circuit characterized by obtaining an output from the emitter of one transistor.