JPH0155772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an emitter follower circuit, and more particularly to an emitter follower circuit for providing an operational amplifier circuit with less load fluctuation characteristics than conventional circuits.

[Prior art]

FIG. 1 shows the configuration of a conventional emitter follower circuit. In the figure, Q1 is an NPN transistor whose base is the input terminal 11, I0 is a constant current source for supplying constant current I, 12 is an output terminal, and Vcc is a power supply.

In this circuit, the output current Iout changes from I1 to I
2, how much the output voltage Vout changes is calculated below.

When the output current Iout is I1, the emitter current of transistor Q1 is I+I1, and the output current Iout is I1.
2, the emitter current of the transistor Q1 is I+I2. Here, since the relationship between the emitter current and the voltage between the base and emitter of transistor Q1 follows Schottley's equation, the output voltage at this time is
The voltage fluctuation ΔVout of Vout is as follows.

ΔVout=kT/qln(I+I2)/(I+I1)...(1) Here, k: Boltzmann constant, T: absolute temperature,
q: Electric charge.

[Summary of the invention]

The present invention provides an emitter follower circuit having a transistor whose base and emitter are used as an input terminal and an output terminal, respectively, and whose collector is supplied with a constant current. The object of the present invention is to provide an emitter follower circuit that can significantly reduce input voltage fluctuations compared to conventional circuits by connecting a transistor and using the transistor to suppress fluctuations in the current flowing through the output terminal. .

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an emitter follower circuit according to one embodiment of the invention. In the figure, I0 is a constant current source for supplying constant current I, Q1 is a first transistor whose collector is connected to the constant current source I0, and Q2 is a transistor whose collector is connected to the transistor Q1.
Q3 is a second transistor whose emitter is connected to the emitter of the transistor Q1, and whose emitter is grounded. Q3 is a third transistor (driving transistor) whose emitter and base are connected to the collector and base of the transistor Q1, respectively, and whose collector is connected to the base of the transistor Q2. circuit),
11 is an input terminal connected to the bases of the transistors Q1 and Q3, and 12 is the transistor Q1.
This is the output terminal connected to the emitter of

Next, the effects will be explained.

Now, in this circuit, the output current Iout is from I1 to I2
, the emitter current of transistor Q1 changes from I-(I-I1)/hFE2 to I-(I-
I2)/hFE2. Here, hFE2 is the common emitter current amplification factor of transistor Q2.

Therefore, the output voltage fluctuation ΔVout at this time is as follows.

ΔVout=kT/qln(I-(I-I2)/hFE2/I-(I-
I1)/hFE2) kT/qln(I+(I2/hFE2)/I+(I1/hFE2))
...(2) However, I・hFE2−I≒I・hFE2.

In this way, the variation in the circuit of this embodiment is suppressed to about 1/hFE2 compared to the circuit of FIG. 1.

FIG. 3 shows another embodiment of the present invention, which is designed to further reduce load fluctuations and includes a fourth transistor between the emitter of transistor Q3 and the collector of transistor Q1 in the circuit of FIG. A transistor Q4 is connected to the transistor Q4. That is, the emitter of the transistor Q4 is connected to the emitter of the transistor Q3, the base to the collector of the transistor Q1, and the collector to the power supply Vcc.

In this example circuit, the output current Iout is I
When changing from 1 to I2, the emitter current of transistor Q1 is I-(I-I1)/(hFE2・hFE4)
It changes from I-(I-I2)/(hFE2・hFE4).

Here, hFE4 is the common emitter current amplification factor of transistor Q4.

Therefore, the output voltage fluctuation ΔVout at this time is as follows.

ΔVout=kT/qln(I-(I-I2)/(hFE2・hFE4)/
I-(I-I1)/(hFE2・hFE4)) kT/qln(I+(I2/hFE2・hFE4)/I+(I1
/hFE2・hFE4))……(3) However, I・hFE2・hFE4−I≒I・hFE2・
It is called hFE4.

In this way, in the circuit of this embodiment, the output voltage fluctuation is suppressed to approximately 1/hFE2・hFE4 compared to the circuit shown in FIG. 1, and the fluctuation is further reduced to approximately 1/hFE4 compared to the circuit shown in FIG. It's suppressed.

〔Effect of the invention〕

As described above, according to the present invention, the base,
The emitters are respectively input and output terminals,
In an emitter follower circuit having a transistor whose collector is supplied with a constant current, a transistor that operates with a current proportional to the constant current is connected to the emitter of the transistor, and this transistor causes fluctuations in the current flowing to the output terminal. Since the current emitter follower circuit is suppressed, the load fluctuation characteristics can be significantly improved compared to the conventional emitter follower circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional emitter follower circuit, FIG. 2 is a circuit diagram of an emitter follower circuit according to an embodiment of the present invention, and FIG. 3 is a circuit diagram of an emitter follower circuit according to another embodiment of the present invention. In the figure, Q1 is the first transistor, Q2
is a second transistor, Q3 is a third transistor, Q4 is a fourth transistor, 11 is an input terminal, and 12 is an output terminal. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A first transistor whose base and emitter are used as input and output terminals, respectively, and whose collector is supplied with a constant current, and whose collector is connected to the emitter of the first transistor and whose emitter is grounded. The present invention is characterized by comprising a second transistor and a drive circuit that supplies a current proportional to the constant current supplied to the first transistor to the base of the second transistor to drive the second transistor. Emitsuta follower circuit. 2. The drive circuit is a transistor whose emitter and base are connected to the collector of the first transistor, and whose base and collector are connected to the base of the second transistor, respectively. Emitsuta follower circuit. 3. The drive circuit includes a third transistor whose base is connected to the base of the first transistor and whose collector is connected to the base of the second transistor, and whose base is connected to the collector of the first transistor and whose emitter is connected to the third transistor. 2. The emitter follower circuit according to claim 1, further comprising a fourth transistor whose collector is connected to a power source at the emitter of the transistor.