JPS59161108A - Amplifier circuit - Google Patents
Amplifier circuitInfo
- Publication number
- JPS59161108A JPS59161108A JP58035335A JP3533583A JPS59161108A JP S59161108 A JPS59161108 A JP S59161108A JP 58035335 A JP58035335 A JP 58035335A JP 3533583 A JP3533583 A JP 3533583A JP S59161108 A JPS59161108 A JP S59161108A
- Authority
- JP
- Japan
- Prior art keywords
- current mirror
- transistor
- output
- collector
- trs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は集積回路に逸した差動増幅回路に関する。[Detailed description of the invention] TECHNICAL FIELD The present invention relates to a differential amplifier circuit that is not integrated into an integrated circuit.
第１図は差動増幅回路の従来例を示すもので、増幅用の
ＰＮＰ差動トランジスタ１及び４更にシングルエンド出
力を得る為にＮＰＮ）ランジスタ２．３が設けられてお
りトランジスタ３のコレクタに出力端子が接続されてお
り、差動トランジスタのバイアス電流を供給する為に回
路電源■１＋と直列にＰＮＰ ）ランジスタ５が設けら
れるとともに、当該トランジスタのコレクタはトランジ
スタ１，４のエミッタに接続されている。かかる構成に
於いて、出力端子のとりつる動作電圧範囲を考察するに
入力端子のバイアス電圧をｖ２とすると、出力電圧の上
限は、はぼＶ２に等しく、又その下限はトランジスタ３
の飽和電圧に等しく、おおよそ０．３■程贋である。即
ち入力端子のバイアス電圧が低い時は出力電圧のとりう
る範囲は、非常に狭いものとなる。従って当該出力端子
を後段の入力端子に接続する場合、後段の回路は著しく
設計の自由度を失うことになる。Figure 1 shows a conventional example of a differential amplifier circuit, in which PNP differential transistors 1 and 4 are provided for amplification, and NPN transistors 2 and 3 are provided to obtain a single-ended output. The output terminal is connected, and a PNP transistor 5 is provided in series with the circuit power supply ■1+ to supply the bias current of the differential transistor, and the collector of the transistor is connected to the emitters of transistors 1 and 4. There is. In such a configuration, considering the operating voltage range of the output terminal, if the bias voltage of the input terminal is v2, the upper limit of the output voltage is approximately equal to V2, and the lower limit is equal to the voltage of the transistor 3.
It is equal to the saturation voltage of , and is about 0.3cm false. That is, when the bias voltage at the input terminal is low, the possible range of the output voltage becomes extremely narrow. Therefore, when the output terminal is connected to the input terminal of the subsequent stage, the degree of freedom in designing the subsequent circuit is significantly lost.
本発明の目的は、簡単な回路構成で、広い出力電圧範囲
をもつ差動増幅回路を提供することである。An object of the present invention is to provide a differential amplifier circuit with a simple circuit configuration and a wide output voltage range.
本発明によれば、第１のトランジスタと第２のトランジ
スタか差動トランジスタ対を構成するとともに、各々の
ベースが入力端子に導出され、かつ第１のトランジスタ
のコレクタが第１のカレントミラーの入力に接続され、
出力が第２のカレントミラー回路の入力に接続され、又
前記第２のトランジスタのコレクタが第３のカレントミ
ラーの入力に接続され、かつ出力が前記第２のカレント
ミラー回路の出力に接続されるとともに出力端子に導出
されることを特徴とする増幅回路が得られる。According to the present invention, the first transistor and the second transistor constitute a differential transistor pair, each base being led out to an input terminal, and the collector of the first transistor being connected to the input terminal of the first current mirror. connected to
An output is connected to an input of a second current mirror circuit, a collector of the second transistor is connected to an input of a third current mirror, and an output is connected to an output of the second current mirror circuit. Thus, an amplifier circuit is obtained which is characterized in that the signal is output to the output terminal.
次に本発明をその実施例に従い図面を用いて詳細に説明
する。Next, the present invention will be explained in detail according to embodiments using the drawings.
第２図り１、本発明の一実施例を示す回路図である。入
力段は差動ＰＮＰ ）ランジスタ９，１１で構成され、
トランジスタ９のコレクタはトランジスタ７．８で構成
されるカレントミラー回路に接続され、同様にトランジ
スタ１１のコレクタは、トランジスタ１２．１３で構成
されるカレントミラー回路に接続される。又前記２つの
カレントミラー回路の出力はトランジスタ６．１４で構
成されるカレントミラー回路と接続され、トランジスタ
１３と１４のコレクタに出力端子が接続されている。か
かる構成に於いて、出力端子のとりつる動作電圧範囲を
考察するに出力電圧の上限はｖ３＋からトランジスタ１
４の飽和電圧を引いたもの即ちは＃’ｌ （Ｖｓ＋−０
，３） Ｖ程度、又その下限はトランジスタ１３の飽和
電圧即ちほぼ０．３ Ｖ程度となり、動作範囲は、おお
よそ電源電圧に一致する。従って入力端子のバイアス電
圧とは無関係となり後段の回路設計は著しく容易になる
。この利点は低電圧動作が必要な場合、著しく顕著とな
る。本発明は以上説明し、たよりに簡単な回路構成で出
力電圧範囲の広い増幅回路を得ることが出来る。The second diagram 1 is a circuit diagram showing an embodiment of the present invention. The input stage consists of differential PNP transistors 9 and 11.
The collector of transistor 9 is connected to a current mirror circuit made up of transistors 7.8, and likewise the collector of transistor 11 is connected to a current mirror circuit made up of transistors 12.13. The outputs of the two current mirror circuits are connected to a current mirror circuit composed of transistors 6 and 14, and the output terminals are connected to the collectors of transistors 13 and 14. In such a configuration, considering the operating voltage range of the output terminal, the upper limit of the output voltage is from v3+ to transistor 1.
4 minus the saturation voltage is #'l (Vs+-0
, 3) V, and its lower limit is the saturation voltage of the transistor 13, that is, approximately 0.3 V, and the operating range approximately corresponds to the power supply voltage. Therefore, it is independent of the bias voltage of the input terminal, and the subsequent circuit design becomes extremely easy. This advantage becomes particularly pronounced when low voltage operation is required. The present invention has been described above, and it is possible to obtain an amplifier circuit with a wide output voltage range with a relatively simple circuit configuration.
第１Ｎは従来例を示す回路図であり、第２図は本発明の
一実施例を示す回路図である。
１．２，３ｔ４ｔ５，６，７，８，９，１０，１１，１
２，１３゜１４・・・・・・トランジスタ。
５−
穿１回
半２揖1N is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1.2,3t4t5,6,7,8,9,10,11,1
2,13゜14...transistor. 5- 1 and a half times 2 liters
Claims (1)
ジスタ対を構成するとともに、各々のベースが入力端子
に導出され、かつ第１のトランジスタのコレクタが裏１
のカレントミラーの入力に接続され、出力が第２のカレ
ントミラー回路の入力に接続てれ、又前記第２のトラン
ジスタのコレクタが第３のカレントミラーの入力に接続
され、かつ出力が前記第２のカレントミラー回路の出力
に接続さｎるとともに出力端子に導出されることを特徴
とする増幅回路。The first transistor and the second transistor constitute a differential transistor pair, each base is led out to an input terminal, and the collector of the first transistor is connected to the back side.
The collector of the second transistor is connected to the input of a third current mirror, and the output of the second transistor is connected to the input of a third current mirror, and the output of the second transistor is connected to the input of a third current mirror. An amplifier circuit characterized in that it is connected to the output of a current mirror circuit and is led out to an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035335A JPS59161108A (en) | 1983-03-04 | 1983-03-04 | Amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035335A JPS59161108A (en) | 1983-03-04 | 1983-03-04 | Amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161108A true JPS59161108A (en) | 1984-09-11 |
Family
ID=12438962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58035335A Pending JPS59161108A (en) | 1983-03-04 | 1983-03-04 | Amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161108A (en) |
-
1983
- 1983-03-04 JP JP58035335A patent/JPS59161108A/en active Pending
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