JPS6276911A - Differential circuit - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a power voltage and to expand the common mode input range by constituting a differential pair by a couple of npn transistors (TRs) and inserting a negative impedance circuit comprising a couple of pnp TRs between the emitters of both the TRs. CONSTITUTION:The negative impedance circuit 23 comprising a couple of the pnp TRs 20, 21 whose base and collector are connected in crossing is inserted between emitters of a couple of TRs 11, 12 constituting a differential pair 13. Further, the collector-emitter current paths of a couple of the TRs 20, 21 and a couple of the TRs 11, 12 are connected in parallel. Thus, the base bias voltage of the TRs 11, 12 is set to a value increased by a base-emitter voltage of a TR or over from the current source 18 or 19, then the TRs are acted normally. As a result, the utilization efficiency of the power voltage is improved and the in-phase input range is expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a differential circuit used in an input stage of an integrated circuit, and particularly to a differential circuit with excellent linearity of transfer characteristics.

[Technical background of the invention and its problems] As a differential circuit with excellent linearity of transfer characteristics,
The one disclosed in Japanese Patent No. 44296 is well known. As shown in FIG. 2, this circuit consists of a pair of NPN transistors 31 and 32 that constitute a differential pair 33, and a pair of NPN transistors 31 and 32 whose bases and collectors are cross-connected between the emitters of the transistors 31 and 32. npn) Negative impedance circuit 3B consisting of transistors 34 and 35
By inserting , the differential amplification gain is increased.

Note that one end of a current source 37 serving as an operating current source for the differential pair 33 and the negative impedance circuit 36 is connected to a common connection point between the emitters of the transistors 34 and 35 constituting the negative impedance circuit 36.

However, in this conventional circuit, the bases and emitters of the transistors 31 and 32 forming the differential pair 33 and the transistors 34 and 35 forming the negative impedance circuit 3B are connected in series.
If the base bias voltage of 2 is not set to a value that is higher than the base-emitter voltage of two transistors from the current [37], it will not operate normally.In other words, the base-emitter voltage of a typical transistor is approximately 0. 7V, the base bias voltage of the transistors 31 and 32 must be set to a value that is approximately 1.γV or more higher than the current source 37.For this reason, the power supply voltage utilization efficiency is low and the common mode input range is It has the disadvantage of being narrow.

[Object of the Invention] This invention has been made in consideration of the above circumstances, and its purpose is to provide a differential circuit that has high power supply voltage utilization efficiency and can improve the common mode input range. It is in.

[Summary of the Invention] In order to achieve the above object, in the present invention, one input signal is supplied to the base of a first transistor having one polarity, one output signal is taken out from the collector thereof, and one polarity The base of a second transistor of the other polarity is supplied with the other human input signal, and the output signal of the other is taken out from its collector, the base of a third transistor of the other polarity is connected to the emitter of the second transistor, and this Third
The collector of the transistor is connected to the emitter of the first transistor, the base of a fourth transistor of the other polarity is connected to the emitter of the first transistor, and the collector of the fourth transistor is connected to the emitter of the first transistor. and the emitters are commonly connected to the emitters of the third transistor, and one ends of the first and second constant current means are connected to the emitters of the first transistor and the emitter of the second transistor, respectively. One end of the third constant current means is connected to the common emitter of the third and fourth transistors.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a differential circuit according to the present invention. npn) The transistors 11 and 12 constitute a differential pair 13 as in the conventional case, and the base of one transistor 11 is connected to the input terminal 4 to which one of the differential input signals 1nl is supplied. The base of the other transistor 12 is connected to the input terminal 15 to which the other input signal in2 is supplied. The collectors of both transistors 11 and 12 are connected to output terminals 1G and 17. The output terminals 16 and 17 are connected to a power supply via an appropriate load (not shown), and output signals are taken out from the output terminals 1B and 17 in a differential format. In addition, a current source 1 is connected to the emitters of both transistors 11 and 12.
8 and 19 are connected to each other.

Further, the base of the pnp transistor 20 and the collector of the pnp transistor 21 are connected to the emitter of the transistor 11, and the emitter of the transistor 12 is connected to the base of the pnp transistor 2 and the collector of the pnp transistor 21.
The collector of np transistor 20 is connected.

The emitters of the pnp) transistors 20 and 21 are connected in common, and one end of a current source 22 is connected to this emitter common connection point.

In the differential circuit configured in this way, a pair of pnp transistors 2 whose bases and collectors are cross-connected are used.
Since the negative impedance circuit 23 consisting of 0 and 21 is inserted between the emitters of the pair of transistors 11 and 12 constituting the differential pair 13, the differential amplification gain is high as in the conventional circuit. ing. Moreover, a pair of transistors 2 constituting the negative impedance circuit 23
The collector and emitter current paths of the pair of transistors 11 and 12 forming the differential pair 13 are parallel to each other. Therefore, transistors 11 and 1
If the base bias voltage of No. 2 is set to a value that is higher than the base-emitter voltage of one transistor from the current source 18 or 19, normal operation will occur. As a result, in this embodiment circuit, it is possible to improve the utilization efficiency of the power supply voltage, and furthermore, it is possible to achieve an improvement in the common mode input range.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a differential circuit that has high power supply voltage utilization efficiency and can improve the common-mode input range.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a differential circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional circuit. 11, 12... npn transistor, 13... differential pair, 14, 15... input terminal, 18.17... output terminal, 18.19° 22... current source, 20.21.
...pnp'r-transistor, 23...negative impedance circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] a first polarity transistor having a base supplied with one input signal and having one output signal taken from the collector; a third transistor of the other polarity, the base of which is connected to the emitter of the second transistor, and the collector of which is connected to the emitter of the first transistor; and a third transistor of the other polarity, whose base is connected to the emitter of the first transistor. a fourth transistor of the other polarity, the collector of which is connected to the emitter of the second transistor, and the emitter of which is commonly connected to the emitter of the third transistor; a first constant current means connected to the emitter; a second constant current means having one end connected to the emitter of the second transistor; and one end connected to the common emitter of the third and fourth transistors. The third
A differential circuit characterized by comprising: constant current means.