JPH03277004A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To reduce an input offset voltage by providing a transistor(TR) whose emitter is connected to a current output terminal of a current mirror circuit and whose collector is connected to an output terminal of a differential amplifier circuit so as to make a level of a current input terminal of the current mirror circuit substantially equal to a level of an output terminal of the current mirror circuit. CONSTITUTION:A potential of the collector of a TR Q2 depends on the base voltage of a TR Q5, and the base voltage is a voltage resulting from a power supply voltage VCC subtracted by two base.emitter voltage (2XVBE). Since the collector potential of the TR Q2 is boosted by the base.emitter voltage VBE from the base voltage of the TR Q5, then equal to (VCC-VBE) and the collector.emitter voltage of both the TRs Q1, Q2 is equal to each other. Thus, no early effect is caused and the collector current of the TR Q1 and that of the TR Q2 at no signal input are equal to each other. Thus, the matching of the collector current of the TRs Q3, Q4 being components of a differential input stage is improved by the operation above and an input offset voltage is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor circuit, and particularly to a semiconductor circuit including a differential amplifier circuit having a current mirror circuit as an active load.

[Conventional technology]

Conventionally, there is a semiconductor circuit as shown in FIG. 3 including this type of differential amplifier circuit. In FIG. 3, transistors Ql and Q2 constitute a current mirror circuit 10, their bases are commonly connected, and their emitters are both connected to the power supply voltage V. Connected to 0. The collector and base of transistor Q1 are commonly connected and act as a current input terminal, and the collector of transistor Q2 acts as a current output terminal. Transistor Q3. Q4 is connected differentially. That is, the base of the transistor Q3 is connected to the common-mode input terminal 1, the emitter is grounded via the constant current source 1, and the collector is connected to the current input terminal of the current mirror circuit (the collector and base connection point of the transistor Q1).
It is connected to the.

The base of the transistor Q4 is connected to the negative phase input terminal 2, the collector is connected to the current output terminal of the current mirror circuit (collector of the transistor Q2), and the emitter is connected to the emitter of the transistor Q3. The collector of the transistor Q4 is taken out as an output terminal of a differential amplifier circuit composed of transistors Ql-Q4, and the collector is connected to the power supply voltage V. 0, the emitter is a constant current source I2. The signals are further supplied to the signal output terminal 3 via emitter follower transistors Q6 connected to the respective terminals. This circuit amplifies a signal supplied between input terminals 1 and 2 and outputs it from an output terminal 3 of the semiconductor circuit.

[Problem to be solved by the invention]

However, the above-described conventional differential amplifier circuit having the current mirror circuit as an active load has a drawback of having a large input offset voltage.

That is, since the base and collector of the transistor Q1 constituting the current mirror circuit 10 are commonly connected, the collector potential of the transistor Q1 is a voltage lower than the power supply voltage VCC by the base-emitter voltage Vat of the transistor Q1 (Vcc VnJ). .

On the other hand, the collector voltage of the transistor Q2 is determined by the DC voltage at the output terminal 3, and is a voltage that is higher than the DC voltage by the base-emitter voltage v0 of the transistor Q6. Generally, the DC voltage of the output 3 is the power supply voltage V from the viewpoint of the power supply voltage utilization rate of the amplified output signal with respect to the input signal. Since it is set to half of C, transistor Q2
The collector voltage of is (V cc/ 2 +V BE). VBE is about 0.7 V, and VCC is much larger than VBE at 5 V or 12 V, so the collector-emitter voltage of transistor Q1 is not equal to the collector-emitter voltage of transistor Q2, and the latter is higher. big. Therefore, due to the so-called Early effect, even though the area ratio of the transistors Ql and Q2 is set so that the current ratio of the current mirror circuit 10 is "1", the collector current of the transistor Q2 is It's even more fun than Q1. The collector currents of transistors Ql and Q2 are respectively the same as transistor Q3.
．． Since it is the collector current of Q4, the transistor Ql,
The above-described difference in collector current between Q2 means that the DC voltage at input terminal 2 is larger than the DC voltage at input terminal 1, resulting in an input offset voltage.

Moreover, the collector voltages of the transistors Ql and Q2 are the same as those of the transistor Q3. Q4's collector voltage, and transistor Q3. Since the emitter and terminal of transistor Q4 are commonly connected, transistors Q3. Q4 collector/
There is a difference in emitter voltage. Transistor Q3
．． Regarding Q4, since the collector voltage of transistor Q3 is higher than that of transistor Q4, transistor Q4 has a smaller collector current supply capability than Q3. On the other hand, since the collector current of transistor Q2 is larger than that of transistor Q1 as described above,
In order to increase the collector current of transistor Q4,
It becomes necessary to make the DC voltage at input terminal 2 even larger than that at input terminal l, and the input offset voltage becomes even larger.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor circuit including a differential amplifier circuit having a current mirror circuit as an active load, which has a reduced input offset voltage.

[Means to solve the problem]

According to the present invention, a transistor is provided whose emitter is connected to the current output terminal of the current mirror circuit and whose collector is connected to the output terminal of the differential amplifier circuit, and the base of this transistor is connected to the current input terminal and current output terminal of the current mirror circuit. A semiconductor circuit is obtained in which a voltage is applied that makes the potentials of terminals substantially equal.

[Effect]

According to this configuration, the electric potentials of the current input and output terminals of the current mirror circuit become substantially equal due to the insertion of the transistor, and the input/output current ratio becomes substantially 1. Therefore, its needle input offset voltage is improved and reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In addition, the third
Components common to those in the figures are given the same numbers and their explanations will be omitted.

In this embodiment, a PNP transistor Q5 is further provided, and its collector is connected to the collector of the transistor Q4 and the base of the transistor Q6, and its emitter is connected to the collector of the transistor Q2, which serves as the current output terminal of the current mirror circuit 10. , the base is connected to the collector of transistor Q6. Furthermore, the potential of the current input terminal and current output terminal of the current mirror circuit IO (i.e., the collector potential of transistors Ql and Q2)
Two diodes D1 and D2 are connected in series with the polarities shown between the base of transistor Q5 and VCC to make them substantially equal.

That is, the anode of the diode D1 is connected to the power supply voltage voo
The cathode of the diode D2 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the base of the transistor Q5 and the collector of the transistor Q6. Note that the diodes D1 and D2 are as follows:
Transistors Ql, Q2. Similar to Q5, the base-emitter junction of a PNP (PNP) Lancistor is used (the collector and base are shorted). According to this configuration, the transistor Q2
The potential of the collector of is determined by the base voltage of transistor Q5, and the base voltage is the power supply voltage V. C to 2
The forward voltage of one diode, that is, the voltage lowered by the base-emitter voltage v3 of two transistors. Since the collector potential of transistor Q2 is raised from the base voltage of transistor Q5 by its base-emitter voltage ■B8, (Vcc
As a result, the collector potentials of transistors Q1 and Q2, and therefore the collector-emitter voltages of both transistors, become equal. Therefore, the Early effect does not occur, and the collector currents of transistors Q1 and Q2 when no signal is present are equal to each other. Since the collector currents of transistors Q1 and Q2 are equal, the matching of the collector currents of transistors Q3 and Q4 forming the differential input stage is improved accordingly, and the input offset voltage is reduced, compared to the conventional example.

In this embodiment, as in the conventional example, the collector voltage of the transistor Q4 is lower than that of Q3, but the collector current of the transistor Q2 is smaller than in the conventional example, and a part of the collector current is the base current of the transistor Q5. Since the difference current is supplied to the collector of transistor Q4, the matching is further improved and the input offset voltage is further reduced.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

In this embodiment, the collector of the transistor Q6 is connected to the power supply voltage V. 0, and a constant current source (3) is set up with one end connected to the base of the transistor Q5 and the cathode of the diode D2, and the other end connected to the ground GND.

According to this configuration, by setting the current value of the constant current source 2 to half of the constant current source 1, the differential pair transistor Q3. Q
When transistor Q4 is balanced, the current flowing between the collector and emitter of transistor Q5 is equal to the current flowing through diodes DI and D2, and the matching accuracy of the collector potentials of transistors Q1 and Q2 is higher than that of the embodiment shown in FIG. 1, resulting in a current mirror. Circuit mismatch can be further reduced. Therefore, the input offset voltage can be further reduced.

Note that in the above embodiment, there are two transistors Ql.

Although a current mirror circuit based on Q2 is used, a current mirror circuit having another configuration may be used. For example, the present invention can also be implemented using a current mirror circuit having a configuration in which a third PNP type transistor is added to the base of the emitter-cut transistor Q1, the base of which is connected to the collector of the transistor, and the collector of which is connected to GND. In this case, the potential of the current input terminal of the current mirror circuit is (VCC2Va
Therefore, a voltage (Vcc 3VBE) is applied to the base of transistor Q5 to make it equal to the potential of the current output terminal.
) can be applied.

〔Effect of the invention〕

As explained above, the semiconductor circuit according to the present invention includes a differential amplifier circuit having a current mirror circuit as an active load, in which the emitter is connected to the current output terminal of the current mirror circuit and the collector is connected to the differential amplifier circuit. A current input terminal of the current mirror circuit is provided by providing a transistor connected to an output terminal of the circuit, and applying a voltage to the base of the transistor to substantially equalize the potentials of the current input terminal and the current output terminal of the current mirror circuit. Since the potential of the current output terminal of the current mirror circuit is clamped to be equal to the potential of effective. Furthermore, the output current from the current output terminal of the current mirror circuit passes between the emitter and collector of the transistor, and is supplied to the output terminal of the differential amplifier circuit as a smaller current by subtracting the current flowing through the base of the transistor. Furthermore, it also has the effect of reducing offset voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the semiconductor circuit of the present invention, and FIG.
This figure is a circuit diagram of another embodiment of the semiconductor circuit of the present invention, and FIG. 3 is a circuit diagram of a conventional semiconductor circuit. 1 is the in-phase input terminal, 2 is the negative-phase input terminal, 3 is the pressure terminal of the semiconductor circuit, 10 is the current mirror circuit, Dl and D
l is a diode, 1 to 3 are constant current sources, Ql to Q
6 is a transistor, voo is a power supply voltage, and GND is a ground.

Claims (1)

[Claims] In a semiconductor circuit including a differential amplifier circuit having a current mirror circuit as an active load, a transistor is provided whose emitter is connected to the current output terminal of the current mirror circuit and whose collector is connected to the output terminal of the differential amplifier circuit; A semiconductor circuit, characterized in that a voltage is applied to the base of the transistor to make the potentials of the current input terminal and the current output terminal of the current mirror circuit substantially equal.